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CycleForge

Python License RISC-V

A cycle-accurate simulator for 32-bit RISC-V processors built in Python. Models precise execution timing and pipeline behavior for performance analysis and architectural research.

🚀 Features

  • 🔄 Cycle-Accurate Execution Modeling

    • Precise timing simulation
    • Detailed pipeline stage tracking
    • Accurate instruction execution timing
  • 🏗️ Complete 32-bit RISC-V ISA Support

    • RV32I base integer instruction set
    • Standard extensions support
    • Comprehensive instruction coverage
  • Pipeline Simulation

    • Multi-stage pipeline modeling
    • Hazard detection and handling
    • Branch prediction support
  • 📊 Performance Analysis

    • Detailed execution statistics
    • Pipeline utilization metrics
    • Performance bottleneck identification

📋 Requirements

  • Python 3.8 or higher
  • Required Python packages (see requirements.txt)

🛠️ Installation

# Clone the repository
git clone https://github.com/yourusername/CycleForge.git

# Navigate to project directory
cd CycleForge

# Install dependencies
pip install -r requirements.txt

🎮 Usage

# Example usage code will be added here

📝 License

This project is licensed under the MIT License - see the LICENSE file for details.

🤝 Contributing

Contributions are welcome! Please feel free to submit a Pull Request.

📧 Contact

For questions and support, please open an issue in the GitHub repository.

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A cycle-accurate simulator for 32-bit RISC-V processors built in Python.

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