Add instruction set detection for SVE_AES, SVE_SHA3, SVE_SM4, SHA3, SM4#124637
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a74nh wants to merge 12 commits intodotnet:mainfrom
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Add instruction set detection for SVE_AES, SVE_SHA3, SVE_SM4, SHA3, SM4#124637a74nh wants to merge 12 commits intodotnet:mainfrom
a74nh wants to merge 12 commits intodotnet:mainfrom
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Mostly a copy/paste of dotnet#115117
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Tagging subscribers to this area: @JulieLeeMSFT, @jakobbotsch |
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Pull request overview
Adds end-to-end ARM64 instruction set detection and plumbing for SHA3/SM4 and SVE crypto extensions so the runtime/JIT/R2R toolchain can recognize and gate these features consistently across platforms.
Changes:
- Extend
minipal_getcpufeaturesto detect SHA3/SM4 and SVE AES/SHA3/SM4 (Linux hwcaps, Applesysctlbyname, WindowsIsProcessorFeaturePresent). - Add new ARM64 instruction sets (including R2R IDs/implications) and propagate them through CoreCLR instruction-set enums and helpers.
- Gate JIT enablement via new CLRConfig/JitConfig switches and wire feature bits into EE JIT compile flags.
Reviewed changes
Copilot reviewed 15 out of 15 changed files in this pull request and generated 2 comments.
Show a summary per file
| File | Description |
|---|---|
| src/native/minipal/cpufeatures.h | Adds new ARM64 feature-bit constants for SHA3/SM4 and SVE crypto extensions. |
| src/native/minipal/cpufeatures.c | Detects new ARM64 capabilities via HWCAP/HWCAP2, sysctl, and Windows PF_* flags. |
| src/coreclr/vm/codeman.cpp | Sets CPU compile flags for new instruction sets, gated by CLRConfig switches. |
| src/coreclr/tools/Common/JitInterface/ThunkGenerator/InstructionSetDesc.txt | Registers new ARM64 instruction sets, R2R bits, and ISA implications. |
| src/coreclr/tools/Common/JitInterface/CorInfoInstructionSet.cs | Updates managed instruction-set enums and implication handling for new ARM64 ISAs. |
| src/coreclr/tools/Common/Internal/Runtime/ReadyToRunInstructionSetHelper.cs | Maps new ARM64 instruction sets to R2R instruction set IDs. |
| src/coreclr/tools/Common/Internal/Runtime/ReadyToRunInstructionSet.cs | Adds new R2R instruction set enum values for ARM64 SHA3/SM4 and SVE crypto. |
| src/coreclr/jit/jitconfigvalues.h | Introduces JIT config toggles for enabling/disabling the new ARM64 ISAs. |
| src/coreclr/jit/hwintrinsicarm64.cpp | Adds name-to-instruction-set and Arm64-variant mapping for new ISAs. |
| src/coreclr/jit/hwintrinsic.cpp | Extends ISA range table to include the new ARM64 instruction sets. |
| src/coreclr/jit/compiler.cpp | Enables new ARM64 instruction sets in “enable available ISAs” flow based on JitConfig. |
| src/coreclr/inc/readytoruninstructionset.h | Adds new R2R instruction set IDs on the native side. |
| src/coreclr/inc/jiteeversionguid.h | Bumps JIT/EE version GUID due to instruction-set enum changes. |
| src/coreclr/inc/corinfoinstructionset.h | Extends CORINFO instruction-set enums/validation/mappings for new ARM64 ISAs. |
| src/coreclr/inc/clrconfigvalues.h | Adds CLRConfig switches to gate the new ARM64 ISAs. |
Co-authored-by: Copilot <175728472+Copilot@users.noreply.github.com>
Co-authored-by: Copilot <175728472+Copilot@users.noreply.github.com>
Co-authored-by: Copilot <175728472+Copilot@users.noreply.github.com>
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Author
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@dotnet/arm64-contrib |
This was referenced Feb 20, 2026
Open
This was referenced Feb 26, 2026
| { NI_Illegal, NI_Illegal }, // Atomics | ||
| { FIRST_NI_Vector64, LAST_NI_Vector64 }, // Vector64 | ||
| { FIRST_NI_Vector128, LAST_NI_Vector128 }, // Vector128 | ||
| { NI_Illegal, NI_Illegal }, // VectorT |
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I assume that six-spaces after the // in this file means its NYI (like the Sha3, Sm4 below you added, other examples)
if so can you apply that here as well to VectorT while you're in here? Sorry for the nit
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The changes to the jit all lgtm |
dhartglassMSFT
approved these changes
Mar 10, 2026
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Mostly a copy/paste of #115117