Add support for passing 128 and 32 bit HFA args to call stubs on arm64#121037
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janvorli merged 4 commits intodotnet:mainfrom Oct 24, 2025
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The interpreter call stubs were missing support for HFA 128 bit args passing. That was causing a lot of failures in the HardwareIntrinsics coreclr tests on macOS arm64. With this change, the results basically match the x64 Windows.
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Pull Request Overview
This PR adds support for passing 128-bit homogeneous floating-point aggregate (HFA) arguments in Q registers on ARM64, which was previously missing from the interpreter call stubs. This change resolves failures in HardwareIntrinsics CoreCLR tests on macOS ARM64 by enabling proper handling of Vector128 types passed as function arguments.
Key Changes:
- Added new
FPReg128routine type to handle 128-bit floating-point register arguments - Implemented Q register load/store routines in ARM64 assembly (both MASM and GAS syntax)
- Enhanced argument processing logic to detect and route 128-bit HFA arguments appropriately
Reviewed Changes
Copilot reviewed 4 out of 4 changed files in this pull request and generated 4 comments.
| File | Description |
|---|---|
| src/coreclr/vm/callstubgenerator.h | Moved RoutineType enum earlier in class definition and added FPReg128 type along with tracking field and method declarations |
| src/coreclr/vm/callstubgenerator.cpp | Added Q register routine tables, implemented GetFPReg128RangeRoutine(), and updated argument processing to handle 128-bit float arguments |
| src/coreclr/vm/arm64/asmhelpers.asm | Added ARM64 MASM assembly routines for loading/storing Q registers (128-bit SIMD registers) |
| src/coreclr/vm/arm64/asmhelpers.S | Added ARM64 GAS assembly routines for loading/storing Q registers (128-bit SIMD registers) |
kg
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Oct 23, 2025
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Oct 23, 2025
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The interpreter call stubs were missing support for HFA 128 bit and 32 bit args passing. That was causing a lot of failures in the HardwareIntrinsics coreclr tests on macOS arm64.
With this change, the results basically match the x64 Windows.