The reverse engineering document (https://dougallj.github.io/applecpu/firestorm.html) does not indicate that M1 recognizes eor v0,v0,v0 as a zeroing idiom (like an x64 CPU would). Instead, there is the movi instruction (https://developer.arm.com/documentation/dui0801/l/A64-SIMD-Vector-Instructions/MOVI--vector---A64-?lang=en) that can initialize all lanes of a SIMD vector. Dougall Johnson's document shows that for zero, this is internally resolved with register renaming.

Also use this for OP_XONES.