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RyuJIT: dangling instructions after converting modulus to bitwise AND #4353

@omariom

Description

@omariom

Looks like after optimization a few instructions left dangling.

[MethodImpl(MethodImplOptions.NoInlining)]
 public static uint Test(uint v)
 {
       return v % 8;
 }

[MethodImpl(MethodImplOptions.NoInlining)]
public static uint Test2(uint v)
{
    return v & 7;
}
;Test
G_M65206_IG02:
       8BC1                 mov      eax, ecx
       33D2                 xor      rdx, rdx
       8BC1                 mov      eax, ecx
       83E007               and      eax, 7
G_M65206_IG03:
       C3                   ret 

;Test2
G_M65206_IG02:
       8BC1                 mov      eax, ecx
       83E007               and      eax, 7
G_M65206_IG03:
       C3                   ret   

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area-CodeGen-coreclrCLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMIoptimization

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