This is currently supported in a limited form for Arm32 double registers, which must be an even/odd pair. However, this support is not well structured, and penalizes the common path that requires only a single register.
In order to support the Arm64 LoadPairVector intrinsics (#39243) intrinsics that would correspond to LD1-LD4, ST1-ST4 instruction, we need the ability to allocate consecutive vector registers, and we don't want to penalize the common path for this case.
One option would be to templatize the allocation methods such that the ones supporting consecutive registers would only be called when required.
Related: issue #8758 would presumably be addressed by such an approach.

category:proposal
theme:register-allocator
skill-level:expert
cost:large
impact:medium