Summary:
3152 ARM64 HW intrinsic test failures across all jitstress2_jitstressregs modes (0x80, 8, 1, 3) on linux, windows, and osx. All failures occur in the RunReflectionScenario_UnsafeRead scenario. Affected operations include BySelectedScalar (1674), ShiftLeftAndInsert (324), ShiftRightAndInsert (210), BySelectedQuadruplet (36), and Sve2 shift/multiply operations. Non-reflection scenarios (BasicScenario, LclVarScenario, ClassFldScenario, StructFldScenario) pass.
Failed in (1):
Console Log: Console Log
Error Message:
Arm64.FusedMultiplyAddBySelectedScalar<Single>(Vector64<Single>, Vector64<Single>, Vector128<Single>): RunReflectionScenario_UnsafeRead failed:
firstOp: (0.2073351, 0.2636208)
secondOp: (0.7460422, 0.16575699)
System.Exception: One or more scenarios did not complete as expected.
Stack Trace:
at JIT.HardwareIntrinsics.Arm._AdvSimd.Arm64.Program.FusedMultiplyAddBySelectedScalar_Vector64_Single_Vector128_Single_3() in gen/FusedMultiplyAddBySelectedScalar.Vector64.Single.Vector128.Single.3.cs:line 61
Analysis:
Root cause: The JIT generates incorrect code for ARM64 hardware intrinsic methods when invoked via reflection (RunReflectionScenario_UnsafeRead) under JitStress2 + JitStressRegs stress modes. The reflection path goes through a different JIT compilation path that is sensitive to register allocation stress. The failures are consistent across all arm64 platforms (linux, windows, osx) and all jitstressregs modes (0x80, 8, 1, 3), producing wrong results (not crashes). The affected intrinsics span AdvSimd, AdvSimd.Arm64, Rdm, Rdm.Arm64, Dp, and Sve2 instruction sets. No existing GitHub issue found matching this pattern.
Summary:
3152 ARM64 HW intrinsic test failures across all jitstress2_jitstressregs modes (0x80, 8, 1, 3) on linux, windows, and osx. All failures occur in the RunReflectionScenario_UnsafeRead scenario. Affected operations include BySelectedScalar (1674), ShiftLeftAndInsert (324), ShiftRightAndInsert (210), BySelectedQuadruplet (36), and Sve2 shift/multiply operations. Non-reflection scenarios (BasicScenario, LclVarScenario, ClassFldScenario, StructFldScenario) pass.
Failed in (1):
Console Log: Console Log
Error Message:
Stack Trace:
Analysis:
Root cause: The JIT generates incorrect code for ARM64 hardware intrinsic methods when invoked via reflection (RunReflectionScenario_UnsafeRead) under JitStress2 + JitStressRegs stress modes. The reflection path goes through a different JIT compilation path that is sensitive to register allocation stress. The failures are consistent across all arm64 platforms (linux, windows, osx) and all jitstressregs modes (0x80, 8, 1, 3), producing wrong results (not crashes). The affected intrinsics span AdvSimd, AdvSimd.Arm64, Rdm, Rdm.Arm64, Dp, and Sve2 instruction sets. No existing GitHub issue found matching this pattern.