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area-CodeGen-coreclrCLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMICLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMIos-linuxLinux OS (any supported distro)Linux OS (any supported distro)os-mac-os-xmacOS aka OSXmacOS aka OSXruntime-async
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ELF file format doesn't like relocs from RO sections to text sections (error : relocation R_X86_64_64 cannot be used against symbol 'Internal_CompilerGenerated__Module___<Resume>valuetask_source_Async2ValueTaskSource__<AsyncCallable>valuetask_source_Async2ValueTaskSource__AwaitConfigDefault'; recompile with -fPIC)
So for ELF (and maybe Mach-O?) these need to go to a different blob.
This would require the JIT to know that ELF needs to place these in a R/W section (but e.g. PE is fine with it as-is)
If we were to design this as native first scheme, we would not have this structure and two different IPs at all. We ended up with a trade-off and these warts are needed to make this trade-off work well.
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area-CodeGen-coreclrCLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMICLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMIos-linuxLinux OS (any supported distro)Linux OS (any supported distro)os-mac-os-xmacOS aka OSXmacOS aka OSXruntime-async
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