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Branch target alignment on Apple Silicon #107284

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Branch target alignment on Apple Silicon#107284
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arch-arm64area-CodeGen-coreclrCLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMIos-iosApple iOSos-mac-os-xmacOS aka OSX
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@filipnavara

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@filipnavara
filipnavara
opened on Sep 3, 2024

PR #59828 started enforcing 32-byte alignment for methods with loops on ARM64 based on the Neoverse N1 optimization guide:

runtime/src/coreclr/jit/emit.cpp

Lines 6775 to 6785 in 16fe4d4

#if defined(TARGET_XARCH) || defined(TARGET_ARM64)
// For x64/x86/arm64, align methods that are "optimizations enabled" to 32 byte boundaries if
// they are larger than 16 bytes and contain a loop.
//
if (emitComp->opts.OptimizationEnabled() &&
(!emitComp->opts.jitFlags->IsSet(JitFlags::JIT_FLAG_PREJIT) || comp->IsTargetAbi(CORINFO_NATIVEAOT_ABI)) &&
(emitTotalHotCodeSize > 16) && emitComp->fgHasLoops)
{
codeAlignment = 32;
}
#endif

This goes contrary to the Apple Silicon CPU Optimization Guide, section 4.4.3 Branch Target Alignment. Apple specifically states that software alignment of branch targets is unnecessary and sometimes detrimental due to the alignment capabilities of the processor. The guidance is to not align branch targets and favor smaller code size.

Aside for performance implications this alignment makes the size of NativeAOT code on iOS/macOS bigger due to unnecessary alignment.

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