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Legalize imul.i64x2 for both AVX and non-AVX x86 CPUs#1759

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abrown merged 9 commits intobytecodealliance:masterfrom
abrown:i64x2-mul
Jun 3, 2020
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Legalize imul.i64x2 for both AVX and non-AVX x86 CPUs#1759
abrown merged 9 commits intobytecodealliance:masterfrom
abrown:i64x2-mul

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@abrown abrown commented May 26, 2020

The convert_i64x2_imul custom legalization checks the ISA flags for AVX512DQ or AVX512VL support and legalizes imul.i64x2 to an x86_pmullq in this case; if not, it uses a lengthy SSE2-compatible instruction sequence. For this logic to work, we need:

  • the AVX512 instruction to be defined as a separate Cranelift instruction, x86_pmullq (this additional instruction would go away in the new backend)
  • a mechanism for accessing the x86 TargetIsa so that we can inspect its flags during legalization
  • a new SSE2 instruction, x86_pmuludq for implementing the SSE2-compatible instruction sequence

@abrown abrown force-pushed the i64x2-mul branch 2 times, most recently from e48a82c to fdcfd1c Compare May 26, 2020 17:11
@github-actions github-actions bot added cranelift Issues related to the Cranelift code generator cranelift:area:aarch64 Issues related to AArch64 backend. cranelift:area:x64 Issues related to x64 codegen cranelift:meta Everything related to the meta-language. labels May 26, 2020
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Looks pretty good! I wonder if the legalization couldn't be done in the meta-language directly using an ISA predicate (and thus avoiding the Any and downcasting).

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Unless guarding-legalizations-against-ISA-settings is easy to implement, the proposed approach here works fine. Thanks for the patch!

abrown added 9 commits June 3, 2020 15:13
Without this special instruction, legalizing to the AVX512 instruction AND the SSE instruction sequence is impossible. This extra instruction would be rendered unnecessary by the x64 backend.
This is necessary when we would like to check specific ISA flags, e.g.
This instruction multiplies the lower 32 bits of two 64x2 unsigned integers into an i64x2; this is necessary for lowering Wasm's i64x2.mul.
This instruction does not exist in the SSE2 feature set; it can be added later with an VEX/EVEX encoding.
The `convert_i64x2_imul` custom legalization checks the ISA flags for AVX512DQ or AVX512VL support and legalizes `imul.i64x2` to an `x86_pmullq` in this case; if not, it uses a lengthy SSE2-compatible instruction sequence.
@abrown abrown merged commit 5db384c into bytecodealliance:master Jun 3, 2020
@abrown abrown deleted the i64x2-mul branch June 3, 2020 23:28
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