Minor cleanups

saulecabrera · saulecabrera · commit e18681c3b716 · 2024-07-16T09:35:46.000-04:00
This commit includes very minor clean-ups, these are mechanical changes
only.

* Rename `shift_rr` to `shift`, as we're still passing the context in,
  the callee can decide what to do with the instruction arguments.

* Delete the un-used `Into&lt;AluOp&gt; for ShiftKind`
diff --git a/winch/codegen/src/codegen/context.rs b/winch/codegen/src/codegen/context.rs
@@ -341,7 +341,7 @@ impl<'a> CodeGenContext<'a> {
             );
             self.stack.push(typed_reg.into());
         } else {
-            masm.shift_rr(self, kind, OperandSize::S32);
+            masm.shift(self, kind, OperandSize::S32);
         }
     }
 
@@ -366,7 +366,7 @@ impl<'a> CodeGenContext<'a> {
             );
             self.stack.push(typed_reg.into());
         } else {
-            masm.shift_rr(self, kind, OperandSize::S64);
+            masm.shift(self, kind, OperandSize::S64);
         };
     }
 
diff --git a/winch/codegen/src/isa/aarch64/asm.rs b/winch/codegen/src/isa/aarch64/asm.rs
@@ -29,19 +29,6 @@ impl From<OperandSize> for inst::OperandSize {
     }
 }
 
-impl Into<ALUOp> for ShiftKind {
-    fn into(self) -> ALUOp {
-        match self {
-            ShiftKind::Shl => ALUOp::Lsl,
-            ShiftKind::ShrS => ALUOp::Asr,
-            ShiftKind::ShrU => ALUOp::Lsr,
-            ShiftKind::Rotr => ALUOp::RotR,
-            // Rotl is implemented as neg+ROR.
-            ShiftKind::Rotl => unimplemented!(),
-        }
-    }
-}
-
 impl Into<ScalarSize> for OperandSize {
     fn into(self) -> ScalarSize {
         match self {
diff --git a/winch/codegen/src/isa/aarch64/masm.rs b/winch/codegen/src/isa/aarch64/masm.rs
@@ -405,8 +405,7 @@ impl Masm for MacroAssembler {
         self.asm.shift_ir(imm, lhs, dst, kind, size)
     }
 
-    fn shift_rr(&mut self, context: &mut CodeGenContext, kind: ShiftKind, size: OperandSize) {
-        // Number of bits to shift must be in the CL register.
+    fn shift(&mut self, context: &mut CodeGenContext, kind: ShiftKind, size: OperandSize) {
         let src = context.pop_to_reg(self, None);
         let dst = context.pop_to_reg(self, None);
 
diff --git a/winch/codegen/src/isa/x64/masm.rs b/winch/codegen/src/isa/x64/masm.rs
@@ -535,7 +535,7 @@ impl Masm for MacroAssembler {
         self.asm.shift_ir(imm as u8, dst, kind, size)
     }
 
-    fn shift_rr(&mut self, context: &mut CodeGenContext, kind: ShiftKind, size: OperandSize) {
+    fn shift(&mut self, context: &mut CodeGenContext, kind: ShiftKind, size: OperandSize) {
         // Number of bits to shift must be in the CL register.
         let src = context.pop_to_reg(self, Some(regs::rcx()));
         let dst = context.pop_to_reg(self, None);
diff --git a/winch/codegen/src/masm.rs b/winch/codegen/src/masm.rs
@@ -704,7 +704,7 @@ pub(crate) trait MacroAssembler {
     /// caller from having to deal with the architecture specific constraints
     /// we give this function access to the code generation context, allowing
     /// each implementation to decide the lowering path.
-    fn shift_rr(&mut self, context: &mut CodeGenContext, kind: ShiftKind, size: OperandSize);
+    fn shift(&mut self, context: &mut CodeGenContext, kind: ShiftKind, size: OperandSize);
 
     /// Perform division operation.
     /// Division is special in that some architectures have specific

Original file line number	Diff line number	Diff line change
`@@ -341,7 +341,7 @@ impl<'a> CodeGenContext<'a> {`
`341`	`341`	`);`
`342`	`342`	`self.stack.push(typed_reg.into());`
`343`	`343`	`} else {`
`344`		`- masm.shift_rr(self, kind, OperandSize::S32);`
	`344`	`+ masm.shift(self, kind, OperandSize::S32);`
`345`	`345`	`}`
`346`	`346`	`}`
`347`	`347`
`@@ -366,7 +366,7 @@ impl<'a> CodeGenContext<'a> {`
`366`	`366`	`);`
`367`	`367`	`self.stack.push(typed_reg.into());`
`368`	`368`	`} else {`
`369`		`- masm.shift_rr(self, kind, OperandSize::S64);`
	`369`	`+ masm.shift(self, kind, OperandSize::S64);`
`370`	`370`	`};`
`371`	`371`	`}`
`372`	`372`
Original file line number	Diff line number	Diff line change
`@@ -405,8 +405,7 @@ impl Masm for MacroAssembler {`
`405`	`405`	`self.asm.shift_ir(imm, lhs, dst, kind, size)`
`406`	`406`	`}`
`407`	`407`
`408`		`- fn shift_rr(&mut self, context: &mut CodeGenContext, kind: ShiftKind, size: OperandSize) {`
`409`		`- // Number of bits to shift must be in the CL register.`
	`408`	`+ fn shift(&mut self, context: &mut CodeGenContext, kind: ShiftKind, size: OperandSize) {`
`410`	`409`	`let src = context.pop_to_reg(self, None);`
`411`	`410`	`let dst = context.pop_to_reg(self, None);`
`412`	`411`
Original file line number	Diff line number	Diff line change
`@@ -535,7 +535,7 @@ impl Masm for MacroAssembler {`
`535`	`535`	`self.asm.shift_ir(imm as u8, dst, kind, size)`
`536`	`536`	`}`
`537`	`537`
`538`		`- fn shift_rr(&mut self, context: &mut CodeGenContext, kind: ShiftKind, size: OperandSize) {`
	`538`	`+ fn shift(&mut self, context: &mut CodeGenContext, kind: ShiftKind, size: OperandSize) {`
`539`	`539`	`// Number of bits to shift must be in the CL register.`
`540`	`540`	`let src = context.pop_to_reg(self, Some(regs::rcx()));`
`541`	`541`	`let dst = context.pop_to_reg(self, None);`