HPU (Intel Gaudi) support for bitsandbytes#1592
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Authored by: Chetan Kumar Verma <chetan.kumar.verma@intel.com> Co-authored-by: Ruheena Suhani Shaik <ruheena.suhani.shaik@intel.com> Co-authored-by: Bhargav Eede <bhargav.eede@intel.com> Co-authored-by: Vivek Goel <vivek.goel@intel.com>
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@jiqing-feng @Titus-von-Koeller Please help review these changes. These changes add support for NF4 quantization/dequantization using Intel Gaudi hardware. https://www.intel.com/content/www/us/en/products/details/processors/ai-accelerators/gaudi.html |
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The docs for this PR live here. All of your documentation changes will be reflected on that endpoint. The docs are available until 30 days after the last update. |
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bitsandbytes-foundation:multi-backend-refactor
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The code looks good, thanks for your work on this, a promising first step! Please see this short update about the multi-backend refactor #1596. Regarding the Intel backend, as discussed in parallel with Ke Ding, the target for PRs migrating existing work from However, some of the pure torch ops and generic cpu functionality still make more sense in the |
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@Titus-von-Koeller Thanks for reviewing and merging our PR! If possible, please add me to shared Slack channel you mentioned or if it needs to be done by someone in Intel team then let me know I will follow-up internally. |
This PR enables the support of bitsandbytes for HPU (Intel Gaudi) devices.
Authored by: Chetan Kumar Verma chetan.kumar.verma@intel.com
Co-authored-by: Ruheena Suhani Shaik ruheena.suhani.shaik@intel.com
Co-authored-by: Bhargav Eede bhargav.eede@intel.com
Co-authored-by: Vivek Goel vivek.goel@intel.com