DERCA is an accelerator architecture tailored for real-time safety critical systems.

Principal Investigator: Prof. Peipei Zhou, https://peipeizhou-eecs.github.io/

Ph.D. Students: Shixin Ji (Student Lead), Zhuoping Yang, Xingzhen Chen, Wei Zhang, Jinming Zhuang

Faculty Collaborators: Prof. Alex Jones (Syracuse University), Prof. Zheng Dong(Wayne State University)

Your support and growing engagement inspire us to continually improve and enhance DERCA

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DERCA provides a commandline tool script to reproduce the figures shown in the manuscript:

#install required packages, virtual env or conda recommended
pip install -r requirements.txt 
#reproduce figures
#/DERCA# 
python reproduce_fig.py --target fig11a
python reproduce_fig.py --target fig11b
python reproduce_fig.py --target fig11c
python reproduce_fig.py --target fig13

DERCA software stack takes (1) a task set and (2) the platform constraints as input, and generates the execution procedure of the taskset for execution.

the main steps of the DERCA software stack includes (1) parsing the input data, (2) enabling intra-layer preemption points, (3) conduct PP placement optimization and schedulability analysis, (4) simulation.

DERCA provides a commandline tool script to reproduce the figures shown in the manuscript:

#install required packages, virtual env or conda recommended
pip install -r requirements.txt 
#reproduce figures
#/DERCA# 
python reproduce_fig.py --target fig11a
python reproduce_fig.py --target fig11b
python reproduce_fig.py --target fig11c
python reproduce_fig.py --target fig13

For more detailed reproduce guide, please refer to the artifact evaluation guide

For more detailed explanation about the codes and workflow used in the software stack, please refer to the DERCA software readme file

DERCA use CHARM as the baseline accelerator, and we hand-tune the codes for our proposed imporvements. The environment configuration of DERCA is the same as CHARM:

• Vitis: 2021.1
• Petalinux: xilinx-versal-common-v2021.1
• hardware platform: xilinx_vck190_base_202110_1.xpfm

Several artifacts representing each component and the whole system are/will be provided:

• example 1: implementation of recompute dataflow, controlled by CPU commands
• example 2: implementation of persist dataflow, controlled by CPU commands
• example 3 (under construction): implementation of flexible dataflow, controlled by CPU commands
• example 4 (under construction): scheduler & kernel management module design with dummy accelerator and task release module
• example 5 (under construction): Final flexible accelerator design