-
Notifications
You must be signed in to change notification settings - Fork 1.6k
Expand file tree
/
Copy patharm64_vector_table.S
More file actions
307 lines (241 loc) · 9.05 KB
/
arm64_vector_table.S
File metadata and controls
307 lines (241 loc) · 9.05 KB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
/****************************************************************************
* arch/arm64/src/common/arm64_vector_table.S
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "arm64_macro.inc"
#include "arch/irq.h"
#include "arm64_fatal.h"
/****************************************************************************
* Public Symbols
****************************************************************************/
.file "arm64_vector_table.S"
/****************************************************************************
* Assembly Macros
****************************************************************************/
/* Save Corruptible Registers and exception context
* on the task stack
* note: allocate stackframe with ARM64_CONTEXT_REGS
* which is ARM64_ESF_REGS + ARM64_CS_REGS
* but only save ARM64_ESF_REGS
*/
.macro arm64_enter_exception xreg0, xreg1
sub sp, sp, #8 * XCPTCONTEXT_REGS
stp x0, x1, [sp, #8 * REG_X0]
stp x2, x3, [sp, #8 * REG_X2]
stp x4, x5, [sp, #8 * REG_X4]
stp x6, x7, [sp, #8 * REG_X6]
stp x8, x9, [sp, #8 * REG_X8]
stp x10, x11, [sp, #8 * REG_X10]
stp x12, x13, [sp, #8 * REG_X12]
stp x14, x15, [sp, #8 * REG_X14]
stp x16, x17, [sp, #8 * REG_X16]
stp x18, x19, [sp, #8 * REG_X18]
stp x20, x21, [sp, #8 * REG_X20]
stp x22, x23, [sp, #8 * REG_X22]
stp x24, x25, [sp, #8 * REG_X24]
stp x26, x27, [sp, #8 * REG_X26]
stp x28, x29, [sp, #8 * REG_X28]
/* Save the current task's SP_ELx and x30 */
add \xreg0, sp, #8 * XCPTCONTEXT_REGS
stp x30, \xreg0, [sp, #8 * REG_X30]
/* ELR and SPSR */
#if CONFIG_ARCH_ARM64_EXCEPTION_LEVEL == 3
mrs \xreg0, elr_el3
mrs \xreg1, spsr_el3
#else
mrs \xreg0, elr_el1
mrs \xreg1, spsr_el1
#endif
stp \xreg0, \xreg1, [sp, #8 * REG_ELR]
mrs \xreg0, sctlr_el1
str \xreg0, [sp, #8 * REG_SCTLR_EL1]
mrs \xreg0, sp_el0
mrs \xreg1, tpidrro_el0
stp \xreg0, \xreg1, [sp, #8 * REG_SP_EL0]
/* Increment exception depth */
add \xreg1, \xreg1, #1
msr tpidrro_el0, \xreg1
/* Save the FPU registers */
#ifdef CONFIG_ARCH_FPU
add x0, sp, #8 * ARM64_CONTEXT_REGS
bl arm64_fpu_save
ldr x0, [sp, #8 * REG_X0]
#endif
.endm
/****************************************************************************
* Public Functions
****************************************************************************/
/* Four types of exceptions:
* - synchronous: aborts from MMU, SP/CP alignment checking, unallocated
* instructions, SVCs/SMCs/HVCs, ...)
* - IRQ: group 1 (normal) interrupts
* - FIQ: group 0 or secure interrupts
* - SError: fatal system errors
*
* Four different contexts:
* - from same exception level, when using the SP_EL0 stack pointer
* - from same exception level, when using the SP_ELx stack pointer
* - from lower exception level, when this is AArch64
* - from lower exception level, when this is AArch32
*
* +------------------+------------------+-------------------------+
* | Address | Exception type | Description |
* +------------------+------------------+-------------------------+
* | VBAR_ELn + 0x000 | Synchronous | Current EL with SP0 |
* | + 0x080 | IRQ / vIRQ | |
* | + 0x100 | FIQ / vFIQ | |
* | + 0x180 | SError / vSError | |
* +------------------+------------------+-------------------------+
* | + 0x200 | Synchronous | Current EL with SPx |
* | + 0x280 | IRQ / vIRQ | |
* | + 0x300 | FIQ / vFIQ | |
* | + 0x380 | SError / vSError | |
* +------------------+------------------+-------------------------+
* | + 0x400 | Synchronous | Lower EL using AArch64 |
* | + 0x480 | IRQ / vIRQ | |
* | + 0x500 | FIQ / vFIQ | |
* | + 0x580 | SError / vSError | |
* +------------------+------------------+-------------------------+
* | + 0x600 | Synchronous | Lower EL using AArch64 |
* | + 0x680 | IRQ / vIRQ | |
* | + 0x700 | FIQ / vFIQ | |
* | + 0x780 | SError / vSError | |
* +------------------+------------------+-------------------------+
*/
SECTION_SUBSEC_FUNC(exc_vector_table,_vector_table_section,_vector_table)
/* The whole table must be 2K aligned */
.align 11
GTEXT(_vector_table)
/* Current EL with SP0 / Synchronous */
.align 7
arm64_enter_exception x9, x10
b arm64_sync_exc
/* Current EL with SP0 / IRQ */
.align 7
arm64_enter_exception x0, x1
b arm64_irq_handler
/* Current EL with SP0 / FIQ */
.align 7
arm64_enter_exception x0, x1
b arm64_fiq_handler
/* Current EL with SP0 / SError */
.align 7
arm64_enter_exception x0, x1
b arm64_serror_handler
/* Current EL with SPx / Synchronous */
.align 7
arm64_enter_exception x9, x10
b arm64_sync_exc
/* Current EL with SPx / IRQ */
.align 7
arm64_enter_exception x0, x1
b arm64_irq_handler
/* Current EL with SPx / FIQ */
.align 7
arm64_enter_exception x0, x1
b arm64_fiq_handler
/* Current EL with SPx / SError */
.align 7
arm64_enter_exception x0, x1
b arm64_serror_handler
/* Lower EL using AArch64 / Synchronous */
.align 7
arm64_enter_exception x9, x10
b arm64_sync_exc
/* Lower EL using AArch64 / IRQ */
.align 7
arm64_enter_exception x0, x1
b arm64_irq_handler
/* Lower EL using AArch64 / FIQ */
.align 7
arm64_enter_exception x0, x1
b arm64_fiq_handler
/* Lower EL using AArch64 / SError */
.align 7
arm64_enter_exception x0, x1
b arm64_serror_handler
/* Lower EL using AArch32 / Synchronous */
.align 7
arm64_enter_exception x0, x1
b arm64_mode32_handler
/* Lower EL using AArch32 / IRQ */
.align 7
arm64_enter_exception x0, x1
b arm64_mode32_handler
/* Lower EL using AArch32 / FIQ */
.align 7
arm64_enter_exception x0, x1
b arm64_mode32_handler
/* Lower EL using AArch32 / SError */
.align 7
arm64_enter_exception x0, x1
b arm64_mode32_handler
/* Restore Corruptible Registers and exception context
* from the task stack.
*/
GTEXT(arm64_exit_exception)
SECTION_FUNC(text, arm64_exit_exception)
#ifdef CONFIG_ARCH_FPU
add x0, sp, #8 * ARM64_CONTEXT_REGS
bl arm64_fpu_restore
#endif
/* restore spsr and elr at el1*/
ldp x0, x1, [sp, #8 * REG_ELR]
#if CONFIG_ARCH_ARM64_EXCEPTION_LEVEL == 3
msr elr_el3, x0
msr spsr_el3, x1
#else
msr elr_el1, x0
msr spsr_el1, x1
#endif
#ifdef CONFIG_ARM64_MTE
ldr x0, [sp, #8 * REG_SCTLR_EL1]
msr sctlr_el1, x0
#endif
ldp x0, x1, [sp, #8 * REG_SP_EL0]
msr sp_el0, x0
msr tpidrro_el0, x1
/* decrement exception depth */
mrs x0, tpidrro_el0
mov x1, #1
sub x0, x0, x1
msr tpidrro_el0, x0
ldp x0, x1, [sp, #8 * REG_X0]
ldp x2, x3, [sp, #8 * REG_X2]
ldp x4, x5, [sp, #8 * REG_X4]
ldp x6, x7, [sp, #8 * REG_X6]
ldp x8, x9, [sp, #8 * REG_X8]
ldp x10, x11, [sp, #8 * REG_X10]
ldp x12, x13, [sp, #8 * REG_X12]
ldp x14, x15, [sp, #8 * REG_X14]
ldp x16, x17, [sp, #8 * REG_X16]
ldp x18, x19, [sp, #8 * REG_X18]
ldp x20, x21, [sp, #8 * REG_X20]
ldp x22, x23, [sp, #8 * REG_X22]
ldp x24, x25, [sp, #8 * REG_X24]
ldp x26, x27, [sp, #8 * REG_X26]
ldp x28, x29, [sp, #8 * REG_X28]
ldp x30, xzr, [sp, #8 * REG_X30]
add sp, sp, #8 * XCPTCONTEXT_REGS
eret