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1. Core_Melters Core_Melters Public

   Out of Order Risc-V processor

   SystemVerilog 2

2. ProtocolLLM ProtocolLLM Public

   ProtocolLLM: RTL Benchmark for SystemVerilog Code Generation of Communication Protocols

   SystemVerilog 6 1

3. Image_to_COE Image_to_COE Public

   Convert a Image to a COE file for Vivado

   Python 10

4. Object-Tracking-with-FPGA Object-Tracking-with-FPGA Public

   VHDL 2

5. CS225_Final_Proj CS225_Final_Proj Public

   C++ 3

6. 2048_vivado 2048_vivado Public

   This is a System Verilog implementation of 2048 in Vivado and Artx A7

   SystemVerilog 3