Thanks you for your PR. Though I am off for TET (Lunar New Year) and won't be able to review this in 2 weeks. Happy New Year

fyi @tannewt

@ladyada Thanks for noticing Scott. I'm not sure if the change I suggested is fine under all conditions. The flash chip in these boards would not support 100Mhz or 133Mhz with the simple read command (0x03). No problem with fast read. An alternative would be to change the flash frequency one the app is started, but I did not find a way to do so. Maybe not yet.

Thank you for both merging the PR and the hint for changing the frequency change. I have another question:
In the memconfig structure there are elements around deviceModeCfgEnable, which are configured to enable quad mode. It is configured to send a Write Status command (hex 01), with argument 0x40; LUT entry 4. So far that's ok. But writing to the status register requires to send the write Enable command before. But that's missing. So I wonder how this enabling happens. Actually, the flash seem to run in quad mode. There is high frequency activity on all IO pins of the flash, even /WP and /HOLD.

I'm not sure how QE is set initially. I haven't looked at this in ages.

I hooked up a logic analyzer to see what happens after reset
The ROM code executes:
a) A large block of data is read using command 0x03, CLK frequency ~30MHz.
b) A write enable command 0x06 is sent
Then:
c) The startup command as defined by the arg of deviceModeCfgEnable is sent. So no magic. The ROM code itself send the Write Enable command.

About changing the flash clock at runtime. I used the code from your link as template. As an element of pedantic, I add a mechanism to change the clock to any of the possible frequencies by modifying both the pfd_480 and the flexspi PODF dividers, using the values below which give the closest match.

typedef struct _ps_div_t {
    uint8_t pfd480_div;
    uint8_t podf_div;
} ps_div_t;

static ps_div_t div_table_mhz[] = {
    { 35, 8 }, // Index 0 is not valid, map it to 30 MHz
    { 35, 8 }, // 30 -> 30.85 MHz
    { 29, 6 }, // 50 -> 49.65 MHz
    { 18, 8 }, // 60 -> 60 MHz
    { 23, 5 }, // 75 -> 75.13 MHz
    { 18, 6 }, // 80 -> 80 MHz
    { 29, 3 }, // 100 -> 99.31 MHz
    { 13, 5 }, // 133 -> 132.92 MHz
    { 26, 2 }  // 166  -> 166.15 MHz
};