Skip to content

Conversation

@dstadelm
Copy link
Contributor

This pull request is split into 4 commits.
Each commit could be applied without breaking the initial code.
The commits are organized so that they are building up on one another. This should make it easier to review the pull request. Each commit has additional description which should help to understand the intent of the commit.

David Stadelmann added 7 commits September 23, 2019 16:32
…_order

These two functions used a lot of similar code. The code is now split
into functions. These will also be used in future for the functionality
to compile only the required subset of files.
SourceFile, VerilogSourceFile and VHDLSourceFile now reside in own
module source_file
These function takes a list of target source files and returns the
minimal list of SourceFiles to compile for the given target source
files.
One quirk is that at the end of the function the list has to be
filtered. This has to do with the get_files_in_compile_order function,
which for reasons that are unknown to me introduces unnecessary files.
This feature is used so that one can find the SourceFile of the test
bench that belongs to a test case. This will be required for generating
the target file list for the subset compile.
The additional argument allows to pass a list of target files. If that
argument is used, only the subset of files that is required to fullfill
all dependencies of the target files, are compiled.
This commit adds the switch for the minimal subset compilation. Also
modifies the def _compile function. The modification filteres gets the
filtered testcases and from those retrives the source files. This
together generates the target_files list.
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment

Labels

None yet

Projects

None yet

Development

Successfully merging this pull request may close these issues.

1 participant