I'm Hrithik Turaka, a freshman at the University of Colorado Denver majoring in Electrical Engineering, and a focused passion for semiconductors—specifically ASIC design, GPU architecture, and digital logic systems 🎓.
I'm building a strong foundation in RTL design, digital systems, and hardware verification while actively working to understand the full semiconductor design flow. My goal is to contribute to cutting-edge chip design anywhere I can.
- RTL Design & Digital Logic: Mastering synchronous design, state machines, combinational/sequential circuits, and hardware description languages
- ASIC + GPU Specialization: Understanding how GPU cores are specialized in ASICs and positioning myself for GPU ASIC design roles
- HDLs and Scripting Languages: Learning and utilizing relevant and necessary HDLs (SystemVerilog, etc) and scripting languages (Python, Perl, UNIX, etc.)
- Building a Portfolio: Creating hands-on projects that demonstrate RTL fundamentals and design thinking
Fall 2025
ELEC 1510: Digital Logic Design
- Designed combinational and sequential switching circuits
- Applied Boolean algebra, Karnaugh maps (K-maps), and algorithmic state machines (ASMs)
- Simulated circuits in Verilog/Behavioral Verilog using Intel Quartus Prime 18.1
- Foundation: Synchronous logic, timing, and basic RTL thinking
Spring 2026
ELEC 1520: Programming for Electrical Engineers (C/C++)
- Learning C/C++ and embedded systems fundamentals
- Building understanding of how high-level code maps to hardware
- Focus: Thinking in parallelism and hardware constraints, not algorithmic optimization
- Ongoing: Supplementing with independent Verilog/SystemVerilog study
Hardware Description Languages
- Verilog (primary focus for RTL design)
- Intel Quartus Prime 18.1 (FPGA synthesis and simulation)
Programming
- C/C++ (in progress via coursework)
- Python (for scripting and data analysis)
- Git & GitHub (version control and portfolio management)
Foundational Knowledge
- Digital logic, Boolean algebra, K-maps, state machines
- Synchronous circuit design and basic timing analysis
- FPGA simulation and synthesis workflows