This project showcases the implementation of an emulator that can run RISC-V assembly programs, demonstrating low-level programming and computer architecture concepts.
- Emulates RISC-V Instructions: Supports a subset of RISC-V instructions.
- Assembly and C Programs: Includes example programs written in both assembly and C.
- Basic CPU Functionality: Implements CPU operations and memory management.
- Instruction Set Architecture (ISA): Understand the RISC-V ISA, including how instructions are fetched, decoded, and executed.
- CPU Design: Learn about the basic components of a CPU, such as registers, the arithmetic logic unit (ALU), and control units.
- Memory Management: Explore how memory is accessed and managed, including stack and heap management.
- Bit Manipulation: Gain insights into low-level data manipulation using bitwise operations.
- Pipelining: Understand basic pipelining concepts, although not fully implemented, it lays the groundwork for learning more advanced CPU design.
- Caching: Learn the basics of caching mechanisms and their impact on performance.
- Exception Handling: Study how exceptions and interrupts are handled in a CPU.