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cpu/riscv_common: enable puf_sram feature#17665

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fjmolinas merged 3 commits intoRIOT-OS:masterfrom
PeterKietzmann:pr_puf_sram_riscv
Feb 18, 2022
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cpu/riscv_common: enable puf_sram feature#17665
fjmolinas merged 3 commits intoRIOT-OS:masterfrom
PeterKietzmann:pr_puf_sram_riscv

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@PeterKietzmann PeterKietzmann commented Feb 16, 2022

Contribution description

This pull request enables the puf_sram feature for RISC-V platforms. The changes include:

  • Add a .noinit section to the RISC-V linker script.
  • Clear .bss section only until actual end of that section, to prevent clearing .noinit.
  • New helper function that calls puf_sram_init is executed from startup code.
  • Enable the feature via Makefile.features.

Testing procedure

Execute tests/puf_sram on a RISC-V board as explained in the test README. I have used the hifive1b board. Note that this platform requires a power-off time of ~10 seconds to produce fresh memory pattern on startup.

  1. Run the example test script alike python tests/example_test.py -t 10 -n 100. This produces 100 SRAM based seeds with a power-off time of 10 seconds. It should produce outputs similar to:
Iteration 0/100
1439302621
Iteration 1/100
3158746474
Iteration 2/100
...
Iteration 99/100
1221232866
Number of seeds: 100       
Seed length    : 32 Bit   
Abs. Entropy   : 28.94 Bit   
Rel. Entropy   : 90.44 perc.
  1. (Requires at least one preceding power-off cycle) Press the reset button. The soft-reset detection should trigger which becomes visible by the print before main.
random: PUF SEED not fresh
main(): This is RIOT! (Version: 2022.01-devel-1951-g397c17)
Start: Test random number generator
Success: Data for puf_sram_seed: [0xEEE4DC19]
End: Test finished

@github-actions github-actions bot added Area: cpu Area: CPU/MCU ports Platform: RISC-V Platform: This PR/issue effects RISC-V-based platforms labels Feb 16, 2022
@PeterKietzmann PeterKietzmann added Area: security Area: Security-related libraries and subsystems CI: ready for build If set, CI server will compile all applications for all available boards for the labeled PR and removed Area: cpu Area: CPU/MCU ports labels Feb 16, 2022
@github-actions github-actions bot added Area: cpu Area: CPU/MCU ports Area: Kconfig Area: Kconfig integration labels Feb 16, 2022
@PeterKietzmann PeterKietzmann mentioned this pull request Feb 17, 2022
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fjmolinas
fjmolinas approved these changes Feb 18, 2022
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ACK, test output provided

@fjmolinas fjmolinas enabled auto-merge February 18, 2022 09:24
@fjmolinas fjmolinas merged commit 1a54357 into RIOT-OS:master Feb 18, 2022
@PeterKietzmann PeterKietzmann self-assigned this Mar 7, 2022
@PeterKietzmann PeterKietzmann deleted the pr_puf_sram_riscv branch April 6, 2022 21:25
@OlegHahm OlegHahm added this to the Release 2022.04 milestone Apr 25, 2022
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@fjmolinas fjmolinas fjmolinas approved these changes

@bergzand bergzand Awaiting requested review from bergzand

@dylad dylad Awaiting requested review from dylad

@maribu maribu Awaiting requested review from maribu

@leandrolanzieri leandrolanzieri Awaiting requested review from leandrolanzieri leandrolanzieri is a code owner

@jia200x jia200x Awaiting requested review from jia200x jia200x is a code owner

@cgundogan cgundogan Awaiting requested review from cgundogan

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@PeterKietzmann PeterKietzmann

Labels

Area: cpu Area: CPU/MCU ports Area: Kconfig Area: Kconfig integration Area: security Area: Security-related libraries and subsystems CI: ready for build If set, CI server will compile all applications for all available boards for the labeled PR Platform: RISC-V Platform: This PR/issue effects RISC-V-based platforms

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Release 2022.04

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3 participants

@PeterKietzmann @fjmolinas @OlegHahm