|
| 1 | + /* |
| 2 | + * Copyright (C) 2025 Mesotic SAS |
| 3 | + * |
| 4 | + * This file is subject to the terms and conditions of the GNU Lesser |
| 5 | + * General Public License v2.1. See the file LICENSE in the top level |
| 6 | + * directory for more details. |
| 7 | + */ |
| 8 | + |
| 9 | +/** |
| 10 | + * @ingroup boards_sam4s-xpro |
| 11 | + * @{ |
| 12 | + * |
| 13 | + * @file |
| 14 | + * @brief Peripheral MCU configuration for SAM4S Xplained pro |
| 15 | + * |
| 16 | + * @author Dylan Laduranty <dylan.laduranty@mesotic.com> |
| 17 | + */ |
| 18 | + |
| 19 | +#ifndef PERIPH_CONF_H |
| 20 | +#define PERIPH_CONF_H |
| 21 | + |
| 22 | +#include "periph_cpu.h" |
| 23 | + |
| 24 | +#ifdef __cplusplus |
| 25 | +extern "C" { |
| 26 | +#endif |
| 27 | + |
| 28 | +/** |
| 29 | + * @name Clock configuration |
| 30 | + * @{ |
| 31 | + */ |
| 32 | +/* targeted system core clock */ |
| 33 | +#define CLOCK_CORECLOCK MHZ(120) |
| 34 | +/* external oscillator clock */ |
| 35 | +#define CLOCK_EXT_OSC MHZ(12) |
| 36 | +/* define PLL configuration |
| 37 | + * |
| 38 | + * The values must fulfill this equation: |
| 39 | + * CORECLOCK = (EXT_OCS / PLL_DIV) * (PLL_MUL + 1) |
| 40 | + */ |
| 41 | +#define CLOCK_PLL_MUL (9) |
| 42 | +#define CLOCK_PLL_DIV (1) |
| 43 | + |
| 44 | +/* number of wait states before flash read and write operations */ |
| 45 | +#define CLOCK_FWS (5) /* 5 is safe for 120 MHz */ |
| 46 | +/** @} */ |
| 47 | + |
| 48 | +/** |
| 49 | + * @brief Enable external oscillator for driving the slow clock |
| 50 | + */ |
| 51 | +#define CLOCK_SCLK_XTAL (1) |
| 52 | + |
| 53 | +/** |
| 54 | + * @name Timer peripheral configuration |
| 55 | + * @{ |
| 56 | + */ |
| 57 | +static const timer_conf_t timer_config[] = { |
| 58 | + { .dev = TC0, .id_ch0 = ID_TC0 }, |
| 59 | + { .dev = TC1, .id_ch0 = ID_TC3 } |
| 60 | +}; |
| 61 | + |
| 62 | +#define TIMER_0_ISR isr_tc0 |
| 63 | +#define TIMER_1_ISR isr_tc3 |
| 64 | + |
| 65 | +#define TIMER_NUMOF ARRAY_SIZE(timer_config) |
| 66 | +/** @} */ |
| 67 | + |
| 68 | +/** |
| 69 | + * @name UART configuration |
| 70 | + * @{ |
| 71 | + */ |
| 72 | +static const uart_conf_t uart_config[] = { |
| 73 | + { |
| 74 | + .dev = (Uart *)UART1, |
| 75 | + .rx_pin = GPIO_PIN(PB, 2), |
| 76 | + .tx_pin = GPIO_PIN(PB, 3), |
| 77 | + .mux = GPIO_MUX_A, |
| 78 | + .pmc_id = ID_UART1, |
| 79 | + .irqn = UART1_IRQn |
| 80 | + } |
| 81 | +}; |
| 82 | + |
| 83 | +/* define interrupt vectors */ |
| 84 | +#define UART_0_ISR isr_uart1 |
| 85 | + |
| 86 | +#define UART_NUMOF ARRAY_SIZE(uart_config) |
| 87 | +/** @} */ |
| 88 | + |
| 89 | +#ifdef __cplusplus |
| 90 | +} |
| 91 | +#endif |
| 92 | + |
| 93 | +#endif /* PERIPH_CONF_H */ |
| 94 | +/** @} */ |
0 commit comments