[Instruction][tcgen05] Add alloc, dealloc and relinquish instructions #47
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Signed-off-by: Yaoyao Ding <dingyaoyao.cs@gmail.com>
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Pull Request Overview
This PR adds three new tcgen05 instructions (alloc, dealloc, and relinquish_alloc_permit) to the tilus framework, along with the necessary infrastructure to support tensor memory operations on SM100 GPU architectures.
- Introduces TensorMemoryTensor class for handling tensor memory allocations
- Adds Tcgen05EmitContext to track CTA group state across tcgen05 instructions
- Refactors codegen context access pattern from dictionary-based to singleton pattern
Reviewed Changes
Copilot reviewed 25 out of 25 changed files in this pull request and generated 2 comments.
Show a summary per file
| File | Description |
|---|---|
| tests/instructions/test_tcgen_alloc_free.py | Test case demonstrating tcgen05 instruction usage |
| python/tilus/testing/requires.py | Adds nvgpu_sm100 target requirement for testing |
| python/tilus/lang/transpiler.py | Updates to use new builder setter method |
| python/tilus/lang/script.py | Adds TensorMemoryTensor support and tcgen05 instruction group |
| python/tilus/ir/tensor.py | Defines new TensorMemoryTensor class for tensor memory |
| python/tilus/ir/instructions/cuda/tcgen05.py | Core tcgen05 instruction implementations |
| python/tilus/backends/emitters/cuda/tcgen05.py | Code generation for tcgen05 instructions |
| python/tilus/backends/contexts/tcgen05_ctx.py | New context for tracking tcgen05 state |
| python/tilus/backends/codegen.py | Refactors context access to singleton pattern |
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This PR adds three tcgen05 instructions:
In IR,
In codegen,