Repository of hardware Trojan (HT) benchmarks created using the GHOST framework, containing HTs generated by GPT-4, Gemini-1.5-pro, and LLaMA3.

• 14 synthesizable hardware Trojans
• 3 target RTL IP cores: AES-128, SRAM, UART
• 3 HT Types: - HT1: Change Functionality - HT2: Leak Information - HT3: Denial of Service
• 3 LLM models: GPT-4, Gemini-1.5-pro, LLaMA3-70B
• Full verification suite including testbenches and synthesis results

project_root/
├── gpt-4/
│   ├── aes_128/
│   │   ├── worked/                 # Successful implementations
│   │   │   ├── AES-HT100/         # Type 1 HT (Change Functionality)
│   │   │   ├── AES-HT110/         # Type 2 HT (Leak Information) 
│   │   │   ├── AES-HT120/         # Type 3 HT (DoS)
│   │   │   └── AES-HT_free/       # Reference design
│   │   └── X/                      # Failed attempts
│   ├── sram/
│   └── uart/
├── models_gemini-1.5-pro-latest/   # Similar structure as gpt-4
├── llama3-70b-8192/               # Similar structure as gpt-4
└── scripts/                       # Automation and generation tools
    ├── LLM_HT_inserter.ipynb      # Main GHOST framework notebook
    ├── tb_generator_no_api.py     # Testbench generator
    └── automation_codes/          # Synthesis and analysis scripts
        ├── compilation_check.py   # Verilog compilation verification
        ├── get_resource_util.py    # Resource utilization analysis
        ├── include_submodules.py   # Submodule inclusion utility
        ├── xilinx_resource_util.py # Xilinx-specific resource analysis
        ├── synth_script_yosys.ys   # Yosys synthesis script
        ├── signle_design_synth_sky130.ys # Sky130 synthesis script
        └── verilog_compilation_results.csv # Compilation results

• *_A1.v: Original HT-inserted RTL
• *_cleaned.v: Cleaned and Unannotated version
• *_tb.v: Testbench for functional verification
• *_taxonomy.txt: HT classification and details

• *_net_sky.v: SkyWater PDK netlist
• *_net_yosys.v: Yosys synthesis output
• *.vvp: Compiled simulation executable

• *_stats_sky.txt: SkyWater synthesis stats
• *_stats_yosys.txt: Yosys synthesis stats
• all_*_stats_*.csv: Consolidated statistics

For AES-128:

• round.v: Round implementation
• table.v: S-box tables

For UART:

• impl_top.v: Top-level wrapper
• uart_tx.v: Transmitter module

For SRAM:

• No additional dependencies

• First digit: LLM (1=GPT-4, 2=Gemini, 3=LLaMA3)
• Second digit: HT type (0=Type1, 1=Type2, 2=Type3)
• Third digit: Attempt number (0=first attempt)

Example: HT120 = GPT-4, Type 3 HT, first attempt

• RTL Compiler: Icarus Verilog v11.0
• Logic Synthesis: Yosys 0.9
• PDK: Google SkyWater 130nm
• Cell Library: sky130_fd_sc_hd_tt_025C_1v80.lib

• LLM_HT_inserter.ipynb: Core GHOST framework notebook that interfaces with multiple LLM APIs (GPT-4, Gemini, LLaMA3) to generate hardware Trojans. Includes prompt engineering, response parsing, and file management functionality.

• tb_generator_no_api.py: Automated testbench generator for hardware Trojan verification.

• compilation_check.py: Verifies Verilog code compilation using Icarus Verilog.
• get_resource_util.py: Analyzes resource utilization from synthesis results.
• include_submodules.py: Utility for resolving Verilog include directives. Automatically incorporates submodules and dependencies into main design files.
• xilinx_resource_util.py: Xilinx-specific resource utilization analysis tool for FPGA implementations.
• synth_script_yosys.ys: Generic Yosys synthesis script for RTL-to-gate level transformation.
• signle_design_synth_sky130.ys: Sky130 PDK-specific synthesis script for single design processing.
• verilog_compilation_results.csv: Results database containing compilation status for all processed designs.

1. Clone repository:

git clone https://github.com/HSTRG1/GHOST_benchmarks.git

2. Install requirements:

• Icarus Verilog v11.0 (RTL compilation/simulation)
• GTKWave v3.3 (Waveform visualization)
• Yosys v0.9 (Logic synthesis)
• SkyWater PDK (sky130_fd_sc_hd_tt_025C_1v80.lib)

3. Run pre-synthesis simulation:

iverilog -o <design>_sim <design>.v <testbench>.v
vvp <design>_sim
gtkwave <design>_sim.vcd

4. Run synthesis:

yosys -p "read_verilog <design>.v; synth -top <module>; dfflibmap -liberty sky130_fd_sc_hd_tt_025C_1v80.lib; abc -liberty sky130_fd_sc_hd_tt_025C_1v80.lib"

@article{faruque2024unleashing,
  title={Unleashing GHOST: An LLM-Powered Framework for Automated Hardware Trojan Design},
  author={Faruque, Md Omar and Jamieson, Peter and Patooghy, Ahmad and Badawy, Abdel-Hameed A},
  journal={arXiv preprint arXiv:2412.02816},
  year={2024}
}

MIT License

Contributions to expand the benchmark set or improve documentation are welcome. Please submit a pull request or contact the maintainers for more information.

• Google SkyWater PDK: https://github.com/google/skywater-pdk

• Open-source EDA tools:

  • Yosys: https://yosyshq.net/yosys/
  • Icarus Verilog: https://steveicarus.github.io/iverilog/
  • GTKWave: https://gtkwave.github.io/gtkwave/

• Original RTL Designs:

  • AES-128: https://github.com/fabriziotappero/ip-cores/tree/crypto_core_aes
  • UART: https://github.com/ben-marshall/uart
  • SRAM: https://github.com/VLSIDA/OpenRAM

These open-source hardware designs served as the base RTL for GHOST framework HT insertions.