Wording of these restrictions was clarified in gpuweb/spirv-execution-env@131313e. Need to confirm that the implementation matches the new text.

• OpControlBarrier* restrictions:
  • The Execution scope operand must be Workgroup
  • The Memory scope operand must be Workgroup
  • The Semantics operand:
  • Memory Semantics Order bits: Must set the AcquireRelease bit, and no other bits.
  • Memory Semantics Storage Class bits: Must set the WorkgroupMemory bit, and no
    other bits.
  • Must not set any Memory Semantics Propagation bits.

Note: To ensure propagation of Workgroup writes to readers,
individual accesses of Workgroup memory should use availability
and visibility semantics:
MakePointerAvailableKHR with Workgroup scope on writes,
MakePointerVisibleKHR with Workgroup scope on reads,
and NonPrivatePointerKHR on both.

• OpMemoryBarrier* restrictions:
  • The Memory scope operand must be Workgroup
  • The Semantics operand:
  • Must not set any Memory Semantics Order bits.
  • Memory Semantics Storage Class bits: Must set the ImageMemory bit, and no other
    bits.
  • Must not set any Memory Semantics Propagation bits.

Note: OpMemoryBarrier is only used to order reads and writes by the same
invocation to the same locations in image memory.