Wording of these restrictions was clarified in gpuweb/spirv-execution-env@131313e. Need to confirm that the implementation matches the new text.

Atomic instructions (OpAtomic*) are restricted:

• The Memory scope operand must be QueueFamilyKHR
• The Semantics operand must be zero:
  * Must not set any Memory Semantics Order bits.
  * Must not set any Memory Semantics Storage Class bits.
  * Must not set any Memory Semantics Propagation bits.

Note: In terms from other standards, OpAtomic* instructions are Relaxed.

Note: In the memory model, atomic operations automatically include
availability and visibility semantics.