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1. ALU ALU Public

   Arithmetic logic unit written in Verilog

2. Rate-Divider Rate-Divider Public

   Verilog File that creates a rate divider to count at different speeds. Includes the model sim file to log the signals.

   Stata

3. Morse-Code Morse-Code Public

   Verilog Module used to decipher morse code

4. Finite-State-Machine Finite-State-Machine Public

   Verilog modules written to create a Finite State Machine on an FPGA

5. Paitent_Health_Information_Removal Paitent_Health_Information_Removal Public

   Python script removes Patient Health Information from Flow Cytometry Files

   Python

6. RBG_Matrix_Spotify RBG_Matrix_Spotify Public

   Display currently playing cover art onto an rgb matrix

   Python