This repo contains circuit functionality learning dataset download instructions and documentation.
This dataset is made from open-source logic synthesis tool ABC and Yosys, together with our customized rewriting algorithm.
Following is a table that illustrates the number of samples contained in the dataset:
| Input Width | Replacement Ratio | ||||
| 10% | 20% | 30% | 50% | total | |
| 4 | 5666 | 5548 | 4302 | 3924 | 19440 |
| 5 | 200000 | 200000 | 200000 | 200000 | 800000 |
| 6 | 200000 | 200000 | 200000 | 200000 | 800000 |
| 7 | 200000 | 200000 | 200000 | 200000 | 800000 |
| total | 605666 | 605548 | 604302 | 603924 | 2419440 |
You can now download our raw AIG data from the following link: (7-zipped ~3GB)
https://drive.google.com/file/d/1thF6OO6mk4q7v5iGvUx2ISuGQsaMNTnq/view?usp=share_link
The archive contains:
- The netlists of a large number of synthetic truth table circuits in the AIG format (.bench) with the input width ranges from 4 to 7.
- The augmented positive pairs of each truth table netlist using replacement ratios 10%, 20%, 40%, and 50%. Note that the augmentation changes the topology while maintaining the Boolean functionality.
Please use the link below. The 7-zipped file is about 2.5GB in size.
https://drive.google.com/file/d/1Ta8uUgVYzAW5fvQExN3RXRmYlX703rXC/view?usp=share_link
You can also refer to our code for usage.