Provides a template for the directory structure used to synthesize custom designs for XLR8. The steps included below can be used to build an OpenXLR8 design.
Additional information and support is available on the Alorium Website
- Download and install Quartus Tool available from Intel.. The
download page can be found by googling for "Intel Quartus"
- This should include Modelsim-Altera Starter Edition and Max 10 FPGA support
- The current version, 17.1, is supported. Older versions will fail due to library incompatibilities.
- Quartus tools are only available for Windows and Linux. On Mac, you'll need to run a VM or some other method to get either a Windows or Linux operating system.
- Install OpenXLR8 libraries in Arduino IDE
- Sketch->Include Library->Manage Libraries
- Filter your search for XLR8
- Install XLR8Core, XLR8BuildTemplate, and any other desired libraries
- Create a copy of the build template in the working location
- In your Operating System's File Explorer
- Goto your Arduino/libraries folder
- Make a copy of the XLR8BuildTemplate folder and name the copy
XLR8Build.
- (The library may have been downloaded as XLR8_Build. Still make a copy named XLR8Build)
- The XLR8Core library may have been downloaded as XLR8_Core. If so, rename it to XLR8Core.
- Modify the XLR8Build with your custimizations
- For a minimal build (no XBs), nothing needs to be done here
- To use a single XB (The following steps assume the name of your
custom logic is "myLogic")
- Rename xlr8_wrap_template.v to xlr8_myLogic.v
- Instantiate your "myLogic.v" into xlr8_myLogic.v, creating the config/data regs needed as well.
- Instantiate xlr8_myLogic in openxlr8.v, making changes as directed by the comments
- Modify xb_adr_pack.vh to define the addresses of the registers you have added in xlr8_myLogic
- For more complex cases such as multiple XBs
- Create a xlr8_foo.v wrapper for each of you logic blocks
- Instantiate all of your wrapper blocks in openxlr8.v
- Building in Quartus
- Modify the quartus/openxlr8.qsf file to specify you rtl source files
- Open XLR8Build/extras/quartus/xlr8_top.qpf with the Altera Quartus software (in windows you can simply double-click on xlr8_top.qpf in Windows Explorer)
(Available on Windows. Linux coming soon. Not available on Mac)
- In Arduino, select
- Board = Open XLR8
- Floating Point XB = Enabled (Can set to disabled if you have the Floating Point XB but want to use software floating point anyway for some reason).
- FPGA Image = choose AVR frequency that matches the rtl and sdc file (16MHz if you haven't changed the rtl)
- Upload Action = Send Sketch to Quartus-Modelsim directory
- Port = doesn't matter for this step
- Sketch->Upload (or hit the Upload button)
- This stores the compiled sketch into XLR8Build/extras/quartus/simulation/modelsim/sketch.dat
- In Quartus
- Processing->Start->Start Analysis and Elaboration
- Tools->Run Simulation Tool->RTL Simulation
- In Modelsim
- The simulation starts running with the top level inputs and outputs logged to the wave window.
- You may want to stop the simulation, add additional signals to the wave window, and then run-continue
- You may want to stop the simulation, add some breakpoints or
enter a number milli-seconds you would like to simulate, and
then run-continue.
- It is also possible for a sketch to control when the simulation finishes. The testbench watches the AVR's GPIOR1 register and if bit 7 is set, it will end the simulation at that point (and by convention report a passing status if bit 6 is also set). If your sketch doesn't set GPIOR1 (most sketches don't), the simulation will run until you hit the stop button.
(Available on Windows and Linux (Linux untested). Not available on Mac)
- In Quartus, do Processing->Start Compilation (or simply click the blue triangle icon)
- In Quartus, do File->Convert Programming Files
- Open Conversion Setup Data->xlr8_16MHz.cof
- Pick the .cof file that matches your Board/Clock
- Generate. Ok. Close.
- Open Conversion Setup Data->xlr8_16MHz.cof
- In Arduino, select
- Board = Open XLR8
- "Floating Point XB" and "Upload Action" setting don't matter for this step
- FPGA Image = choose AVR frequency that matches the rtl and sdc file (16MHz if you haven't changed the rtl)
- Port = Serial Port that XLR8 board is connected to
- Burn Bootloader (takes about a minute)
- Copy the URL that is printed at the end of the status message, paste it into a web browser, and leave us any comments you may have.
- Issues? Check the forums at http://forums.aloriumtech.com/
- Altera has both paid and free on-line training at Intel FPGA Technical Training, or simply google for "Intel FPGA Technical Training"
- An overview of the ModelSim HDL simulator is also available from Intel at Intel Modelsim Overview, or simply google for "Intel Modelsim Overview"