Summary

• Implement software SMI# and SMI status registers on the STPC chipsets
• Fix the Cyrix CCR1 and instruction validity checks to also apply to 486-class Cyrix CPUs (Cx486/Cx5x86/STPC)
• Fix STPC PCI ID initialization
• Properly handle saving descriptors where the segment limit is 4GB but the granularity bit is still set to byte on Cyrix CPUs
• Give the Lanner Electronics IAC-H488 the correct flash chip fixing the "No NVRAM" message on POST
• Implement the Cyrix Cx5x86 PMR (F0h) register
• Make the Cyrix register code not fatal() on writes to F2h: The IMS 8848-based J-Bond PCI400C-B attempts to write to chipset register F2 and since the I/O space is shared this was getting handled by the Cyrix CPU I/O handler.

Checklist

• Closes #xxx
• I have tested my changes locally and validated that the functionality works as intended
• I have discussed this with core contributors already
• This pull request requires changes to the ROM set
  • I have opened a roms pull request - https://github.com/86Box/roms/pull/changeme/
• This pull request requires changes to the asset set
  • I have opened an assets pull request - https://github.com/86Box/assets/pull/changeme/

References

Provide links to datasheets or other documentation that helped you implement this pull request.

• STPC Atlas/Client/Consumer-II/Elite Programmers' Guides: On the 86Box FTP
• Cyrix 5x86 CPU BIOS Writers' Guide: https://bitsavers.org/components/cyrix/appnotes/5x86_CPU_BIOS_Writers_Guide_1.12_1995.pdf
• Cyrix SMM Programmers' Guide: https://ardent-tool.com/CPU/docs/Cyrix/Smm6x86.pdf
• ST486DX SMM Programming Manual: https://ardent-tool.com/CPU/docs/ST/486_5x86/2513.pdf