Skip to content

Conversation

@TC1995
Copy link
Contributor

@TC1995 TC1995 commented Oct 3, 2024

Summary

8514/A changes:

  1. Correct interlaced display resolution.
  2. Added a limit to cursor coordinates.
  3. Test/WIP features of the add-on Mach8 side (ATI 8514/A Ultra) such as configurable BIOS.
  4. Made the CMD 5 of the acceleration (Polygon Boundary) more accurate per manual (as much as I could regarding the clipping).

Cirrus related:

  1. Added SUBSYS PCI vendor/device ID of the 5480 (per manual).

IBM VGA:

  1. Built-in/option rom-less VGA don't need the "available" flag.

ATI Mach8/32:

  1. As with 8514/A, corrected interlaced display.

XGA-1/-2:

  1. Moved the XGA R/W memory size tests out of the SVGA R/W routines to reflect the per card basis, although anything that uses its own SVGA mapping would call the tests there (such as Cirrus, Headland and ATI) when not accessing the LFB. This finally puts an end to the XGA MCA mapping enabling bugs.
  2. Re-organized the ISA standalone and non-standalone (INMOS) sides of the chips so that they work properly and remove the FILE rom loading hack from init.
  3. The Memory Mapped R/W sides now account for instance in their address range.
  4. INMOS only: prevent any ROM address access to anything lower than 0xc8000 to not conflict with the main BIOS rom loading.
  5. Fixed native pitch by using the correct register, this fixes non 1024x768 resolutions under NT.
  6. More logs when enabled to see any future bugs.

Checklist

References

VESA XGA specification
INMOS G201 MCA/ISA
8514/A/Mach8/32 (for CMD 5)

8514/A changes:
1. Correct interlaced display resolution.
2. Added a limit to cursor coordinates.
3. Test/WIP features of the add-on Mach8 side (ATI 8514/A Ultra) such as configurable BIOS.
4. Made the CMD 5 of the acceleration (Polygon Boundary) more accurate per manual (as much as I could regarding the clipping).

Cirrus related:
1. Added SUBSYS PCI vendor/device ID of the 5480 (per manual).

IBM VGA:
1. Built-in/option rom-less VGA don't need the "available" flag.

ATI Mach8/32:
1. As with 8514/A, corrected interlaced display.

XGA-1/-2:
1. Moved the XGA R/W memory size tests out of the SVGA R/W routines to reflect the per card basis, although anything that uses its own SVGA mapping would call the tests there (such as Cirrus, Headland and ATI) when not accessing the LFB. This finally puts an end to the XGA MCA mapping enabling bugs.
2. Re-organized the ISA standalone and non-standalone (INMOS) sides of the chips so that they work properly and remove the FILE rom loading hack from init.
3. The Memory Mapped R/W sides now account for instance in their address range.
4. INMOS only: prevent any ROM address access to anything lower than 0xc8000 to not conflict with the main BIOS rom loading.
5. Fixed native pitch by using the correct register, this fixes non 1024x768 resolutions under NT.
6. More logs when enabled to see any future bugs.
@OBattler OBattler merged commit 1b1b283 into master Oct 3, 2024
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment

Labels

None yet

Projects

None yet

Development

Successfully merging this pull request may close these issues.

IBM XGA-2 BIOS is not properly mapped during POST

3 participants