(S)VGA updates and fixes, 2023-11-22 edition #3844
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…0x05.6 is set This allows correct emulation of the 4bpp chunky mode which is supported by many but not all chipsets. See discussion 86Box#3840 on GitHub.
The current implementation still uses the shifter forced to Shift 256 mode to keep things generic, but we can always opt for a separate scanline renderer.
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Summary
This should sort out issue #3843 (I just knew there would be regressions), but it would need to be tested with the Windows 95 driver to prove it - I was using a more direct method to test things, and it works in the cases I tested.
Basically, in a high-resolution 8bpp mode, this now bypasses the shifter logic, which should make it consistent with how the HT-216 handles the mode as documented in the datasheet ("The whole 8 bits in the PEL is shifted out each PCLK").
I was also working on implementing the Shift 256 flag correctly, which should operate as expected now.
And there's an unused variable which has been cleaned up.
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References