A novel pipelined architecture of entropy filter

Abstract

In computer vision, entropy is a measure adopted to characterize the texture information of a grayscale image, and an entropy filter is a fundamental operation used to calculate local entropy. However, this filter is computationally intensive and demands an efficient means of implementation. Additionally, with the foreseeable end of Moore’s law, there is a growing trend towards hardware offloading to increase computing power. In line with this trend, we propose a novel method for the calculation of local entropy and introduce a corresponding pipelined architecture. Under the proposed method, a sliding window of pixels undergoes three steps: sorting, adjacent difference calculation, and pipelined entropy calculation. Compared with a conventional design, implementation results on a Zynq UltraScale+ XCZU7EV-2FFVC1156 MPSoC device demonstrate that our pipelined architecture can reach a maximum throughput of handling 764.526 megapixels per second while achieving $2.4\times$ and $2.9\times$ reductions in resource utilization and $1.1\times$ reduction in power consumption.

Appendix: conventional hardware architecture

Figure 6 illustrates the block diagram of the conventional hardware architecture for the entropy filter. The design is based on the sliding mechanism (described in Sect. 4.2) and the cumulative histogram [8].

Given n, representing a set of discrete intensities assigned to a pixel, this conventional design requires n registers, corresponding to $\textrm{Bin}\ 0,\ \textrm{Bin}\ 1,\ \ldots ,\ \textrm{Bin}\ (n-1)$ in Fig. 6, to store the number of occurrences of each pixel intensity. Each bin can increase or decrease by a specific amount based on whether the associated pixel intensity is about to enter or leave the sliding window. As shown in Fig. 6, when the window moves to an adjacent location, it will exclude pixels in the red column from its coverage while including pixels in the blue column. To handle these two groups of pixels, the conventional design utilizes register banks, as shown Fig. 6.

The next block determines the quantity to increase or decrease each histogram bin according to input pixel intensities. To implement this block, [18] proposed using barrel shifters, which were more memory-efficient than ROMs in [8]. Specifically, a barrel shifter decodes a $\lceil \textrm{log}n\rceil$-bit input into an n-bit signal, with each bit indicating an increment or decrement of a bin associated with the input intensity. For example, an 8-bit input of $11111110_2$ ($=254_{10}$) causes the barrel shifter to produce a 256-bit output of $4000\ldots 00_{16}$, signifying an increment or decrement of $\textrm{Bin}\ 254$. Table 3 demonstrates the input–output relationship of the barrel shifter.

Fig. 6

Block diagram of the conventional hardware architecture. We illustrate the sliding mechanism using a $3\times 3$ window

Fig. 7

Block diagram of the barrel shifter. Input and output are $\lceil \textrm{log}n\rceil$-bit and n-bit data, respectively. We adopt the square bracket to access individual bits of the input

Given an $S\times S$ window, S pixels are about to leave, and another S pixels are about to enter the window’s coverage every time the window slides. Accordingly, the conventional design requires 2S barrel shifters (details of the barrel shifter are available in Fig. 7). Half of these shifters signify bin decrease events (BDEs), and the other half signifies bin increase events (BIEs). The conventional design then converts every bit of BDE outputs to two’s complement representation and performs negation. Meanwhile, it solely converts every bit of BIE outputs to two’s complement representation. Afterward, it adds these negative and positive two’s complement numbers together using n adder trees to determine the quantity for increasing or decreasing each histogram bin.

Table 3 Input–output relationship of the barrel shifter

After updating histogram bins, the final block is to calculate the summation in (1). In this block, [18] utilized n LUTs to calculate summation terms corresponding to n bins. The content of each LUT is identical to that of the LUT described in Sect. 4.3. The outputs of these LUTs then undergo a large adder tree to compute the entropy value.

From the above description, it becomes evident that the conventional design is resource-consuming because it requires n registers for histogram bins and substantial quantities of resources for the resultant adder trees. Moreover, its space complexity is dependent on n and thus increases exponentially with n. Hence, it is inefficient compared to our proposed hardware architecture.