Abstract
The reduction of test costs, especially in high safety systems, requires that the same test strategy is employed for design validation, manufacturing and maintenance tests, and concurrent error detection. This unification of off-line and on-line tests has already been attempted for digital circuits and it offers the advantage of serving to all phases of a system lifetime.
Market pressure originating from the high costs of analog and mixed signal testing has resulted in renewed efforts for the test of analog parts. In this paper, off-line and on-line test techniques for fully differential analog circuits are presented within an unified approach. The high performance of these circuits makes them very popular for many applications, including high safety, low voltage and high speed systems.
A test master compliant with IEEE Std. 1149.1 is described. The Analog Unified BIST (AUBIST) is exemplified for linear and non-linear switched-capacitor circuits. High fault coverage is achieved during concurrent/on-line testing. An off-line test ensures the goal of self-checking circuits and allows the diagnosis of faulty parts. The self-test of the AUBIST circuitry is also considered.
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References
M. Nicolaidis, “A Unified Built-in Self-Test Scheme: UBIST,” Proc. 18th International Symposium on Fault Tolerant Computing, Tokyo, Japan, 1988, pp. 157–163.
S.K. Gupta and D.K. Pradhan, “Can Concurrent Checkers Help BIST,” Proc. International Test Conference, 1992, pp. 140–150.
X. Sun and M. Serra, “Merging Concurrent Checking and Off-line,” Proc. International Test Conference, 1992, pp. 958–965.
M. Lubaszewski and B. Courtois, “On the Design of SelfChecking Boundary Scannable Boards,” Proc. International Test Conference, 1992, pp. 372–381.
J.L. Huertas, D. Vázquez, and A. Rueda, “On-line Testing of Switched-Capacitor Filters,” Proc. IEEE VLSI Test Symp., 1992, pp. 102–106.
A. Chatterjee, “Concurrent Error Detection in Linear Analog and Switched-Capacitor State Variable Systems Using Continuous Checksums,” Proc. IEEE International Text Conference, 1991, pp. 582–591.
M. Lubaszewski, V. Kolarik, S. Mir, C. Nielsen, and B. Courtois. “Mixed-signal Circuits and Boards for High Safety Applications,” Proc. European Design and Test Conference, Paris, March 1995, pp. 34–39.
M. Slamani and B. Kaminska, “T-BIST: A Built-in Self-Test for Analog Circuits Based on Parameter Translation,” Proc. Asian Test Symposium, 1993, pp. 172–177.
S. Mir, V. Kolarik, M. Lubaszewski, C. Nielsen, and B. Courtois, “Built-in Self-Test and Fault Diagnosis of Fully Differential Analogue Circuits,” Proc. 12th International Conference on Computer-Aided Design, San Jose, California, Nov. 1994, pp. 486–490.
P.R. Gray, B.A. Wooley, and R.W. Brodersen (eds.), Analog MOS Integrated Circuits, II, IEEE Press, 1989.
Y.P. Tsidivis and J.O. Voorman (eds.), Integrated Continuous-Time Filters. Principles, Design and Applications, IEEE Press, 1993.
IEEE Standards Board, 345 East 47th Street, New York, NY 10017-2394, IEEE Standard Test Access Port and Boundary Scan Architecture, IEEE Standard 1149.1, 1990.
R. Castello and P.R. Gray, “A High-Performance Micropower Switched-Capacitor Filter,” IEEE Journal of Solid-State Circuits, Vol. SC-20, No. 6, pp. 1122–1132, Dec. 1985.
J.F. Duque-Carrillo, “Control of the Common-Mode Component in CMOS Continuous-Time Fully Differential Signal Processing,” Analog Integrated Circuits and Signal Processing, Vol. 4, pp. 131–140, 1993.
R. Harjani and B. Vinnakota, “Analog Circuit Observer Blocks,” Proc. 12th IEEE VLSI Test Symposium, April 1994, pp. 258–263.
M. Banu and Y. Tsividis, “An Elliptic Continuous-Time CMOS Filter with On-Chip Automatic Tuning,” IEEE Journal of Solid-State Circuits, Vol. SC-20, No. 6, pp. 1114–1121, Dec. 1985.
S. Mir, M. Lubaszewski, V. Kolarik, and B. Courtois, “Programmable Self-Checking Analogue Oscilators,” Proc. IEEE International On-line Testing Workshop, Nice, France, July 1995, pp. 30–33.
P.W. Li, M.J. Chin, P.R. Gray, and R. Castello, “A Ratio-Independent Algorithmic Analog-to-Digital Conversion Technique,” IEEE Journal of Solid-State Circuits, Vol. SC-19, No. 6, pp. 828–836, Dec. 1984.
S. Mir, M. Lubaszewski, V. Kolarik, and B. Courtois, “Automatic Test Generation for Maximal Diagnosis of Linear Analogue Circuits,” Proc. European Design and Test Conference, Paris, France, March 1996, pp. 254–258.
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This work is part of AMATIST ESPRIT-III Basic Research Project, funded by CEC under contract #8820.
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Mir, S., Lubaszewski, M. & Courtois, B. Unified built-in self-test for fully differential analog circuits. J Electron Test 9, 135–151 (1996). https://doi.org/10.1007/BF00137570
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DOI: https://doi.org/10.1007/BF00137570