Abstract
Physical defects widely encountered in today's CMOS processes (bridges, gate oxide short (gas) and floating gates) are modeled taking into account the topology of the defective circuit and the parameters of the technology. These models are used to simulate at electrical level the behavior of a simple 3-inverter chain with a defective inverter. The results are compared with experimental data of integrated circuits fabricated with intentional defects. The influence of the characteristics of each defect on I DDQ has been investigated by electrical simulation and experimentation.
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J.A. Segura is at the Balearic Islands University (UIB) and is working on his Ph.D. at the Polytechnical University of Catalonia.
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Segura, J.A., Champac, V.H., Rodríguez-Montañés, R. et al. Quiescent current analysis and experimentation of defective CMOS circuits. J Electron Test 3, 337–348 (1992). https://doi.org/10.1007/BF00135337
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DOI: https://doi.org/10.1007/BF00135337