Navitas has developed a TO-247 package offering more than 6000 V of isolation for its 1200-V, 2300-V, and 3300-V SiC MOSFETs. Designated the UHV-TO-247-4-ISO, the through-hole package supports direct-cooled thermal management through a reflow-compatible isolated thermal pad. It also provides over 12 mm of pin-to-pin creepage, enabling module-level performance in a compact discrete form factor.

Compared to standard non-isolated through-hole packages, the UHV-TO-247-4-ISO reduces the need for external high-voltage isolation while improving thermal and EMI performance. These benefits extend to high-voltage grid-tied power conversion systems, solid-state transformers, battery energy storage systems, and renewable energy applications.

The UHV-TO-247-4-ISO delivers integrated high-voltage isolation using an AlN substrate, reducing die-to-heatsink capacitance and helping lower common-mode noise and radiated EMI. Its reflow-compatible, direct-cooled thermal interface enables direct mounting to liquid- or air-cooled heatsinks, improving thermal performance while eliminating the need for external TIM and isolation materials. The package also enhances thermal cycling and power cycling lifetime through its AlN/AMB construction and robust heatsink interface.

To request samples or additional product information, please contact a Navitas sales representative or email info@navitassemi.com.

Navitas Semiconductor 

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Lotus Microsystems’ vStrata vertical power delivery platform targets the electrical, thermal, and mechanical challenges of AI infrastructure. The first module in the vStrata Power Series, the LS0580, is a fully integrated power-system-in-package (PSiP) that places power conversion closer to the load to reduce distribution losses and board complexity. The device has completed tape-out for leading CPU, GPU, and AI accelerator platforms, with engineering samples shipping in Q3 2026.

Built on a silicon-based substrate, vStrata combines power delivery, thermal management, and packaging in a single architecture. Designed for kiloampere-class AI workloads, the platform delivers up to 96% point-of-load efficiency while reducing power losses and thermal constraints. Its low-profile vertical architecture is enabled by silicon PIT technology, supporting ultra-thin designs below 1 mm by placing power directly beneath the processor to shorten electrical paths and improve transient response.

The vStrata platform is compatible with existing power management controllers and reference designs. Lotus is currently evaluating the platform with hyperscale customers and additional partners through an early access program.

vStrata product page

Lotus Microsystems 

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Altera is now sampling its Agilex 9 Direct RF AGRW039 wideband SoC FPGA for aerospace, defense, and communication systems. According to Altera, the device delivers a 40% increase in compute capability per square millimeter. It also provides 45% greater logic and DSP density than the previous generation and supports DDR5 and LPDDR5 memory technologies.

With integrated 64-Gsample/s wideband RF and increased compute and memory resources, the programmable device eliminates the need for multichip designs and enables advanced beamforming, radar, and data cube processing. The AGRW039 provides high-bandwidth signal capture and generation, allowing customers to scale performance while maintaining design flexibility.

Agilex 9 Direct RF SoC FPGAs combine high-speed data converters, programmable logic, and processing elements in a single package. The integrated architecture helps reduce system complexity and power consumption for wideband RF applications that require real-time performance.

Production silicon and development kits for the Agilex 9 Direct RF AGRW039 are expected to be available in Q3 2026.

Agilex 9 Direct RF series

Altera

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Learning from and adapting the lessons of the past is wise, as long as it’s not taken to overly constraining excess. So, too, is adopting others’ ideas (in a non-patent-infringing way, of course).

As you already know if you read last week’s blog post (and if not, please do so first before continuing with today’s…I’ll be right here, waiting for your return…), I initially planned on covering this topic in a single writeup. It ended up, however, being at least twice as long as I’d originally envisioned, so I basically chopped it in two. Part 1 covered the historical precedents that led to the ongoing memory card innovations of more modern times, which I’ll discuss this time.

Interface evolutions

I’m spending all this time on past-history factoids and trends because, as you’ll soon see, they conceptually continue(d) to repeat themselves multiple times over with the passage of time. To that point, one other historical example, involving performance, also bears mention. PCMCIA, introduced in 1990, tackled a mid-life enhancement five years later, from the 16-bit ISA bus-derived PC Card to the PCI bus-based and 32-bit, but still backwards-compatible, CardBus.

A more radical transformation, ExpressCard (originally called NEWCARD), followed roughly a decade after that. Based on the combination of PCI Express and USB 2.0, it was not directly backwards compatible with CardBus, far from with PC Card, thereby either forcing systems adopters to include slots for both standards in designs or forcing users to use clumsy adapters:

More generally, as my attempted blending of two Wikipedia entry excerpts notes:

Despite being much faster in speed/bandwidth, ExpressCard was not as popular as PC Card, due in part to the ubiquity of USB ports on modern computers. When the PC Card was introduced, the only other way to connect peripherals to a laptop computer was via RS-232 and parallel ports of limited performance, so it was widely adopted for many peripherals. More recently, virtually all equipment has Hi-Speed USB ports, and most types of peripherals which formerly used a PC Card connection are available for USB (and have the advantage of being compatible with desktop computers as well as portable devices) or are built-in, making the ExpressCard less necessary than the PC Card was in its day.

Wash, rinse, repeat

Let’s now fast-forward to more modern times. CFast, short for CompactFast, which I mentioned in both of my 2023 writeups (in the context of their use by my Blackmagic cameras), is based on CompactFlash (and is also managed by the CFA) but migrates from ATA to SATA. CFast 1.x dates from 2009 and is based on SATA 2.0; the backwards-compatible CFast 2.0 upgrades to SATA 3.0 but has seen limited-at-best industry uptake since being initially unveiled in 2012.

Why? Enter, for example, the alternative CFexpress, also managed by the CFA, which switches from SATA to the solid-state media-optimized NVM Express (i.e., NVMe) as its command set and to PCI Express (PCIe) as its hardware interface foundation (as I’d mentioned at the end of 2023), as well as coming in multiple dimensional options. The smaller Type A (at left in the following image) and larger Type B (right) card variants are today commonplace in the industry, with the even larger Type C conversely not yet in production to the best of my knowledge:

In this context, an overview of the earlier XQD standard also bears mention. XQD, once again now managed by the CFA (albeit initially announced solely by Sandisk, Sony and Nikon), dates from 2010. It’s dimensionally and connector-compatible with CFexpress Type B and is also based on PCIe, albeit only in a single-lane implementation (with PCIe 3.0 support added with XQD 2.0 in mid-2012). The XQD and CFExpress standards are therefore cross-compatible, although only to a degree, generally requiring firmware updates which not all camera, memory card reader and other system manufacturers have provided.

CFexpress 1.0, announced by the CFA in September 2016 as the successor to XQD, launched with support for PCIe 3.0, albeit this time in higher-bandwidth dual-lane form (for the size option now known as Type B and used by my high-end Canon and Panasonic cameras, among others). CFExpress 2.0, following in February 2019, added the single-lane PCIe Type A and quad-lane Type C options, along with upgrading the NVMe command set from 1.2 to 1.3. And the latest iteration, August 2023’s CFexpress 4.0, upgrades the supported PCIe interface to 4.0 (again, at up to four lanes with Type C), and the NVMe command set to 1.4. CFExpress 4.0-optimized systems are not yet in the market, to the best of my knowledge, but cards (such as this OWC Atlas Pro) are prevalent and backwards-compatible with existing cameras and such:

No, I don’t know what happened to CFexpress version 3.0, either. While buying a CFexpress 4.0 card now will leave potential performance “on the table” with CFexpress 2.0-only systems, it does provide obsolescence protection for subsequent camera-or-other upgrades you might make in the future. And conversely, if future-proofing isn’t a concern, you’ll be able to (as I’ve personally done) get some great deals on CFexpress 2.0 memory cards right now, despite overall semiconductor memory supply constraints, as manufactures strive to “fire sale” deplete their inventories of legacy product variants.

Don’t count out Donkey Kong

And what about the SD and related microSD card standards; are they in danger of falling by the wayside as these high-performance newcomers ramp into the market? Not if the SD Association has anything to say about it, specifically with next-generation “Express” offerings. See if you notice anything familiar trend-wise in the paragraphs that follow:

When the SD Association (SDA) first announced SD Express in June 2018, it set the bar high and opened a world of possibilities for manufacturers to integrate supercharged removable storage into their designs. SD Express is capable of delivering SSD performance levels of up to 4GB/sec. This makes it perfect for use in high-performance electronic devices and products. With the introduction of advanced security features in May 2022 found in the SD specification version 9, performance and versatility merge to create an innovative, and advanced powerhouse solution for SD memory cards.

SD Express leverages the PCI Express and NVMe interfaces and uses the well-known SD memory card form factor for compatibility with existing SD slot architectures. The SDA also introduced a microSD Express memory card format that is backward compatible with devices. SD Express is not just about SD memory cards getting faster, it is also about SD memory cards doing more.

After languishing for several years awaiting market demand that stubbornly refused to emerge, “Express” variants’ fortunes are finally looking up. Specifically, the microSD Express card is used in the Nintendo Switch 2 game console, notably (and singlehandedly) increasing the likelihood of a high-volume long-term future for the standard.

Blazing a trail

I’ll wrap up this writeup with coverage of a recently emergent sole-source memory card option (in spite of my earlier comment that I planned to avoid diving into past-history proprietary offerings) that I’d earlier caught mention of at The Verge and elsewhere. It’s Biwin’s Mini SSD:

Biwin is, if you hadn’t already guessed from the coin at left in this “stock” image, a China-based memory subsystem manufacturer (to the right of the 1-yuan coin is the rare U.S. $1 coin). Most of the products on the company’s website are industry standards-based: PCIe NVMe internal SSDs, for example, along with USB flash sticks and drives, DRAM DIMMs and SoDIMMs, SD/microSD and CFexpress memory cards (an image of which you saw earlier), and memory card readers. But with the Mini SSD, the company has apparently decided to try its hand at also going proprietary.

Interestingly, the Mini SSD is slightly larger (at 15x17x1.4 mm) than the microSD Express (15x11x1 mm) counterpart. And at least from a latest-generation ratified-spec standpoint, it’s seemingly no faster than microSD Express, either; both are based on dual-lane PCIe 4.0 and NVMe (once again: sound familiar?). The key differentiator that Biwin seems to be betting on is timing; as Ars Technica notes, currently available microSD Express cards “top out around 900MB per second, roughly the amount of bandwidth available from a single PCI Express 3.0 lane.”

Conversely, Biwin was demonstrating functional products at CES in January, claiming read speeds up to 3,700 MB/s and write speeds up to 3,400 MB/s (at least in combination with the company’s own card reader peripheral), and with capacities ranging from 512 GB to 2 TB. Biwin also touts Mini SSD’s IP68-rated dust- and water-proof chops. One note: while the company was referring to them as the “BL100” series late last summer, it’s now calling them “CL100”. Why?

There’s considerable interest in leveraging the bandwidth and other potential virtues of terahertz waves that occupy the spectrum between the conventional RF and optical worlds, generally considered to span 100 GHz (3 mm wavelength) to 10 THz (30 μm). However, managing electromagnetic energy at these wavelengths presents many challenges, as they are too short for most electronics, yet too long for all-optical components.

Nonetheless, there’s a significant amount of ongoing research in developing the materials and components needed, especially with many potential applications, including the emerging 6G standards being developed now.

At these frequencies and corresponding wavelengths, signal energy must be conveyed via waveguides—discrete wires won’t do, of course. But making the needed waveguide physical transitions is difficult when they are fabricated in silicon as part of a larger set of on-chip functions.

Addressing this issue, a team of researchers at The Skolkovo Institute of Science and Technology—or Skoltech, a private institute in Moscow—working with a team from KTH Royal Institute of Technology in Sweden, has developed a key technology that could support silicon-based terahertz waveguides and their on-chip transitions.

Their solution is based on carbon nanotubes, one of those amazing materials that keeps offering solutions to diverse problems. The single-wall carbon nanotube (SWCNT) was discovered in 1991 (see “A Brief Introduction of Carbon Nanotubes: History, Synthesis, and Properties“). Like fullerene and graphene, SWCNTs are one of the allotropes of carbon.

Allotropes present a different structural form of the same chemical element within the same physical state; because their atoms are bonded differently, allotropes have vastly different physical and chemical properties from each other—think diamond versus graphite.

A key challenge in building these complex terahertz arrangements is devising properly matched terminations. Without proper termination, reflections at device discontinuities can cascade, thus degrading performance and altering the intended operational profile. In addition, these terminations are necessary for characterization of multi-port devices such as directional couplers, where the unused ports must be terminated with matched loads.

The conventional solution is to use adiabatic or impedance-matched tapering of the waveguide cross-section to free space, gradually expanding the guided mode to induce radiation losses while operating as a dielectric rod antenna. However, the efficiency of these structures depends on the length of the tapering, therefore consuming valuable chip area; it can also radiate power in undesirable directions, thus complicating packaging, limiting integration density, and creating electromagnetic pollution.

Note that in the adiabatic-coupling approach, the optical mode is coupled from one waveguide to another by a slow change of a waveguide parameter (width, thickness, or both) such that the optical mode remains in the fundamental mode and does not couple to unwanted higher-order modes. As a result, the tapered waveguides need to be long enough to meet the requirements of the adiabatic conditions of slow change of waveguide parameter. However, at the same time, they need to meet the device compactness requirement. Therefore, there is a trade-off to be made

The research team devised and tested a carbon nanotube-based coating that blocks electromagnetic radiation, thereby creating waveguides compatible with terahertz wavelengths. The ultrathin single-walled carbon nanotube films that they synthesized are similar to those that they used previously to create small-scale components, such as lenses and antennas, but with a big difference, as this time it’s not for standalone components. Instead, they leveraged carbon-based material to control electromagnetic radiation in 2D-integrated optical circuits, eliminate interference, and enable additional functionality.

They demonstrated a compact, broadband termination by coating silicon dielectric rod waveguides (DRW) with ultrathin single-walled carbon nanotube films. Fabricated via a floating-catalyst (aerosol) chemical vapor-deposition process, the film thickness varies from 2 to 53 nm and was characterized in the 140-220 GHz range. A 53-nm thick film introduced up to 47 dB of attenuation while maintaining over 20 dB reflection loss, confirming nearly reflection-free absorption (Figure 1).

Figure 1 Reflection measurements of the SWCNT-loaded DRWs show ∣S₁₁∣ for the 6-mm long samples (a) and ∣S₁₁∣ for the 12-mm long samples (b). The light grey line is baseline reflection after calibration by measuring a thru-standard (flanges of the frequency extenders connected); dark grey is the reflection coefficient of an unloaded DRW. Source: Nature Communications

Shielding analysis shows absorption dominates over reflection, and they achieved a record specific shielding efficiency of 5.5 × 10⁹ dB cm²/g (Figure 2).

Figure 2 Shielding efficiency components for the SWCNT-coated dielectric waveguides: reflection component SE_R (a, b), absorption component SE_A. (c, d), and total shielding SE_T (e, f) for 6-mm (left column) and 12-mm (right column) samples over 140-220 GHz, with light grey as the equivalent shielding efficiency of an unloaded silicon waveguide provided for reference. Source: Nature Communications

This approach offers a footprint-efficient solution for high-density terahertz circuits without bulky, radiative terminations. The work is presented in their paper “Ultrathin Single-Walled Carbon Nanotube Surface Wave Absorbers for Terahertz Dielectric Waveguides” published in Nature Communications. It’s unfortunate that the paper does not have any microphotographs of the SWCNT waveguide and transitions in silicon, so you’ll just have to visualize those yourself.

Have you had any interaction with or uses for carbon nanotubes? If so, in what way? Do you see a role for them in any of your projects, whether terahertz or other?

Bill Schweber is a degreed senior EE who has written three textbooks, hundreds of technical articles, opinion columns, and product features. Prior to becoming an author and editor, he spent his entire hands-on career on the analog side by working on power supplies, sensors, signal conditioning, and wired and wireless communication links. His work experience includes many years at Analog Devices in applications and marketing.

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You might be feeling that your taxes have quietly turned into a year round worry. Maybe it started with a simple return and a basic tax preparer, but as the years went by, things became less simple. Now you have multiple income sources, maybe a side business, investments, or a big life change, and you are not sure if the person typing numbers into the software is really looking out for you. JuvoTax CPA firm in Greenwood Village.

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Because of that tension, you might be asking yourself a hard question. Is it enough to keep using a basic tax preparer, or is it time to bring in a Certified Public Accountant and get deeper guidance, not just data entry. The short version is this. If your financial life has grown more complex, if you are making bigger money decisions, or if you feel exposed in any way with the IRS, then hiring a CPA is not a luxury. It is protection and strategy.

The good news is that you do not have to guess. There are clear signs that it is time to move from a simple tax preparer to a more strategic partner. When you understand these signs, you can stop second guessing yourself and start getting the kind of help that matches where you are in life now, not where you were five years ago.

Are your taxes no longer “simple,” even if they used to be?

For many people, the story goes like this. Early on, your taxes were easy. One job, one W 2, maybe a student loan deduction. A basic tax preparer or even a DIY program worked fine. Then life happened. You bought a home. You started investing. Someone offered you freelance work. Suddenly your return grew thicker, and your questions grew sharper.

This is where the first sign appears. Your financial life is now layered, but your tax help has stayed basic. A general tax preparer can often handle straightforward returns. However, they may not be trained to give deeper advice on planning, entity choice, or complex deductions. The IRS itself explains that different tax credentials come with very different training and authority. You can see the differences in this IRS overview of tax preparer credentials and qualifications.

So where does that leave you. If you recognize any of these situations, it is a strong sign it may be time to hire a Certified Public Accountant instead of relying on a basic preparer.

What if you own or are starting a business. Maybe you sell online, run a small consulting practice, or own rental property. A tax preparer might put your numbers in the right boxes, but a CPA can help you decide how to structure your business, what you can legitimately deduct, and how to manage quarterly taxes so you are not surprised by a big bill.

What if you have significant investments. Stock options, RSUs, crypto, brokerage accounts, or multiple rental properties can make your return much more complex. Simple mistakes in timing or reporting can cost you thousands. A CPA can help plan for capital gains, loss harvesting, and long term tax impact, not just report what already happened.

What if your income or life is changing quickly. Marriage, divorce, a big promotion, moving states, or inheriting money all carry tax consequences. If you feel like you are guessing about the impact of these changes, that is another strong sign that a more strategic tax advisor is needed, not just a seasonal preparer.

Are you worried about risk, audits, or “getting it wrong” with the IRS?

There is a particular kind of stress that comes from feeling exposed. Maybe you got a letter from the IRS once and never forgot the feeling. Maybe your current preparer seems rushed, does not explain things, or shrugs off your questions, and you walk out thinking, “I hope that was right.”

This is the second major sign. You are no longer comfortable with “I hope.” You want to be able to say, “I understand what we did and why, and I know what would happen if the IRS asked questions.”

Here is where the difference between a basic tax preparer and a CPA really starts to matter. Not all preparers have the same authority to represent you or stand by your side if something goes wrong. The IRS shares guidance on this in its tips for choosing a tax professional, and many people are surprised to learn that someone who simply “does taxes” may not be qualified to help beyond filing the return.

If any of this sounds familiar, it is a sign to consider moving from a simple tax preparer vs CPA mindset and ask a different question. Who do you want in your corner if the IRS comes back with questions. A CPA is trained not just in tax law, but also in documentation, representation, and long term planning that reduces risk before it shows up as a letter.

Do you want strategy and planning, not just a once a year tax filing?

The third sign is more subtle, but just as important. You no longer see taxes as a once a year chore. You see that your tax choices connect to your bigger goals. Paying off debt. Saving for retirement. Funding your child’s education. Buying or selling a business. You start to realize that tax planning is really life planning, and that a quick annual appointment is not enough.

Many basic preparers are seasonal. They appear in January, disappear in April, and you may not hear from them again. A CPA is more likely to work with you all year, helping you make decisions in real time instead of cleaning up after the fact.

If you have ever thought, “I wish someone would just help me put all of this together,” that is your signal. You are looking for a true advisor. That is what a strong CPA relationship can offer.

How does hiring a CPA compare to staying with a basic tax preparer?

To make this more concrete, it can help to see the differences side by side. Of course, not every CPA or tax preparer is the same, but this comparison can help you frame the decision.

If you want more help thinking through who should prepare your return, the Taxpayer Advocate Service offers a useful, neutral overview on choosing a tax return preparer. It is designed to help you protect yourself and ask better questions, regardless of who you hire.

What can you do right now if you think you might need a CPA?

Once you suspect it is time to upgrade from a basic preparer to a more strategic partner, the next question is what to do next. Here are three concrete steps you can take this week.

1. Map your “complexity triggers” in one clear list

Sit down with a blank page and write out every factor that adds complexity to your taxes. Business income. Side gigs. Rental property. Stock options. Crypto. Multiple states. Marriage or divorce. Inheritance. Major medical bills. Anything that makes you pause or feel unsure belongs on that list.

When you see it all in one place, you can better judge whether a basic preparer is still a match for your reality. This also becomes a powerful tool when you talk to a CPA, because you can walk through each item together and ask how they would approach it.

2. Interview at least two CPAs, not just one

You are not just buying a tax return. You are choosing a long term advisor. Set up short calls with at least two CPAs and treat them like interviews. Ask about their experience with people like you. Business owners. High earners. Investors. Ask how they work outside of tax season. Ask how they charge. Flat fee. Hourly. Monthly.

Notice not only what they say, but how you feel. Do they explain things clearly. Do they invite questions. Do they respect your concerns. You deserve someone who treats your stress as real, and your goals as important.

3. Decide what “success” with your taxes looks like for you

Before you hire anyone, define what you want. Less anxiety about audits. More predictable tax bills. Better planning for retirement. Clear guidance on your business. When you know what success looks like, it becomes easier to see whether a CPA for tax planning is the right move or whether your situation is still simple enough for a basic preparer.

You might find that your goal is not to pay the absolute minimum tax this year. It might be to feel confident, to avoid surprises, and to build a plan that supports your life five or ten years from now. That is the kind of work a strong CPA relationship can support.

Moving forward with more confidence and less tax stress

If you see yourself in any of these signs, you are not overreacting. You are noticing that your life has grown, and your support system needs to grow with it. Choosing to hire a CPA instead of a tax preparer is really about choosing clarity over confusion, and strategy over scrambling.

You deserve more than a rushed appointment and a signature on a form. You deserve someone who will sit with your questions, understand your story, and help you make choices that protect you now and support where you want to go next. When you take that step, tax season stops feeling like a test you are not prepared for, and starts feeling like one more part of a plan you actually understand.

A slow withdrawal page is more likely to frustrate an online casino player than a missing game title. Most regulated casinos already offer large game libraries. What separates them is often the experience around the games. For players exploring jackpot city south Africa and other licensed operators, mobile access and payment processes can shape the experience long before game selection becomes an issue.

A Good Mobile Experience Matters

A page that works perfectly on desktop can feel awkward on a phone. Pages that load slowly, menus that cover half the screen and games that struggle to run properly can quickly become frustrating. Moving between the casino lobby, account settings and payment pages should feel straightforward, especially on smaller screens.

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According to the GSMA’s Mobile Economy Africa 2025 report, 416 million people across Africa were using mobile internet in 2024. For casino operators, that leaves less room for slow-loading pages and awkward mobile layouts. Connection quality also varies. Not everyone is using high-speed WiFi, so heavy pages and oversized graphics can have a noticeable impact on the experience. Slow-loading pages become far more noticeable when someone is trying to switch quickly between different parts of a casino.

Nobody Likes a Complicated Sign-Up Process

Verification is a normal part of regulated gambling, but problems usually appear when the process becomes inconsistent. Casinos need to confirm identities and comply with local requirements. The issue is usually not the checks themselves. Problems arise when players are unsure what documents are needed or why another verification request has appeared.

Login issues can be just as frustrating. Password recovery emails that never arrive or account settings hidden across several pages make simple tasks feel harder than they need to be. Someone may register on a mobile phone and return later on a laptop. Account information should remain accessible and consistent regardless of how they choose to log in.

Some people do not complete registration in one sitting. They might create an account on a phone and return later to finish verification on a laptop. If account information does not carry across properly, the process becomes harder than it needs to be.

Clear Payments Build Confidence

Depositing funds is usually straightforward. Withdrawals tend to receive more attention because that is where players spend the most time checking updates and processing information. Players want to know which payment methods are available and whether their withdrawal request has been received successfully.

Clear communication often matters as much as speed. If a withdrawal is being processed, players generally want updates rather than silence. Uncertainty creates frustration, even when the transaction itself is progressing normally. A payment does not necessarily feel slow because of the waiting time. It often feels slow when there is no indication of what is happening. Even a simple status update can remove much of the uncertainty.

According to the Worldpay Global Payments Report, digital wallets continue to increase their share of online transactions worldwide. As a result, many users now expect familiar and convenient payment options wherever they spend money online.

Players Want to Find Games Quickly

Game libraries have grown significantly over the past decade. It is common for online casinos to offer hundreds or even thousands of titles across slot games, table games and live dealer sections.

The problem becomes obvious when a player already knows what they want to play. Searching for a specific title should not take longer than the game itself. Search functions and categories help users move through a casino without wasting time. A player who has logged in specifically to play a favorite slot is unlikely to spend ten minutes searching for it.

Research by Nielsen Norman Group has consistently shown that users become frustrated when websites make information difficult to locate. This also applies to online casinos. If navigation feels awkward, players are more likely to leave than continue searching. New releases can create a similar problem. Popular titles are often easy to find for the first few weeks, but older games can quickly disappear into larger libraries if categories and search tools are not maintained properly.

Small Issues Can Be Memorable

Players do not always remember major technical failures. More often, it is the smaller issues that stand out over time. A balance that takes too long to refresh, a page that occasionally freezes while moving between sections, or repeated popups interrupting normal use can make a casino feel less dependable. On their own these problems may seem minor, but frequent interruptions can gradually reduce a player’s confidence in the platform.

Players often forgive an occasional technical problem. What becomes frustrating is seeing the same issue repeatedly. A slow-loading cashier page once was an inconvenience. Seeing it every week becomes part of how the platform is remembered.

A page loading slowly while reading information is one thing. The same delay during a deposit or withdrawal tends to attract much more attention because money is involved. Some casinos also overload pages with promotional banners and notifications. Promotions have their place, but they can become distracting when they compete with the main functions people are trying to use. Small design decisions can have a surprisingly large effect on how easy a platform feels to navigate, whether the product is an online casino or another type of digital service.

A player can tolerate the occasional missing game or promotional banner. Repeated problems with logging in or tracking a withdrawal tend to be remembered for much longer.

EMI (electromagnetic interference) can be a real nuisance in sensitive circuits. That might be from one device affecting another, but it can also happen when a circuit on a PCB interferes with another circuit on the same PCB (or another PCB in the same device). Engineering to prevent that entirely is really difficult and it helps a lot to be able to see where the interference is, which is why element14 Presents’ Clem Mayer converted an old 3D printer into a new EMI imager.

The goal here is to capture a “picture” of the device or PCB in question that shows the areas where EMI is highest. That picture looks like a heat map, with hot spots corresponding to areas of high EMI. But it isn’t something you can capture by snapping a photo with your Nikon. That’s where this EMI imager comes in.

Using an old 3D printer as a motion system, Mayer’s EMI imager moves a detector back and forth across the entire area, scanning EMI levels as it goes. At many points across that area, the system records both the XY coordinates and the EMI level. After scanning, a simple script can turn that data into a 2D image. 

A conventional camera mounted overhead also captures a normal photo. With the generated heat map overlaid onto the photo, the user can easily visualize the areas of the PCB or device that produce a lot of EMI.

The EMI detector is actually just an RTL-SDR module, which is affordable. It and the camera connect to a computer, which records the data. The 3D printer’s motion system operates under the control of an Arduino UNO Rev3 running Grbl 1.1, so it can run a simple G-code file that causes the toolhead (with detector) to move in a serpentine pattern across the scanning area.

If you have an old 3D printer gathering dust, this is an easy and affordable way to capture high-quality EMI images for diagnosing and improving designs.

The post An old 3D printer becomes a new EMI imager appeared first on Arduino Blog.

You’ve probably noticed that your car feels different when driving on gravel, compared to what you’re used to on asphalt — even normal road asphalt can feel different than the concrete of a bridge. A lot of the feeling you detect is the result of the vibrations caused by that particular surface and the sounds they make. Dan Velarde took advantage of that to give a robot terrain-sensing capability with just an IMU and microphone.

The purpose of this system, called GRIP (Ground Recognition Intelligence Platform), is to help a robot achieve better traction and control across different terrains. Many cars also have that capability, though you normally have to manually select the terrain type. In this case, GRIP enables the robot to automatically sense if it is on a normal flat surface, snow, gravel, or grass. It can then adjust motor output to accommodate that terrain.

It does so by classifying vibrations in the chassis with an IMU (inertial measurement unit) and acoustic signatures with a microphone. An Arduino® UNO Q monitors the IMU data output and sound from the microphone, then determines the surface type.

That would be very difficult to program for explicitly, because there is a lot of data without clean and easily distinguished thresholds. But it is exactly the kind of thing machine learning excels at.

Velarde leveraged Edge Impulse to train and deploy the ML model. He recorded training data while driving over the different surface types, which tells the model what to expect from the IMU and microphone on each surface. Upon deployment, the model can match up what it sees from the sensors to the training data.

In testing, the accuracy varied from one surface to another. Snow was the most reliable, at 91.4% accuracy. Gravel was the least reliable at 73.8% — though that is still pretty decent. 

The post This robot can identify terrain based on the vibrations it causes appeared first on Arduino Blog.

Founder George Hammel describes his Star Stream engineering team as “a pretty wild group.” A few of them aren’t certified engineers in the traditional sense, but all of them grew up solving problems in motorsports – an environment that rewards fast thinking, creative solutions, and zero tolerance for downtime. That background shows in what they’ve built.

Star Stream is a live video, telemetry, and data streaming service provider, built around Starlink connectivity and designed for the most demanding environments in racing. Their Streambox Pro Kit delivers ultra-low latency video from cockpit to pit wall on circuits and off-road courses alike. But as the demands of professional racing evolved, video alone stopped being enough.

After Hammel took part in Arduino Days 2026, we had a chance to dive deeper with him into how Star Stream is meeting challenges and innovating – moving from prototype to track-ready deployment faster than expected – thanks to the Arduino ecosystem’s open-source flexibility.

From video to vehicle intelligence

Teams today want real-time granular telemetry – engine data, GPS, environmental sensors, driver biometrics – delivered fast enough to influence decisions mid-race. That meant Star Stream needed a processing platform that was rugged, versatile, and smart enough to keep up with a vehicle’s own systems.

The answer became the Telemetrybox Pro, their onboard telemetry and biometric system, built around the Arduino^® UNO Q board. UNO Q pulls CAN bus frames in real-time, automatically detects and maps signal parameters, and translates raw vehicle data into meaningful telemetry – without any manual configuration from the user. Its machine learning capabilities mean the system doesn’t just read data, it learns from it. As Hammel puts it, “it’s also very smart with the machine learning capabilities that we can program from Star Stream into the device. And now we have the flexibility to make it learn, not just right now, but also well into the future. That gives us scalability.”

In practice, this means teams get real-time telemetry, biometrics, and course diagnostics through Star Stream’s mobile apps and web dashboards – something that until recently was exclusively available with Formula 1 budgets.

Built for the track, ready for the road

Star Stream has already put the Telemetrybox Pro through some of the most extreme conditions in motorsport. At Pikes Peak, where engines struggle with altitude and vehicles are tuned to the limit, a team running Star Stream’s system detected a loss of turbo boost pressure while the car was still climbing. The data reached the pit crew before the driver even reached the summit, giving the mechanics enough time to diagnose the problem, fix it, and send the car out for another run. Without real-time telemetry, Hammel says, the team’s weekend would have been over.

In Baja, where connectivity doesn’t exist until Starlink makes it possible, the stakes are different but just as real. Mid-race, Star Stream’s system flagged a tire losing pressure and a fuel situation developing – the chase crew radioed the driver and co-driver in time to pull over and fix it before the tire went flat. At a recent NORA Rally, a voltage drop was caught early enough that the team switched to a backup alternator before any damage occurred. “We or the chase crew, mechanics, crew chief, can tell what’s going on with the car before the people that are in the car usually know what’s happening,” Hammel explains.

The Telemetrybox Pro is already in commercial use, not just prototyping. Now, its same technology is being adapted well beyond motorsport: fleet services, automotive mechanics, and contractors – anyone who depends on vehicles to run a business – can use the same real-time vehicle health monitoring to reduce downtime, optimize workflows, and even feed data to insurers to demonstrate safe operation. 

Curious to find out more? Watch the full unveil video by Star Stream here and follow Star Stream on Facebook or Instagram.

Arduino and UNO are trademarks or registered trademarks of Arduino S.r.l

The post Star Stream is bringing F1-level telemetry to every race team – and every fleet – with Arduino UNO Q appeared first on Arduino Blog.

Artificial intelligence has already evolved from simple conversational assistants into autonomous systems capable of interacting with software, hardware, sensors, and even the physical world. The next frontier is not simply “chatting” with AI, but enabling AI agents to observe, reason, decide, and execute actions locally at the edge.

This shift becomes particularly interesting when combined with embedded systems. Why? Because traditionally, embedded development required deterministic programming, fixed automation logic, and carefully predefined behaviors. But now AI systems are capable of dynamically generating code, controlling peripherals, interacting with operating systems, and adapting behavior in real-time. And we see all of this happening in projects built around the Arduino^® UNO Q board.

“Think local” takes on a whole new meaning

What makes this especially compelling is that these agents can run locally.

Instead of relying entirely on cloud APIs and remote inference, developers are beginning to deploy autonomous AI systems directly on edge devices – reducing latency, improving privacy, lowering operational costs, and enabling offline functionality. Projects such as QClaw and the broader OpenClaw ecosystem are demonstrating how this model can work on UNO Q.

Our first dual-brain board is particularly well suited for this new generation of AI-native embedded simple systems because it combines two different computing worlds on the same platform. In simple words, this means you have one board where, on one side, there is a Linux-capable Qualcomm Dragonwing QRB2210 processor capable of running Python applications, Docker containers, networking stacks. On the other side, an STM32 microcontroller handles deterministic real-time operations such as GPIO access, peripheral control, and low-level hardware timing. This hybrid architecture allows developers to separate high-level reasoning from low-level execution, effectively creating systems where AI can “think” on Linux while the microcontroller interacts directly with the physical environment.

Your word is AI’s command

One of the most interesting frameworks emerging in this space is OpenClaw. Rather than being a language model itself, OpenClaw acts as an orchestration layer that connects large language models with tools, terminals, filesystems, APIs, and hardware interfaces. As described in the OpenClaw installation guide for Qualcomm^®and Arduino^®platforms, the framework enables AI models to move beyond pure text generation and become actionable agents capable of executing commands and interacting with their environment.

This changes the relationship between developers and embedded systems faster than ever. Instead of manually writing every line of code, users can increasingly interact with hardware through natural language. We’ve already showcased a good example of this approach here, demonstrating how OpenClaw can run on UNO Q to use conversational prompts to control hardware directly. Rather than opening an IDE and programming peripherals manually, you can ask the agent to blink LEDs, modify animations on the LED matrix, or generate entirely new interactions dynamically.

What makes these demonstrations powerful is the iterative workflow they enable. In one example, the AI agent generated code to display graphics on the LED matrix, uploaded the firmware, and then refined the visual output interactively through additional prompts. The interface to embedded systems effectively becomes conversational. Hardware prototyping starts looking less like firmware engineering and more like collaborative interaction with an intelligent assistant.

Fast, private, cheap AI agents? Cutting edge!

This concept evolves even further in the QClaw project, where the Arduino UNO Q becomes a fully local agentic assistant. In this architecture, the system is capable not only of generating code, but also of compiling sketches, uploading the compiled code, interacting with local services, and managing workflows autonomously. Within this scenario, the agent orchestrates the full pipeline from intent to execution.

An especially interesting direction is the growing trend toward fully local AI deployments. While many AI systems depend heavily on cloud-hosted models, several developers are exploring combinations of OpenClaw with Ollama and lightweight open-source LLMs to build completely offline agents. The article How to turn OpenClaw into a real Arduino agent using a free local LLM demonstrates how developers can run local inference directly on the device without sending prompts or data to external APIs. In this model, Ollama hosts the local language model while OpenClaw orchestrates tools and actions, allowing UNO Q to function as an autonomous AI node entirely within the local network.

This approach is particularly attractive for edge AI applications because it addresses many of the practical concerns associated with cloud AI. Sensitive data remains local, recurring API costs disappear, internet connectivity becomes optional, and response times improve significantly. Of course, local models are generally smaller and less capable than frontier cloud models, but for many embedded automation tasks the tradeoff is worthwhile. In fact, for hardware-centric workflows, deterministic execution and local responsiveness often matter more than absolute model intelligence.

Local AI meets the real world

The implications become even more interesting when AI agents start interacting with sensors and perception systems. A compelling example comes from this AI-powered gas stove monitoring project, where computer vision and local AI reasoning were combined to monitor kitchen burners and detect potentially dangerous situations. Instead of relying on rigid rule-based automation, the AI system interpreted contextual visual information and made decisions dynamically. 

This is an important shift because it demonstrates how edge AI agents can combine perception, reasoning, and physical interaction into unified systems capable of operating in real environments.

Safety first! Let UNO Q be your “hardware sandbox”

What emerges from all these projects is a broader transformation in how embedded systems may be designed in the future and how UNO Q allows this shift, acting as an accelerator. 

Traditionally, embedded devices were deterministic endpoints executing carefully predefined logic. AI agents introduce adaptability. Developers no longer need to explicitly define every possible branch of execution. Instead, they can define goals, permissions, tools, and constraints, allowing the agent to determine dynamically how tasks should be completed.

This does not eliminate traditional engineering. Rather, it shifts engineering effort toward architecture, orchestration, safety, and supervision. The challenge becomes designing systems where AI agents can act autonomously while remaining constrained, secure, and reliable.

Security is in fact one of the most important considerations in this new paradigm. AI agents often gain access to terminals, filesystems, APIs, and hardware interfaces, which introduces entirely new attack surfaces. One advantage of platforms such as UNO Q is the possibility of creating isolated “hardware sandboxes” dedicated to agent execution. Instead of granting AI systems unrestricted access to personal laptops or production environments, developers can deploy agents on dedicated edge hardware with limited permissions and compartmentalized resources. This physical separation is one of the most important deployment strategies for safe personal AI agents.

The bigger picture

The broader trend is clear: AI is moving toward the edge, becoming increasingly autonomous, multimodal, and physically interactive. UNO Q plays a relevant role not because it replaces cloud AI, but because it makes AI tangible – empowering developers, makers, researchers, and students to experiment with autonomous embedded intelligence locally, affordably, and safely. 

Ready to upgrade from chatbots to autonomous embedded collaborators? Get your hands on UNO Q and play an active role in the AI revolution!

Qualcomm branded products are products of Qualcomm Technologies, Inc. and/or its subsidiaries. Arduino, and UNO, and the Arduino logo are trademarks or registered trademarks of Arduino S.r.l.

The post Local AI agents on Arduino UNO Q appeared first on Arduino Blog.

Hey India!

If you’ve ever had an idea that could solve a real-world problem, not just live inside an app, but actually exist out there, this is your moment.

Across India, something exciting is happening. Makers, students, startups, and engineers are starting to move beyond software-only AI and into something far more tangible: building systems that can sense, think, and act in the real world. And Arduino^® with Robu.in (our local partner) has been right at the centre of this shift.

With accessible hardware and a growing ecosystem, Arduino has helped lower the barrier to entry for AI across India. Startups and MSMEs are now able to integrate AI into their products without needing massive R&D investment. Students are getting hands-on experience with production-ready tools. And through workshops, partnerships, and providing better access to hardware in cities and towns across India , innovation is no longer limited to just a few tech hubs.

At the same time, there’s a clear shift toward edge AI — where intelligence runs directly on devices rather than in the cloud. Together with Qualcomm Technologies, Arduino is helping developers build low-power, high-performance systems that can operate in real-world conditions. The result? A new generation of builders who aren’t just writing code, but creating complete, intelligent systems.

And that’s exactly what Physical AI is all about: combining sensors, computation, and action into systems that interact with their environment. Across India, we’re already seeing this come to life in smart agriculture, healthcare devices, industrial automation, and smart city solutions—projects built not just for demos, but for real impact.

Now, there’s an opportunity to take that even further.

The Arduino Physical AI Challenge is a free, national-level competition designed and run by Robu.in to bring this movement together and push it forward.

Learn more and register!

Robu.in invites anyone, from school students to creators and startups to build real-world AI systems using the Arduino^®UNOQ. Solo or teams of up to four, all skill levels are welcome.

What makes it exciting

30 Lakhs+ total prize pool — including special awards, so every type of builder from school students, to college teams, to women in tech and more, all have a real chance of winning something special.

Every winner and runner-up in the Robu.in Arduino Physical AI Challenge receives something that doesn’t show up in a bank account: all-expenses-paid mentorship at Qualcomm / Arduino.

For an engineering student or recent graduate, access to Qualcomm Technologies and Arduino engineers — the people building the silicon that powers AI on the edge is not a line you normally get to jump.

It’s the kind of exposure that shapes what you work on next. Whether you’re heading into a placement process, a startup, or research, “worked with Arduino engineers on Physical AI” is not a common CV line.

Key dates

Open for registration now, you’ll have the chance to submit your projects from June 15th onwards, with the final project submission deadline of July 31, 2026.

Final thoughts

India already has the talent, the creativity, and the “jugaad” mindset that makes innovation happen.

Now it also has the tools, the ecosystem and the opportunity. 

Don’t just learn AI. Don’t just watch innovation happen. Build something real. Start here!

Arduino and UNO are trademarks or registered trademarks of Arduino S.r.l

The post Build something real: Join the Arduino Physical AI Challenge India 2026! appeared first on Arduino Blog.

Abundant use of the AI acronym is increasingly evident at various industry events. Strip away the hype layer and look deeper, however, and interesting trends still emerge into view.

This is my third straight year covering Microsoft’s developer-focused conference, following up on the 2024 and 2025 show editions. And interestingly (at least to me), the event timing, both in an absolute sense and relative to other notable industry trade shows, has shifted each year.

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• 2024’s Build took place on May 21-23, the week after Google’s I/O developer event (May 14-16) and several weeks before Computex (June 4-7).
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• Last year, all three conferences took place on the same week.
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• And this year, the Google I/O and Microsoft Build cadence returned to separate-weeks spacing, two weeks apart this time. Conversely, Build and Computex were still in the same-week slot.
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Why the upfront focus on this seeming nuance? Well, for one thing, Computex conversely is a consumer-tailored show. That’s why, for example, Microsoft and Nvidia co-announced one new computer (information on which I’ll share shortly) at Computex, while introducing another with a different form factor but the exact same processing subsystem at Build.

Plus, in emphasizing a point that is likely already obvious to at least some of you, any chronological spacing between two companies’ events enables the latter to fine-tune its announcements and messaging to react to the former…and the more spacing the better from a reaction-robustness standpoint.

Speaking of announcements, let’s get to them, shall we? Microsoft CEO Satya Nadella and his various lieutenants, along with a couple of special guests, covered a lot of ground in the 2.5-hour kickoff keynote, the video of which I’ve embedded below. I’ll hit what I thought were the highlights in the following paragraphs.

AI inference-accelerating hardware

About those computers I just mentioned…stop me if you’ve heard this before. Microsoft and a partner roll out new Windows-on-Arm computer platforms, both mobile and mini-desktop in shape, and intended for both consumers and developers. Two years ago, that partner was Qualcomm, the SoCs were the Snapdragon X Elite and Plus, and the consumer mobile systems were the Surface Laptop and Pro (also accompanied by other OEMs, in a nod to Microsoft’s broader Windows-on-Arm aspirations). The developer mini-desktop was the Snapdragon Dev Kit for Windows, which never made it to production: Qualcomm “indefinitely paused” it only a few months later.

This outcome was more than a bit of a surprise to me, albeit not a complete surprise, as I’d been hearing for some time of both chronic hardware and software issues with the platform. That said, I already owned (and still use) its two Qualcomm application processor-based, developer-tailored predecessors, the Qualcomm-branded ECS LIVA Mini Box QC710:

and Microsoft’s “Project Volterra” (officially: Windows Dev Kit 2023) system:

So, the Snapdragon Dev Kit for Windows was unsurprisingly on my wish list, too.

Hopefully, Nvidia will have better luck, although the situation still feels somewhat embryonic. Let’s discuss consumer mobile system(s) first: launched at Computex and coming “this fall” at an as-yet-unannounced price, is the Microsoft Surface Laptop Ultra, based on Nvidia’s RTX Spark SoC.

While you might not immediately recognize the processor from its new marketing moniker, you’ve heard about it (from me, to be precise) before. It was previously known as the N1 and N1X, as well as the GB10, and it’s the outcome of a co-development project with MediaTek, who contributed the up-to-20-core CPU constellation and reportedly also took lead on full-chip integration, including the NVLink interconnect to the up-to-6,144 core GPU cluster.

The SoC’s development has been lengthy and troubled, if longstanding and widespread rumors are to be believed, and industry analyst skepticism remains existent. It first appeared in a Linux-based system, the DGX Spark (rebranded from its initial name, Project DIGITS), last October.

And now, Nvidia has determined that the RTX Spark is finally ready for Windows-based laptops (and not just from Microsoft itself, just as was the case two years before with Qualcomm). But not now. “This fall”. At a price to be announced later, but likely stratospheric if due only to the industry constraints-driven currently pricey “up to 128 GB of unified memory”. And what about the developer mini-desktop system, the Surface RTX Spark Dev Box, unveiled at Build?

There’s…umm…a waitlist. Microsoft CEO Nadella invited the Build attendees to join him on it. None of which inspires much in the way of confidence. Maybe one or both systems will be available for sale in time to end up on this November’s edition of my yearly “Holiday shopping guide for engineers”, but at this point, I’d be (pleasantly, mind you) surprised.

If you’re once again feeling déjà vu, by the way, it’s because Microsoft and Nvidia have been here before. The initial attempt at bringing a Windows-on-Arm system to market, the Surface with Windows RT, was based on an Nvidia Tegra SoC. I personally owned one and ended up tearing it apart after it eventually died. The hardware was first-rate for the time, although a dearth of native software in conjunction with woeful x86 code emulation support doomed it.

That was 2012. Jump forward again to the other, earlier-mentioned déjà vu moment, when Qualcomm’s announced partnership with Microsoft in 2024, and I feel compelled to point out that by no means is it seemingly deceased (or even on life support, for that matter). I recently acquired a gently used Microsoft Surface Pro 11 based on Qualcomm’s Snapdragon X Plus to replace my long-in-the tooth Surface Pro X.

The SP11 has 16 GBytes of RAM and a 1 TByte SSD and runs solely on its integrated battery all day with ease, even when emulating x86. Microsoft systems based on second-generation Snapdragon X2 Elite (and presumably also Plus) SoCs are seemingly coming soon. And on a similar note, Microsoft’s still churning out branded systems based on x86 CPUs, too, with most recent updates less than a month ago.

Agentic-centric O/Ss

One particularly memorable quote from Nadella in the keynote was the following:

“There’s a real platform shift. We’re moving from building operating systems, devices for apps, to agents.”

Indicative of this forecasted shift is Project Solara, explained in part by means of a conversation between Nadella and Qualcomm President and CEO Cristiano Amon.

At Build, there was also an Android-derived proof-of-concept demonstration showing agent-based interactions with (and between) a smart speaker with a screen, mobile devices, and intelligent ID cards. Google also spoke a great deal about agentic AI at its I/O developer conference two weeks ago; instead of repeating myself again, I’ll refer you to my coverage of that event for the background info if you need it.

Speaking of agents, Microsoft also announced Execution Containers, which keep agents from accessing unintended, critical regions of other agents and applications, the underlying operating system and system hardware. And for when you want to communicate with them, OpenClaw founder Peter Steinberger showed up on stage for introducing Scout, an OpenClaw AI Assistant gateway.

If you’re thinking it sounds at least something like Gemini Spark, which Google announced two weeks back, you’re not off-base. Remember my comments at the beginning of this piece about competing-event timing and ordering and effects on later-event messaging?

Homegrown models

Last but not least, let’s touch on an event topic that prompted the “AI Independence” title of this piece. In late April, OpenAI and Microsoft “redefined” their business relationship, which among other changes fundamentally freed both companies from the various exclusivity arrangements that had previously defined (and arguably dominated) it. While a “divorce” might be overstating the result (but then again, maybe not), a “softer” term such as “conscious uncoupling” wouldn’t be far off.

One tangible outcome of this redefinition was clearly evident this week, as Mustafa Suleyman, head of Microsoft AI, unveiled seven new homegrown AI models with capabilities spanning image, voice, and transcription functions, and claimed performance matching if not exceeding that of Google, OpenAI and other competitors’ models, both open- and closed-source. I was particularly interested in Suleyman’s declaration regarding MAI-Thinking-1, the flagship reasoning model, that:

“We trained it from the ground up on clean data, without distillation from third-party models.”

And with that, I’ll wrap up for today. As always, I welcome your thoughts in the comments on the topics I’ve covered here, as well as any others that might have caught your eye—Microsoft’s ongoing research work on quantum computing, for example, including the development of Majorana 2, the sequel to last year’s premier quantum computing chip from the company.

Next Monday, Tim Cook (along with, presumably, his CEO successor John Ternus) will hit the stage to kick off Apple’s yearly Worldwide Developers Conference (WWDC), completing the yearly big-tech-company developer conference triumvirate. I’ll see you back here then, if not before!

—Brian Dipert is the associate editor, as well as a contributing editor, at EDN.

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The post Build 2026: Accumulating evidence of Microsoft’s AI independence appeared first on EDN.

Recent frontier LLM inference benchmarks have highlighted a recurring pattern. GPU-based systems deliver outstanding throughput when latency is not a concern, but their performance drops sharply once real-time response requirements are imposed.

This behavior is sometimes attributed to software inefficiencies or suboptimal system tuning. In reality, the root cause lies much deeper. It reflects a fundamental mismatch between how GPUs are architected and how autoregressive inference works.

LLM inference: Prefill versus generation

To understand this limitation, it is useful to examine the two distinct phases of LLM inference: prefill and generation.

During the prefill phase, the model processes the entire input prompt in one pass. The prompt is tokenized, embedded, and propagated through every layer of the transformer network. At each layer, the model computes the attention relationships among all tokens and builds the key-value (KV) cache, which stores the intermediate data needed for subsequent token generation.

This stage maps extremely well onto GPU hardware. GPUs were designed to execute thousands of identical operations in parallel. In the prefill phase, the model performs massive matrix multiplications over large tensors, exactly the type of workload for which GPUs excel. When all tokens are available upfront, the calculations can be distributed across tens of thousands of cores, resulting in very high arithmetic utilization.

The generation phase is fundamentally different.

Once the KV cache has been created, the model begins producing output tokens one at a time. Each token depends on all tokens that came before it. This sequential dependency means that, regardless of how much hardware is available, the model cannot generate the next token until the current one has been completed.

For every generated token, the model must read the parameters for every layer, consult the KV cache, compute the next token probabilities, and then repeat the autoregressive process. The amount of computation per token is relatively modest, but the amount of data movement remains substantial.

Two faces of GPU architecture: Why modern GPUs struggle with real-time latency constraints

This is where the GPU architecture begins to work against the workload.

GPUs achieve peak efficiency when they execute large, highly parallel workloads with regular memory access patterns. Token generation offers neither. The workload is small, inherently sequential, and dominated by repeated memory accesses rather than dense arithmetic. Many of the GPU’s compute units remain idle while the device waits for data to arrive from high-bandwidth memory.

In other words, generation is not compute-bound; it’s memory-bound.

The distinction is crucial. In a compute-bound workload, adding more arithmetic units improves performance. In a memory-bound workload, performance is limited by how quickly data can be moved to the processors. Once memory bandwidth becomes the bottleneck, additional compute resources provide diminishing returns.

This explains why GPUs can appear extraordinarily efficient when throughput is measured without latency constraints. In that scenario, inference servers are free to buffer requests and combine them into large batches. Batching allows the system to process many token streams simultaneously, effectively transforming numerous small sequential tasks into a larger parallel workload that better matches the GPU’s strengths.

The role of batch sizes in GPU’s utilization

At first glance, batching in AI inference may appear straightforward. Unlike image inference where every sample in a batch completes simultaneously, LLM inference involves many conversations progressing independently and asynchronously. Some requests finish quickly, others may continue for hundreds or even thousands of decoding iterations, and new requests may arrive continuously while older conversations are still active.

The workload therefore becomes highly dynamic and irregular. Specifically, the generation of each request ends only when the model produces a special “end-of-sequence” token indicating that the response is complete.

This characteristic fundamentally changes the nature of inference scheduling.

This is where continuous batching becomes essential. Continuous batching is the runtime orchestration algorithm responsible for managing the simultaneous execution of multiple conversations across the same accelerator resources. Instead of treating inference as a sequence of isolated batches, the scheduler continuously inserts, removes, pauses, and resumes requests as tokens are generated.

The objective is to maximize hardware utilization while minimizing user-visible latency. As batch sizes increase, hardware utilization rises and throughput improves dramatically. However, batching comes at the cost of response time.

When users expect low latency, the system cannot afford to delay requests while waiting to accumulate a large batch. Each request must be processed almost immediately. As batch sizes shrink, the GPU loses the parallelism needed to keep its compute resources busy. Utilization falls, and throughput drops accordingly.

This is the central architectural limitation of GPUs in LLM inference.

The issue becomes even more pronounced when the same accelerator must handle both prefill and generation. Prefill is a large, compute-intensive task, while generation consists of many smaller, latency-sensitive operations. When new prompts arrive, the system may need to interrupt ongoing token generation to perform prompt processing. These context switches, often referred to as preemption, increase latency and reduce efficiency further.

Inference disaggregation: A clever shortcut to mitigate GPU’s inefficiencies

To mitigate this problem, system designers have begun disaggregating inference. Instead of assigning both phases to the same accelerator pool, they dedicate one group of GPUs to prefill and another to generation. The prefill GPUs build the KV cache and transfer it to the generation GPUs, which decode tokens independently.

This separation eliminates interference between the two phases and allows each group of GPUs to operate more efficiently. Prompt processing can proceed continuously without disrupting active token generation, and generation can continue without interruption.

In controlled benchmark environments, where prompt lengths, output lengths, and request patterns are known in advance, this approach can deliver substantial improvements.

Yet the underlying limitation of GPU architectures remains.

Inference disaggregation: Does it scale in real-world applications?

The generation phase is still sequential and memory bound. No amount of software optimization can eliminate the need to read model weights and cached data for each token. The disaggregated approach simply reduces scheduling inefficiencies and isolates the phases so that GPU resources are used more effectively.

Whether this strategy can scale efficiently in real-world applications depends on workload predictability.

The real-world AI services process a highly variable mix of requests. Some consist of long prompts and short responses. Others involve short prompts and long outputs. Demand can shift rapidly over time, changing the ideal ratio between prefill and generation resources.

Adapting to these changes requires dynamically reallocating accelerators. That process is not instantaneous. Devices must be initialized, model parameters loaded, and serving infrastructure synchronized. If traffic patterns are highly volatile, the overhead of reconfiguration can offset much of the benefit.

The broader lesson is that GPU performance in LLM inference is governed by more than raw TeraFLOPS.

The prefill phase showcases the strengths of GPUs, leveraging dense matrix operations and massive parallelism. The generation phase exposes their weaknesses, forcing highly parallel processors to execute a fundamentally sequential, memory-dominated workload.

As a result, the impressive throughput numbers often reported in unconstrained benchmarks can be misleading. They reflect idealized conditions in which batching hides architectural inefficiencies. Once latency constraints are introduced, those inefficiencies become visible.

The challenge for the industry is not simply to build larger GPUs, but to develop architectures and system designs better aligned with the realities of autoregressive inference.

Until then, the most significant limitation in real-time LLM serving will remain the same: generation is a sequential, memory-bound process running on hardware originally optimized for massively parallel computation.

Lauro Rizzatti is a business development executive with Vsora, a technology company offering semiconductor solutions that redefine design performance. He is a noted chip design verification consultant and industry expert on hardware emulation.

Editor’s Note

In a two-part series, contributor Lauro Rizzattti examines how LLM inference forced changes to MLPerf benchmarking. He will illustrate the evolution of the MLPerf benchmark and detail how generative AI forced a radical shift in AI hardware evaluation in the upcoming Part 2.

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The post The hidden bottleneck in LLM inference and the impact on MLPerf benchmarking appeared first on EDN.

Clock speeds get faster. Per-cycle (and per-clock edge) address and data dollops get larger. And protocols get more efficient. But here we’re talking about external, not internal, buses.

Back in 2023, I devoted two blog posts’ worth of content to comparing various memory card technologies, products and speed bin options, initially in March (identifying a fake card in the process) and more in-depth in July. Since then, I’ve come across numerous examples of both evolutionary and revolutionary successors to the devices discussed in that two-part series, not to mention those covered in even more distant-past writeups (themed, for example, around the cameras, digital audio recorders and other devices that leverage such storage).

I’ve had this follow-up piece in my to-do list for a while now, and I’ve finally decided to actualize my longstanding aspiration before the dust pile accumulating on this specific list entry gets any deeper. Not every technology to be discussed in the paragraphs to follow will likely achieve high-volume market success, mind you, with any sooner-or-later failures not necessarily the result of implementation shortcomings, either. Note, for example, that today’s (and past) industry supply constraints encourage manufacturers to “double down” on maximizing the output and profitability of existing approaches, versus devoting scarce capacity to dubious bets.

That said, win or lose there’s usually an interesting story behind each approach. Without further ado…and with the upfront qualifier that I’ll be intentionally delaying any discussion of USB-interface memory devices until later, since their connector locations compel them to be fully external to the system, either sticking straight out of it or cable-tethered to it…and that for related reasons, I won’t be covering eMMC and other fully internal formats, either…and lastly, that I’ll be skipping over legacy formats that were proprietary and/or otherwise non-impactful…

Historical precedents

A short writeup, “History Repeating” at Virginia Tech’s website, begins as follows:

Variations on the repeating-history theme appear alongside debates about attribution. Irish statesman Edmund Burke is often misquoted as having said, “Those who don’t know history are destined to repeat it.” Spanish philosopher George Santayana is credited with the aphorism, “Those who cannot remember the past are condemned to repeat it,” while British statesman Winston Churchill wrote, “Those that fail to learn from history are doomed to repeat it.”

Long-time readers may recall that I’ve referenced variants of this same quote theme in several past writeups, consistently with a negative connotation involving the downsides of ignorance to the past. That said, excessive dependence on history lessons can also be problematic, resulting in evolutionary, overly constraining baby-steps that suppress alternative more revolutionary strides, which may lead to failure but may also dramatically leap beyond traditional approaches.

I’ll leave you to decide for yourselves what to conclude from this first case study, admittedly too personal to likely allow me to be completely arms-length about it! Embedded within the tuple (card identifier) data structures reported by Intel’s Series 2 flash memory cards were the initials of the small team of developers, myself among them, who designed their ASIC (30 years ago…yikes!). I subsequently led the technical marketing launch of the 28F008SA 8 Mbit flash memories inside those same cards, followed by the definition, development and introduction of 16 and 32 Mbit component successors and cards based on them, all in the early-to-mid-1990s.

Products such as these, representing the industry’s first removable and high capacity (for the era, at least) memory cards, added these tuple structures and other enhancements in order to deliver full Personal Computer Memory Card International Association (PCMCIA, later known as PC Card) compatibility, in contrast to Series 1 precursors which were more elementary multi-component arrays along with address decode and chip select logic. Intel’s and others’ similar products were specifically referred to as linear flash memory PC Cards, both to differentiate them from other PCMCIA card types—modems, ISDN and SCSI, for example, and living on (at least to a degree) with CableCARDs—and from alternative ATA-interface flash memory cards.

The key difference between the two memory card types centered on where the flash media management intelligence was located: in the card itself for ATA flash PC Cards, thereby presenting a standardized hardware and software interface to the system regardless of what (and whose) media was inside, versus in the system, implemented as software and/or dedicated hardware, for the linear flash PC card approach. Proponents of the latter scheme touted its claimed reduced media bill-of-materials cost, not to mention the potential ability to direct-execute code out of it (acting as a big parallel-interface chip), but it was inherently relevant for only NOR (vs NAND) memory suppliers, along with being a “heavier lift” for system developers. For these and other reasons, the ATA approach eventually won out in the marketplace.

Miniaturization

That said, Intel and several of its NOR flash memory partner/competitors had also taken a stab at miniaturizing the linear flash PC Card with the creatively named (ha!) Miniature Card format:

Other flash memory suppliers countered with the ultimately much more popular CompactFlash card, now maintained by the aptly named CompactFlash Association (CFA), whose hardware interface was similarly PCMCIA-derived albeit instead (as with the ATA flash PC Card precursor) focused on the IDE/ATA (and later, UDMA) command set:

Amid this “where is the media management intelligence best located” debate, two other notable contending approaches of the same timeframe also bear mentioning. The first, SmartMedia, was championed by Toshiba (as well as, later, by its primary competitor, Samsung):

SmartMedia was essentially a single (although a few variants embedded multiple) NAND flash memory die embedded within a thin plastic membrane, plus a multi-contact metallic interface that wirebond-direct-connected to the die with no intervening media controller intelligence.

Conceptually sounds like linear flash PC Cards and their derivatives, doesn’t it? Yes…and no. For one thing, SmartMedia was much smaller than either Miniature Card or Compact Flash. For another, it was based on NAND flash memory, which was more HDD-like in its core attributes  (notably erase block size and speed) than NOR, simplifying system-side media management development. And then there was the fact that Toshiba wasn’t just a semiconductor supplier; its various systems divisions were potential SmartMedia implementers, and the company also did a good job of cultivating business from other Japanese and broader Asian systems manufacturers.

Finally, near the end of the last century (in 1997, to be exact), Sandisk and systems partners Siemens and Nokia unveiled the MultiMediaCard (MMC), which ultimately came in multiple dimension options, as well as in both standard and clock-boosted performance variants:

MMC is best known today in its aforementioned non-removable eMMC form, which itself is being slowly supplanted by the embedded variant of the MIPI- and SCSI-based Universal Flash Storage (UFS) (an organization whose own removable-version standard ironically has conversely been underwhelmingly adopted by the industry). Today’s generational successor to MMC is the Secure Digital (SD) card, originally referred to as SecureMMC:

which built on the MMC foundation with “enhancements including a digital rights management (DRM) feature, a more durable physical casing, and a mechanical write-protect switch.” The SD standard’s successive iterations have expanded the available clock speed, protocol and electrical contact count options in a backwards-compatible fashion to keep pace with flash memory performance gains, such as in this high-end V90 card from OWC:

The microSD Card derivative tackled substantive dimensional decreases with notable success; here’s one alongside the SmartMedia card I showed you earlier:

One interesting newer SD (and microSD) card specification variation that I became aware of recently when shopping for storage media for a couple of new Raspberry Pi cards is the Application Performance Class. Quoting from Kingston Technology documentation:

A new classification has been presented with the introduction of Android’s Adopted Storage Device feature. The App Performance Class assures minimum random and sequential performance speeds to meet both run and store execution time requirements under given conditions. It does this simultaneously while providing storage for pictures, videos, music, files and other important data. Basically, they’re ideal for use in smartphones and mobile gaming devices that run applications at random read and write speeds while also being used for storage.

 There are two ratings for the App Performance Class which are known as A1 and A2. A1 has a minimum random read of 1500 IOPS and a minimum random write of 500 IOPS while A2 has a minimum random read of 4000 IOPS and a minimum random write of 2000 IOPS. Both A1 and A2 have a minimum sustained write speed of 10MB/s. The App Performance Class is something to consider [editor: for example] when planning on installing Android apps on a microSD card.

And, by the way, unlike the SmartMedia competitor of the day, both MMC and successor SD Cards notably also embed (despite their smaller sizes) media management intelligence that simplifies and standardizes the system implementation. Moore’s Law strikes again, eh?

Hang tight; I’ll be right back

Believe it or not, I originally envisioned this being, and wrote it as, a single unified blog post. However, as thought of more (and more…and more…) things to include, the wordcount grew (and grew…and grew…), transforming it into something resembling a small book (I exaggerate, but you get my drift). Having passed through 1,500 words at the beginning of this paragraph, I’m instead going to pause for now, intending (God willing) to share the other half of this now-two-part series with you next week. Until then, please share in the comments your thoughts on what I’ve covered so far!

—Brian Dipert is the associate editor, as well as a contributing editor, at EDN.

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• Memory cards: Specifications and (more) deceptions
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• SD card speeds: question your assumptions
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• AI boom and the politics of HBM memory chips
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The post Memory card interfaces keep pace with the internal bus evolution race: Part 1 appeared first on EDN.

Editor’s note: This is a multi-part series on how to design a digital-controlled PFC. Previous entries: 

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• How to design a digital-controlled PFC, Part 1
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• How to design a digital-controlled PFC, Part 2
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• How to design a digital-controlled PFC, Part 3
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High efficiency is a mandatory requirement in some applications, especially in data centers. The recently announced 80 Plus Ruby certification sets the highest efficiency standard for data center power-supply units (PSUs), as shown in Table 1. The new efficiency requirement is not only higher than 80 Plus Titanium at each load condition, but also requires 90% efficiency at a 5% load, which has never been specified before.

Table 1 “Ruby” is the most recent and most stringent of the 80 Plus certification levels

With totem-pole bridgeless power factor correction (PFC) offering the best efficiency among all PFC topologies, digital control can further push the efficiency capabilities of this topology to new levels. In the fourth and final installment of this series, I will first introduce several digital methods to improve efficiency and then discuss some special PFC requirements including re-rush current control, electrical metering (e-metering) and PFC with a baby boost converter.

Dynamic dead time to achieve ZVS for synchronous switch

Theoretically, the PFC synchronous switch can operate with zero voltage switching (ZVS), but there must be a proper dead time between when the boost switch turns off and the synchronous switch turns on. As illustrated in Figure 1, assuming a positive cycle, when boost switch Q2 turns off, the inductor current (I_L) starts to charge the output capacitance (C_OSS) of Q2 and discharge the output capacitance C_OSS of Q1, and the switch-node voltage rises.

If Q1 turns on before the switch-node voltage rises to the output voltage (V_OUT), this is hard switching, and the switching losses are high. If Q1 turns on too late after the switch-node voltage rises to V_OUT, the current will conduct in the third quadrant of Q1 with diode-like behavior. Since the gallium nitride field-effect transistor used for Q1 has a higher V_SD drop compared to a silicon metal-oxide semiconductor field-effect transistor body diode, this induces a higher third-quadrant conduction loss.

\nFigure 1 This equivalent circuit describes a PFC synchronous switch during dead time. (Source: Texas Instruments)

Ideally, Q1 should turn on at the exact moment when the switch-node voltage rises to V_OUT. Given the I_L, V_OUT and C_OSS of Q1 and Q2, the following equation calculates the time to charge the switch node from 0 to V_OUT:

You can use firmware to dynamically adjust the dead time calculated from the equation to maintain ZVS for the synchronous switch.

CCM_TCM multimode control

A totem-pole bridgeless PFC can operate in either continuous conduction mode (CCM) or triangular current mode (TCM); each has its advantages and disadvantages. Table 2 provides a high-level comparison between the two modes.

Table 2 Continuous conduction mode (CCM) and triangular current mode (TCM) options both have pros and cons for totem-pole power factor correction (PFC) operation purposes.

Ideally, the totem-pole bridgeless PFC could operate with multimode, as shown in Figure 2. At heavy loads or at the peak of an AC half cycle, the desired PFC input current is high and the PFC operates in CCM mode. When the load reduces or around the AC zero-crossing area where the desired PFC input current is low, the PFC switches to TCM mode and operates with ZVS.

Compared to pure CCM mode, this multimode operation has better efficiency at light loads because of ZVS. Compared to pure TCM mode, because the inductor current ripple is much lower, there is no need to use multiphase interleaved operation; therefore, this multimode operation significantly reduces the size and system costs. By combining the advantages of both CCM and TCM, this multimode operation can meet both high-efficiency and high-power-density requirements.

\nFigure 2 CCM_TCM multimode operation can meet both high-efficiency and high-power-density requirements. (Source: Texas Instruments)

Reference 1 provides details about this control method and its implementation. Figure 3 compares the efficiency (tested on the same board) between this CCM_TCM multimode control method and traditional CCM control, with efficiency improving as much as 2%.

(a)	(b)

Figure 3 CCM_TCM multimode control delivers efficiency improvements versus traditional CCM control in both low line (a) and high line (b) environments. (Source: Texas Instruments)

Special burst mode – AC cycle skipping

Burst mode is widely used to improve efficiency at light loads. Unlike traditional pulse-width modulation (PWM) pulse-skipping burst mode, where you skip PWM pulses randomly, here I would like to introduce a special burst mode: AC cycle skipping, which is you skip one or more AC cycles in light loads.

In other words, you would turn the PFC off for one or more AC cycles and turn the PFC back on for the next AC cycle. The turnon and turnoff instance occurs at the AC zero crossing such that the whole AC cycle is skipped. Since PFC turnon and turnoff at inductor current equal zero, there is less stress and electromagnetic interference.

The number of AC cycles to skip is reverse-proportional to the load; the lighter the load, the more AC cycles skipped. Figure 4 shows the skipping of one and two AC cycles, respectively. Channel 1 is the AC voltage, and channel 4 is the AC current.

(a)	(b)

Figure 4 Shown here is AC cycle skipping at a light loads: one cycle (a) and two cycles (b). (Source: Texas Instruments)

Once the PFC turns off, the switching losses, driving losses and reverse-recovery losses all drop to zero, and the power losses are just the PFC standby power.

When turning off the PFC to skip AC cycles, both the current loop and voltage loop need to be frozen; otherwise, the integrators in those loops will build up to generate a big PWM pulse when the PFC turns back on, causing a large current spike.

Determining whether the PFC enters a light load requires the load information. Normally there is no current sensor at the PFC output; therefore, it’s not possible to directly measure the output load. However, because the PFC voltage-loop output is proportional to the load, you can use the voltage-loop output as a rough indicator to determine whether the PFC is operating with a light load.

If you must precisely skip an appropriate number of AC cycles to maintain V_OUT ripple within a specified range, you will need accurate load information, which you can obtain through an integrated e-meter function that I will discuss after the next section.

A big concern with AC cycle skipping is the V_OUT drop during a load transient. Assuming that a load step-up occurs when the PFC is off, V_OUT may drop too much.

To address this issue, you can compare V_OUT to a predefined threshold through a comparator. Once V_OUT is below this threshold, the PFC will immediately exit burst mode, disable AC cycle skipping, and return to normal operation. The PFC will handle the transient response as if there is no such special burst mode.

AC cycle skipping can also help reduce total harmonic distortion (THD) at light loads. Reference 2 compares THD with and without this method.

Re-rush current limit

The AC input voltage could suddenly drop out when PFC is operating normally. Since the load is still applied, the PFC V_OUT could drop to a lower value. Then, when the AC voltage returns, if the AC input voltage is higher than V_OUT, there will be an inrush current. This current is called the re-rush current.

Previously, the re-rush current was unspecified and there was no special control action for this event, it solely relied on the power-stage components’ ability to handle re-rush current. Test results show that re-rush current can jump more than 10 times higher than the PFC-rated maximum input current. Such a high re-rush current can either damage the power supply or reduce its lifetime.

The recently released Modular Hardware System– Common Redundant Power Supply (M-CRPS) specification requires limiting re-rush current when the input voltage resumes after an input brownout or blackout event on the power supply used in a data center. As shown in Figure 5, the root-mean-square (RMS) value of re-rush current should not exceed 5 times the maximum PSU rating over one-half cycle of input frequency, or 3.5 times the maximum PSU rating over one cycle of input frequency. In addition, the input current of the PSU should settle to a value less than or equal to two times the maximum PSU rating of the PSU within two cycles of the input frequency after applying the AC input.

\nFigure 5 The Modular Hardware System– Common Redundant Power Supply (M-CRPS) specification documents limits on both re-rush current and timing. (Source: Texas Instruments)

Reference 3 provides a firmware-based solution to handle this re-rush current so that when the AC voltage comes back from dropout, both the re-rush current (when V_IN > V_OUT) and the non-re-rush current (when V_IN < V_OUT) are well controlled – not exceeding the M-CRPS limit specification, but high enough to rapidly boost V_OUT.

E-metering

Power supplies in data centers are required to measure the input power in real time and report the measurement to the host; this is called e-metering. The M-CRPS specification requires an input power measurement error within ±1% when the load is >125W, within ±1.25W when the load is between 50W and 125W, and within ±5W when the load is <50W. To achieve such high measurement accuracy, the e-meter function is traditionally implemented through a dedicated metering device, as shown in Figure 6a.

(a)	(b)

Figure 6 These circuit diagrams show a traditional e-meter and PFC control (a), as well as combining an e-meter with PFC control (b). (Source: Texas Instruments)

A current shunt placed on the PFC input side senses the input current, with a voltage divider (not shown in Figure 6a) across the AC line and AC neutral senses the input voltage. A dedicated metering device receives this current and voltage information and calculates the input power and input RMS current information, sending the results to the host.

With a digital controller, since analog-to-digital converters (ADCs) of the microcontroller (MCU) are measuring both the input voltage and input current, it becomes possible to integrate the e-meter function into PFC control code. Figure 6b shows this e-meter configuration.

A current shunt senses the input current and an isolated delta-sigma modulator (the AMC1306 from Texas Instruments) measures the voltage drop across the current shunt. The delta-sigma modulator output is sent to the PFC controller MCU. The current information will be used for both e-metering and PFC current-loop control. A voltage divider senses the input voltage, which is then measured by the MCU’s ADC directly, just as in traditional PFC control. Reference 4 has more details about e-meter implementation and calculation.

Integrating e-meter functionality into PFC control code eliminates the need for a dedicated metering device, not only reducing system costs, but also simplifying printed circuit board layout and expediting the design process.

PFC with a baby boost converter

In server applications, a bulk capacitor (C_BULK in Figure 7) is required to hold PSU output in regulation for more than 10mS after AC dropout. To accomplish this, a 3kW server PSU would need a total capacitance of over 1.3mF, which would consume at least 30% of the overall space. To improve power density, you must reduce the bulk capacitance.

Adding a baby boost converter between PFC and DC/DC, as shown in Figure 7 and described in Reference 5, can achieve high power density. The baby boost converter is a compact boost converter that only operates during AC dropout events.

\nFigure 7 A PFC with a baby boost converter can achieve high power density. (Source: Texas Instruments)

Figure 8 is a flow chart of baby boost converter operation. During normal operation, the baby boost converter is off and bypassed by a BYPASS FET Q4. When AC line dropout occurs and V_BULK drops to a certain level, Q4 turns off, and the baby boost converter turns on to allow V_BB to maintain its nominal value. If AC power returns, V_BULK will rise; once V_BULK rises to a certain level, MCU turns off the baby boost converter, turns on BYPASS FET Q4, and the PFC resumes normal operation.

\nFigure 8 This flow chart outlines the various stages of baby boost converter operation.

Conclusion

I hope that the information imparted in this series enables you to design your own digital-controlled PFC and meet ever-more-strict specifications. You will find that digital control is so flexible that is possible to implement advanced control algorithms that would be difficult to implement with analog control. A digital-controlled power supply also offers impressive performance.

References

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1. Sun, Bosheng. “A novel CCM-TCM multimode control method for totem-pole bridgeless PFC.” Texas Instruments Analog Design Journal article, literature No. SLYT877, 1Q 2026.
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2. Sun, Bosheng. “AC cycle skipping improves PFC light-load efficiency.” Texas Instruments Analog Design Journal article, literature No. SLYT585, 3Q 2014.
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3. Sun, Bosheng. “How to limit PFC re-rush current.” Texas Instruments Analog Design Journal article, literature No. SLYT865, 1Q 2025.
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4. Sun, Bosheng. “A low-cost and high-accuracy e-meter solution.” EDN, Aug. 26, 2024.
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5. Yu, Sheng-Yang, Benjamin Genereaux, and LiehChung Yin. “Improve power density with a baby boost converter in a PFC circuit.” Texas Instruments Analog Design Journal article, literature No. SLYT830, 2Q 2022.
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The post How to design a digital-controlled PFC, Part 4 appeared first on EDN.

Any discussion of modern AI system performance must include MLCommons and its MLPerf benchmark suite, which has become the industry’s de facto standard for measuring machine learning performance. Since its debut in 2018, MLPerf has provided a neutral, peer-reviewed framework for comparing hardware and software platforms across a broad range of AI workloads.

The original MLPerf benchmarks reflected the dominant AI workloads of the late 2010s. Early inference tests focused on models such as image classification with ResNet-50, natural language processing with Bidirectional Encoder Representations from Transformers (BERT), object detection with RetinaNet, and recommendation with Deep Learning Recommendation Model (DLRM).

These workloads were important and representative at the time, but they shared one characteristic: they were highly parallel and relatively easy to map onto GPU architectures.

For several years, benchmark results reinforced a simple narrative. Each new generation of accelerators delivered higher throughput, lower latency, and better energy efficiency. Because the workloads aligned well with GPU strengths, the benchmark curves rose steadily and predictably.

The generative AI shockwave: Rewriting the rules of MLPerf

Autoregressive LLMs introduced a fundamentally different inference pattern. Prompt processing remained highly parallel, but token generation became sequential and memory bound. Suddenly, raw TeraFLOPS no longer told the whole story.

MLPerf began incorporating this new reality in stages. Inference v4.0 introduced the first LLM benchmark based on Meta platform Llama 2 70B. This benchmark measured token throughput and provided the industry with its first standardized method for comparing LLM inference systems.

MLPerf Inference v5.0 released in 2025 significantly expanded the generative AI focus. It added Llama 3.1 405B Instruct, a 405-billion parameter model with a 128,000-token context window. The benchmark also introduced an interactive variant of Llama 2 70B that imposed strict limits on Time to First Token (TTFT) and Time Per Output Token (TPOT), two metrics that directly capture user experience in conversational applications.

These additions were pivotal because they exposed the core weakness of GPU-based inference systems. When unconstrained by latency, GPUs could buffer requests, create large batches, and deliver excellent throughput. Under interactive latency limits, batching opportunities shrank, hardware utilization dropped, and throughput fell sharply.

In other words, MLPerf began measuring not just how fast a system could run under ideal conditions, but also how responsive it remained under realistic conditions.

Inference disaggregation: Optimization of resources

This evolution reached another milestone in MLPerf Inference v5.1 and the emerging v6.x era. The benchmark suite broadened its focus to include increasingly sophisticated workloads, including reasoning models such as DeepSeek-R1 and more demanding long-context applications. At the same time, submissions began showcasing system-level optimizations such as inference disaggregation, where prompt processing and decoding are assigned to different accelerator pools.

Disaggregation has become one of the most consequential developments in modern inference benchmarking.

Historically, MLPerf treated each benchmark run as a single system under test, leaving vendors free to optimize their hardware and software stacks as they saw fit. As long as submissions complied with accuracy and latency requirements, any architectural technique was fair game.

This openness allowed participants to introduce increasingly sophisticated serving strategies. One of the most effective has been the separation of prefill and generation across distinct groups of accelerators. The prefill cluster handles the compute-intensive prompt processing stage, while the generation cluster focuses exclusively on token decoding.

In controlled benchmark scenarios, where prompt lengths and output lengths are known in advance, disaggregation can produce dramatic gains. By eliminating interference between the two phases, systems reduce preemption and improve latency-sensitive throughput.

Yet this raises an important question. Does the benchmark still measure accelerator capability, or is it increasingly measuring system orchestration? The answer is both.

Modern AI performance depends on the interaction between processor, memory hierarchy, interconnect fabric, runtime software, and serving algorithms. MLPerf has evolved accordingly. It now rewards system-level innovation rather than isolated chip performance.

That shift is entirely appropriate, but it also means benchmark results must be interpreted carefully.

A disaggregated configuration optimized for long document summarization may perform brilliantly in MLPerf while delivering more modest benefits in production environments where workloads vary continuously. Real-world deployments must cope with unpredictable prompt lengths, bursty traffic, and rapidly changing ratios of prefill to generation demand.

Consequently, MLPerf increasingly measures a system’s ability to align resources with a known workload profile. This is a valuable metric, but it’s not synonymous with universal real-world performance.

Illustrative comparison: MLPerf 5.x versus MLPerf 6.x

Table below illustrates how benchmark methodology evolved as MLPerf shifted from throughput-oriented LLM tests to more latency-sensitive and system-aware workloads. The numbers are representative rather than exact, but they reflect the broad trends seen in published results and vendor disclosures.

Publicly discussed MLPerf inference results based on Llama 3.1 405B LLM run on a leading-edge GPU-based processor in three scenarios (off-line, server mode, and interactive mode) highlight MLPerf’s evolution. Source: Author

From chip benchmark to system benchmark

The history of MLPerf mirrors the evolution of AI itself.

The early benchmark suites focused on relatively static workloads that aligned naturally with the strengths of GPU architectures. Tasks such as image recognition, recommendation systems, and conventional deep learning inference relied heavily on dense matrix operations and large-scale parallelism, allowing GPUs to demonstrate exceptional throughput and scalability. In that era, benchmark leadership was closely associated with raw compute capability, memory bandwidth, and increasingly larger accelerator configurations.

The rise of generative AI fundamentally changed that equation.

As autoregressive LLMs became the dominant workload, MLPerf evolved accordingly, introducing larger models, longer context windows, interactive server scenarios, and increasingly strict latency constraints. These additions exposed a critical reality: while GPUs remain extraordinarily efficient during the highly parallel prefill phase, they are far less efficient during token generation, where inference becomes sequential, memory-bound, and heavily dependent on latency-sensitive execution.

This shift transformed the meaning of benchmark performance.

Modern MLPerf results no longer measure the capabilities of an isolated accelerator alone. Instead, they measure the effectiveness of an entire inference architecture.

Disaggregation, scheduling policies, key-value (KV) cache management, streaming pipelines, runtime orchestration, and workload balancing have become just as important as the underlying silicon itself. In many cases, the benchmark winner is no longer the system with the most compute power, but the one that most effectively adapts a fundamentally sequential workload to hardware originally designed for massively parallel graphics and HPC computation.

As a result, benchmark interpretation has become significantly more nuanced. The headline numbers increasingly reflect how intelligently the system orchestrates resources across racks of accelerators, separates prefill from generation, minimizes preemption, and maintains throughput under realistic latency constraints. MLPerf has evolved from a pure hardware benchmark into a broader measure of system architecture and software orchestration.

At the same time, this evolution reveals something even more profound. The latest MLPerf 6.x requirements implicitly highlight the growing limitations of conventional GPU architectures for real-time LLM inference. The industry has reached a point where increasingly sophisticated scheduling mechanisms and disaggregated serving infrastructures are being used to compensate for a deeper architectural mismatch between autoregressive inference and massively parallel processors.

In many respects, the benchmark itself is beginning to suggest the next major transition in AI infrastructure design.

Rather than continuing to optimize architectures originally developed for graphics rendering and parallel numerical computing, the future may require entirely new inference-centric architectures built specifically for the unique characteristics of the LLM generation. Such architectures would need to deliver high utilization and low latency even with very small batch sizes—potentially down to a single user request—while minimizing data movement, reducing memory bottlenecks, and supporting continuous token generation without relying on increasingly complex orchestration layers to hide inefficiencies.

In that sense, MLPerf has become more than a benchmark suite. It is now a window into the architectural tensions shaping the future of AI computing, revealing both the extraordinary adaptability of modern accelerator systems and the growing need for a fundamentally new class of inference hardware designed from the ground up for the realities of autoregressive AI.

Lauro Rizzatti is a business development executive with Vsora, a technology company offering semiconductor solutions that redefine design performance. He is a noted chip design verification consultant and industry expert on hardware emulation.

Editor’s Note

This is Part 2 of the mini-series that examines how LLM inference forced changes to MLPerf benchmarking. In Part 1, contributor Lauro Rizzattti analyzes LLM inference across its two processing phases—prefill versus generation—and highlights how this workflow exposes structural inefficiencies in GPU-based accelerators.

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You might be feeling like your taxes have grown a second head. It started simply enough when you lived and worked in one place. Then you took a remote job in another state, maybe your company sent you abroad for a few months, or you began investing in another country. Suddenly, you are hearing about accounting in Tampa, state “nexus,” foreign tax credits, treaties, and reporting rules you never knew existed.

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If you feel a mix of confusion and quiet anxiety, that is very normal. Multi-state and international tax rules are confusing even for seasoned professionals. You are not behind. You are just in a more complex situation than basic tax software was built to handle.

Here is the short version of what you need to know. When your life crosses state or national borders, you can end up owing tax in more than one place on the same income. The goal is to stay compliant while not overpaying. A good accounting firm for multi-state and international tax issues helps you map where you are exposed, claim every credit and treaty benefit available, and keep the paperwork straight so you can sleep at night.

So, where does that leave you today? You might be wondering whether you can keep doing it yourself or whether it is time to bring in help. To answer that, it helps to see what is actually going on under the surface.

Why multi-state and international taxes feel so overwhelming

On the surface, taxes sound simple. You earn money, you report it, you pay what you owe. The stress shows up when you realize that several different governments may claim a right to tax the same dollar of income.

For example, imagine you live in State A but work remotely for a company in State B. State A may tax you because you live there. State B may also tax you because your employer is based there. If you travel and work from State C for part of the year, it may join the party too. Each state has its own rules, its own forms, and its own deadlines. None of them is responsible for making life easy for you.

Now add international tax rules on top. Maybe you are a U.S. citizen working abroad. The U.S. still expects you to file and report worldwide income. The country where you are working may tax that same income, too. There may be a tax treaty. There may be foreign tax credits. There may also be extra reporting on foreign bank accounts or investments. You can see where the stress comes from.

If you want a sense of how complex international rules can be, it helps to look directly at the IRS resources for international taxpayers and their detailed FAQs on international individual tax matters. Just scrolling those pages can feel like drinking from a fire hose.

Because of this tension between “I want to get it right” and “I do not want to become a tax expert,” you may feel stuck. You know mistakes can be expensive. You also know that ignoring the problem is not an option.

Where accounting firms actually change the story for you

This is where a professional accounting firm comes in. Not as a magic wand, but as a guide that already knows the terrain. Think of multi-state and international tax planning as a puzzle where the picture is your life. The firm’s job is to help you fit the pieces together so nothing important is missing and nothing is forced into the wrong place.

Here are some of the specific ways they help.

1. Sorting out where you really owe tax

An experienced firm will start by asking where you live, where you work, where your employer is based, where your clients are, and where your assets sit. They translate that into a map of which states and countries can tax you, and to what extent.

For state issues, they will often use resources like official state government tax websites to verify current rules for residency, source income, and filing thresholds. For international issues, they look at tax treaties, local laws, and how they interact with U.S. rules.

2. Preventing double taxation

Paying tax twice on the same dollar is one of the biggest fears. A good firm focuses on reducing that. They identify credits, exclusions, and treaty positions that allow you to pay once, in the right place, and then get relief elsewhere.

For instance, if you are a U.S. citizen working in another country, they might use the foreign earned income exclusion, foreign tax credits, or both, depending on your income level and how much you are paying abroad. If you are earning in multiple states, they look for credits for taxes paid to other states and make sure the math is done correctly.

3. Handling the reporting that most people miss

The tax you owe is only part of the story. Many problems come from missed forms. Foreign bank account reports, disclosures for foreign companies or trusts, state nonresident returns, and composite returns through partnerships are all easy to overlook.

An accounting firm keeps a checklist tailored to your situation. They track what is required, what is optional but helpful, and how long you need to keep records. This alone can save you from painful letters years later.

4. Planning forward, not just cleaning up the past

When you work with a firm that understands multi-jurisdiction tax services, you can start making decisions with taxes in mind instead of reacting after the fact. That might mean changing how you are paid, where you work from, how you structure a business, or how you hold investments.

Instead of learning the hard way that your three-month work stint created a state filing requirement or that a foreign investment fund carries harsh U.S. tax treatment, you talk through ideas in advance and avoid surprises.

Should you do it yourself or hire an accounting firm

You might be wondering whether you can keep handling everything on your own. That is a fair question, especially if you are careful and detail-oriented. The answer depends on your situation, your risk tolerance, and how much time you want to spend learning tax rules.

There is no single right answer. The real question is how much complexity you can reasonably manage on your own without sacrificing your time, your peace of mind, or your financial security.

Three concrete steps you can take right now

1. Map your “tax footprint” on one page

Write down, for the last year and the coming year, where you lived, where you worked from, where your employer or clients are located, and where your bank and investment accounts sit. Include any foreign accounts or assets, even if they seem small.

This simple map often reveals more exposure than you expected. It also gives any accounting firm you speak with a clear starting point, which can save you time and money.

2. Gather proof before you need it

Collect documents that show where you were and when. Pay stubs, travel itineraries, remote work agreements, lease or mortgage statements, and residency certificates can all matter. For foreign issues, gather account statements, local tax returns, and any letters from foreign tax authorities.

You do not need to organize everything perfectly. Just making sure the records exist and are backed up puts you ahead of many people in similar situations.

3. Have a short, focused conversation with a professional

Even if you are not ready for ongoing services, a one-time consultation with an accounting firm that understands cross-border and multi-state tax services can be eye-opening. Go in with your one-page footprint map and your main questions. For example.

“Which states and countries do you think I need to file in?”

“Where do you see the biggest risk if I keep doing this myself?”

“Are there any simple changes I can make this year to reduce my tax or my risk?”

That conversation can help you decide whether to keep handling things on your own, get targeted help, or build an ongoing relationship.

Moving forward with more clarity and less fear

You do not need to become an expert in tax treaties or state nexus rules to protect yourself. You just need enough awareness to know when your situation has outgrown “simple,” and enough support to bridge that gap.

If you are juggling income in several states, working remotely across borders, or managing foreign accounts, you are not alone. Many capable, responsible people are in the same place, quietly worried about getting a letter in the mail. The difference between ongoing anxiety and steady confidence is often a clear plan and the right guide.

Consider taking one small step this week. Map your tax footprint, pull a few key documents, or schedule a short call with an accounting firm that understands multi-state and international tax issues. You do not have to solve everything at once. You just need to start moving from uncertainty toward clarity, one decision at a time.

There was a time when computers were exciting and fun. Now most of them feel like commodity appliances — no more interesting than a washing machine or a toaster. Joe longed for the good ol’ days of 8-bit personal computers, so he used a trio of Arduino development boards to design his own “fantasy computer.”

This is reminiscent of fantasy video games consoles, such as the PICO-8. More than anything else, it is about recreating the feeling and experience of using an 8-bit personal computer. But unlike the PICO-8, which is really just software that can run on a wide range of hardware, the Pinecone DAISY-1 isn’t separable from its hardware. 

That hardware consists of three different development boards: an Arduino Due (runs the OS and BASIC interpreter), an Arduino Mega 2560 Rev3 (acts as a video processor), and an Arduino UNO Rev3 (does audio processing). The Due communicates with the Mega and the Uno via UART. There is also a separate ESP8266 board pretending to be a modem, giving the DAISY-1 access to Wi-Fi.

All of those fit inside the stripped enclosure of a VTech Laser 50, which was a very inexpensive 8-bit computer from the ‘80s that was like an even cheaper version of the TRS-80 Model 100 (though it was built around a Z80, so maybe the Epson PX-8 would be a more appropriate comparison). 

But the Laser 50’s internals were gutted to accommodate those Arduino boards and so Joe had to build his own system for the hardware. That is DaisyBASIC and it incorporates aspects of several of the classic BASIC implementations that first introduced so many of us to programming. It also has some nifty upgrades, including network access via that ESP8266 modem and storage on a networked computer running a small Python server.

Joe even went through the trouble of creating an in-universe reference guide — actually usable in the real world — inspired by similar materials from the past.

The post The Pinecone DAISY-1 is a fantasy 8-bit computer that exists in reality appeared first on Arduino Blog.

Gardening is a prime application for smart automation, because plant care requires a lot of monitoring, but is relatively simple to execute. Large-scale agricultural operations are already highly automated, so why not do the same thing with your house plants? Giovanni Mannara (AKA Ingeimaks) did so in style by building this smart planter system that does everything.

Before we even get to the technical details, we have to point out that this smart planter looks amazing. It is the kind of planter a person would be happy to display. Mannara had a talented friend design the 3D-printed outer shell of the planter, so he could focus on the engineering tasks.

The first step was selecting a brain and Mannara chose an Arduino® UNO Q (4GB) for the job. Like any “smart planter,” it does the basics of controlling lights and watering (powered via MOSFETs), plus monitoring soil moisture levels and ambient environmental conditions, the latter through a BME280 sensor.

But the use of the UNO Q allowed for dramatically higher intelligence. It looks at the plant through a USB webcam and is able to determine its health by running a computer vision model deployed with Edge Impulse. Sensor readings can do a lot, but the visual monitoring gives the smart planter even more capability. It can tell, for example, if the leaves wilt. Combined with the data from the sensors, that is very powerful. 

Once a plant is in place, the smart planter can do most of the care automatically. But there is an integrated display to show important status information and a web interface, which provides more detail and manual control. Real-time alerts are also sent over Telegram, enabling Mannara to take immediate action remotely.

It looks great and it should keep plants healthier than most of us manage!

The post This stunning smart planter tracks plant health and handles daily care appeared first on Arduino Blog.

Edge AI is evolving quickly. It was the end of 2022 when the world saw the first Cloud AI tool available to everyone, accessible through a simple and intuitive chat. In less than four years, models have been refined, distilled, optimized, quantized – at record-breaking speed – to meet the needs of the first generation of edge systems focused mostly on detection and classification: identifying an object, recognizing a keyword, or triggering an action when a predefined event occurs.

The landscape is changing so quickly that the conversation is now already shifting toward something more interesting. Devices are starting to move from simple recognition to local understanding.

So instead of asking, “What is this?”‘ developers are beginning to ask:

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• “What is happening here?”
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• “What does this information mean?”
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• “What action should the system take next?”
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This is where local AI agents, LLMs, and intelligent workflows start becoming relevant at the edge.

That does not mean every device suddenly needs to run massive cloud-scale models. In most real-world scenarios, the goal is not running the biggest possible AI model – but running the right intelligence close to where data is generated. This is exactly the space where the Arduino^® UNO Q board shows its full potential.

By combining Debian Linux with a real-time STM32 microcontroller, UNO Q creates a hybrid platform where developers can experiment with practical local intelligence while still interacting reliably with sensors, actuators, cameras, industrial signals, and physical systems.

The Linux side can manage higher-level orchestration, local AI frameworks, APIs, dashboards, and model execution. The microcontroller side continues handling deterministic I/O, timing-sensitive interactions, and hardware control. That balance makes it possible to explore a new category of edge applications that don’t immediately depend on cloud infrastructure.

Now, let’s briefly explore three major directions in which UNO Q is contributing to reshaping edge computing. This is the introduction to a series of posts, where we’ll dive into each of these topics in more detail.

Building local AI agents on UNO Q

With the latest developments of agentic AI making headlines in the tech-world news, the next step is creating systems capable of reasoning about tasks and coordinating actions locally.

AI agents are essentially workflows where models interact with tools, hardware, APIs, sensors, or software services to complete specific objectives. On UNO Q, this means creating systems that observe the environment, interpret context, and trigger actions directly on the device. 

For example, David Groom ran OpenClaw on UNO Q to access embedded hardware conversationally, with a zero code approach – but an agent could also query and analyze information coming from sensors, summarize machine conditions, read visual states from a camera, or interact with connected services while still keeping the execution flow local. The interesting part is creating focused systems that are useful, understandable, and deployable in real products.

Because UNO Q combines Linux with real-time hardware control, these agents can move beyond chat interfaces and directly interact with the physical world. Interested in finding out more? Stay tuned for the dedicated article in this series.

Start experimenting with radical accessibility, following David’s example here.

Running local LLMs on UNO Q

Local language models are opening the door to a different type of edge interaction.

Instead of sending every request to the cloud, developers can run compact models directly on the device for task-specific workflows such as local assistants, OCR (optical character recognition), status summarization, command parsing, or contextual responses.

There are huge advantages to this in terms of privacy, any time keeping sensitive operational data on-device matters. But the real game-changer in this type of application is the reduced dependency on connectivity paired with improved responsiveness, resulting in systems that continue to operate without skipping a beat even when the network is unavailable.

UNO Q provides a practical platform for these experiments thanks to its Debian Linux environment, support for local AI frameworks, and compatibility with optimized inference workflows. Check out the documentation on this Project Hub entry by Robuinlabs to build your own private AI assistant, creating a local LLM chatbot that can run even when the internet is down or connection is not available.

There are, of course, constraints to what models can realistically run on the board, and on the computational power that can be expected from the nimble and cost-effective UNO Q. However, the trade-off may often prove perfectly acceptable for many experiments, prototypes, and a wide range of light applications. You don’t need a sledgehammer to crack a nut!

We’ll dive deeper into all of this in the next blog post in this series.

Build your own AI assistant with a local LLM chatbot, thanks to Robuinlab’s tutorial here.

Automating AI workflows on UNO Q 

The final step goes beyond single models or isolated agents.

Modern AI systems increasingly rely on workflows composed of multiple stages: capturing information, analyzing context, generating responses, triggering actions, and coordinating software execution. This includes workflows like local audio transcription and object recognition pipelines, multi-source data acquisition and automation systems: a great example of how all of this can fit together is Kevin McAleer’s “Nibsy” project, an AI agent that watches you work, listens to what you say, and at the end of a session writes the tutorial for you.

In these scenarios, the AI model becomes part of a larger orchestration pipeline rather than a standalone feature.

Using UNO Q is particularly interesting here because it allows developers to combine multiple layers together: Linux applications, Python environments, AI frameworks, cloud-connected services, local APIs, and deterministic microcontroller logic – all running side by side. Some workflows may use local models entirely on-device. Others may combine local execution with cloud-based reasoning depending on latency, privacy, or computational requirements.

The important shift is that UNO Q is no longer limited to simple inference. It enables solutions that coordinate complex operational workflows while remaining closely connected to the physical environment. We’ll see a few inspiring examples of how this can happen in a dedicated blog post. 

Explore how AI can automate complex projects in the example documented by Kevin here.

From AI demos to useful edge systems

One of the biggest misconceptions around AI at the edge is that success is measured by running the largest possible model. In reality, most successful deployments are built around smaller, focused systems designed for specific operational goals – such as:

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• Reading text locally from a camera feed
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• Recognizing gestures without streaming video to the cloud
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• Summarizing machine states
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• Interpreting operator commands
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• Triggering actions from simple contextual understanding
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• And many other practical examples of intelligence creating real value directly on-device!
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UNO Q makes experimenting and building applications approachable by combining familiar Linux development with the flexibility of the Arduino ecosystem and real-time hardware interaction. All of it is built leveraging Arduino^® App Lab and the Bricks available there.

Over the next three articles in this series, we’ll explore how local AI agents, LLMs, and complex AI workflows can move from experimentation into practical edge applications running on UNO Q. Are you ready to explore with us?

Arduino, and UNO, and the Arduino logo are trademarks or registered trademarks of Arduino S.r.l.

The post Beyond Edge AI: bringing local intelligence to Arduino UNO Q appeared first on Arduino Blog.

The planet is facing a crisis in energy demand versus supply, and data centers are at the center of this dilemma due to the increasing demand from new data-intensive applications. This article will explore the causes of data center inefficiency and speculate on methods to improve efficiency. It will also acknowledge the U.S. Department of Energy’s analysis on energy efficiency, which provides a basis for this work.

Energy demand and where it’s being used

The announcement that Three Mile Island nuclear reactor was being recommissioned to power an AI data center might have been shocking news to some, but it’s no secret in the industry that the exploding demand for energy is outpacing our ability to deliver power to data centers. For the first time, power efficiency is now a higher priority to data center architects than performance of the individual components.

Semiconductor Research Corp. modeled this increase in energy demand in the context of the planet’s projected energy generation capacity, which includes the assumption that more nuclear power plants will be deployed. Figure 1 shows a daunting projection, and the potential for the lines of supply and demand to intersect around the year 2055 has the electronics industry rethinking its choices in how data centers can be designed.

Figure 1 The worldwide energy consumption trends show that we will eventually consume more energy than we produce. Source: Stanford University

Sadasivan Shankar at Stanford University broke down the places where we are spending that energy. In addition to AI, another culprit in energy demand is cryptocurrency. When combined, AI and crypto are consuming over 1.5% of the planet’s energy already. Some projections estimate that their data consumption will increase to 3% by 2030 and 4.4% by 2035 (see Figure 2). Note the scaling for the Y-axis in Figure 2: Applications such as cryptocoin mining require 18 orders of magnitude more energy than the base instructions on which the computers operate.

Figure 2 The energy demands for AI and cryptocurrency are a magnitude greater than that of other operations. Source: The U.S. Department of Energy

With this in mind, it makes sense to determine the efficiency of a data center by measuring the work accomplished for each watt that is spent. Figure 3 breaks down the power consumption per operation. It’s critical to note that almost every operation in the top two-thirds of the table refers to moving data around, while the bottom third of the table represents data processing.

Figure 3 Data centers consume different amounts of power for different functions. Source: Wolley Inc.

The memory, storage, and communications hierarchy is commonly shown as a pyramid, with processor registers at the top, various levels of cache followed by DRAM, then storage and communications at the bottom. This article will use this simplistic model, as shown later in Figure 5. The pyramid’s biggest issue is that it does not highlight how each resource is on a separate bus. In addition, moving information from one resource to another typically involves multiple movements on many buses, each of which consumes power and generates heat.

Figure 4 shows an example in which an application is read from the disk though the CPU across one channel—for instance, a PCIe—to be written to the memory over another channel (for example, a DDR), only to be read back to the CPU one cache line at a time to execute the application and store the temporary results back to the memory.

Figure 4 Here is how data movement demands high power. Source: IEEE

The application may read content across a communications channel, such as PCIe to a wide area network, then crunch that data to be written back to the disk. Even in this simple example, it’s obvious that data processing is an exceptionally minor outcome and that data movement is dominant. The percentage of data operated upon rather than moved around is close to zero as to be unmeasurable.

Why focus on memory?

Memory utilization is a focus area because there is a high potential to make substantial improvements in energy efficiency. Memory consumes as much power as many CPUs, at about 22% of server power. The increasing number of tiers of memory creates both the best and worst of trends.

The good news is that more power-efficient memories are being added closer to the processor. The bad news is that these near-memory tiers have limited capacity and require additional larger capacity, higher power memories to keep filling the datasets into the local memory. The power consumption of each tier adds to the total power footprint.

High bandwidth memory (HBM), for example, offers an interface around 1.5 pJ/bit, which compares favorably to a double data rate memory module at 15pJ/bit (see Figure 5). Unfortunately, these memories still burn significant power—for instance, 75 W or 100 W per HBM stack—and they are co-located with the high-power processor on the same substrate. This makes cooling extremely challenging compared to DDR modules, which are around 15 W each but located farther from the processor in areas that may be air-cooled.

Figure 5 Memory and accompanying storage consume considerable amounts of energy. Source: Monolithic Power Systems

Efficiency by tier

Speculation can improve system performance tremendously, but speculation always implies waste as well—even processor registers have implied waste. A system variable with a 32-bit integer that never assumes a value outside the range 1 to 10 has an implied waste factor of 87.5%. Processor caches have very high hit rates of 95% and higher, so one could invert that number to imply a 5% waste. DRAM access efficiency drops the further the memory is from the processor, with direct attached DDR memory at 27% waste and CXL-attached DDR at over 40% waste.

These numbers may not sound bad until one considers the activity inside each DRAM that allows cache line hit rates. The majority of processors operate with a 64-byte cache line. Consider how 64 bytes map to the internal structure of a DRAM. Each DRAM has an internal page buffer of 1 kB, and DRAMs are typically combined into ranks for 10 DRAMs energized per access (see Figure 6).

Figure 6 DRAMs are typically combined into ranks for 10 DRAMs energized per access. Source: Monolithic Power Systems

To fulfill a single cache line, a DRAM module is “activated” to read 1 kB from each DRAM into its sense amplifiers, or 10 kB across the width of the module. 64 bytes are read and sent to the processor. DRAM activation is destructive—the cells of the memory core are wiped out by the activation—so the cells must be rewritten from the sense amplifiers back into the core. The math for a single random access is 20 kB moved for 64 bytes of work, or 99.7% waste.

This factor of 0.3% efficiency is only against that movement of a 64-byte cache line. If that DRAM tier is operating at a 60% hit rate, efficiency drops to 0.18%. If only 1 byte from that cache line was actually needed, the waste factor increases to 99.98%. As you can see in this simple example, data center efficiency is rapidly approaching zero.

Another form of speculation that improves system performance is execution and access speculation, where a processor may pre-load code on both sides of a branch condition in case the branch is taken. Many SSDs do the same, pre-loading pages that may be accessed. These forms of speculation have 100% waste if the branch is not taken or the access is never made.

Total cost of ownership (TCO)

With electricity access becoming a bottleneck for data center expansion, architects are finally acknowledging that total cost of ownership (TCO) is a primary factor driving system design. While processor vendors focus strictly on performance, their customers are forced to determine whether they can power these machines and cool them. By some estimates, cooling a data center is currently consuming 43% of the cost of operating a data center, which is equivalent to the 43% required to run the machines themselves.

This expenditure is driving architects to measure efficiency not only as petaFLOPS/second but also petaFLOPS/watt-hour.

Improving memory energy efficiency

Improving the accuracy of speculative accesses is an obvious key to taming memory subsystem power consumption. Similar to telling a doctor “It hurts when I do this,” system architects should ask the question, “Is this speculative access successful often enough to pay for the energy consumed?”

For example, if a CXL memory module is in a memory pool and shared by multiple processors, what is the hit rate on any particular bank of DRAM? Should a page be left open, delaying precharge in case of another hit on that row of memory or be closed, issuing the precharge immediately under the assumption it will not be accessed?

Non-uniform memory access (NUMA) has been in server architectures for years to allow tightly coupled processors to share memory resources as demand shifts. However, multiple hops for each memory access can more than triple the power consumed, whereas moving the task to a processor closer to the memory resource can significantly reduce power (see Figure 7). Computational storage is a variation of task relocation that has had some success, though this success is limited by standards for the tasks executed on the devices.

Figure 7 For a server DRAM module, moving the task to a processor closer to the memory resource can significantly reduce power. Source: Monolithic Power Systems

Similarly, placing data in the appropriate tier of memory can have a significant impact on energy consumption. Figure 8 shows the temperature of the data, where hot data is accessed often, and cold data is accessed less often.

Figure 8 Map data based on how often it’s accessed to determine its temperature (where “hotter” data is accessed more often). Source: Monolithic Power Systems

Persistent memory is a system option that can be exploited for data reliability. Persistent memory is either based on a memory technology that does not lose its contents if the power fails (for example, MRAM) or uses an energy source to maintain data integrity by saving DRAM contents in a non-volatile memory (NVM), such as a flash-on power failure. Persistent memory can also be thought of as a significant way to reduce system power by eliminating the need for “checkpointing,” or saving intermediate results (see Figure 9). In many systems, checkpointing is responsible for 7% to 8% of the system traffic and therefore power.

Figure 9 Persistent memory can reduce checkpointing. Source: Monolithic Power Systems

Hybrid memory modules that combine storage and direct access memory on the same module are available to minimize system traffic as well. For example, flash memory mounted as an SSD can be coupled with DRAM, which is directly accessed by a cache line at a time. The efficiency of hybrid modules comes from the statistic of the typical 4-kB block moved from SSD to system memory; only 100 bytes on average are used, which results in an efficiency of only 2.5%.

Software has a huge impact on efficiency

Hardware cannot fix every challenge; software plays a significant role in taming this beast, too. Zooming in on the power consumed by data type, orders of magnitude more power are used for complex and large data types such as floating point, whereas integer math consumes far less power (see Figure 10). This may be as simple as programmers considering the range of values needed by variables in their software. For example, “for (i=0; i<10; i++)” does not need for i to use a 32-bit counter value.

Figure 10 Software plays a significant role in energy consumption. Source: The U.S. Department of Energy

The choice of variable types is sometimes the result of using the wrong programming language for the task (see Figure 11). Not all programming languages allow much flexibility in choosing the data types for variables, and these impacts are magnified tremendously by the matrix math employed by languages such as Python, a common tool for AI applications. Python has another energy-consuming characteristic: the programmer source is compiled to bytecode and then interpreted by a virtual machine as opposed to C programming, which compiles to processor native codes.

Figure 11 Programming languages can be ranked based on their energy consumption. Source: Wireunwired Research

You can’t fix what you can’t measure

Measuring runtime power is a key to tuning efficiency. The voltage regulators for memory modules—such as the MPQ8894, MPQ8895, and MPQ8896—are power management integrated circuits (PMICs) with an integrated system management interface to I²C, I³C, or SidebandBus. This system management interface allows the host system to interrogate the PMIC while the system is running. The current used by each voltage rail can be read from the PMIC to calculate the total power for the memory module while running test and measurement programs, or even while customer applications are running.

Triggers may be configured into the PMICs, and these devices can keep logs of any conditions that exceed the expected maximums. The host system may respond to the triggers by reading the telemetry registers and then acting on those conditions, such as by throttling applications that exceed system-imposed limits.

Choosing the right PMIC is a power-saving measure. With improved 4% power regulation efficiency when compared to competing solutions, this results in a total data center power reduction of 2%. For a typical 300 megawatt-hour installation, this would reduce power by 6 MWh and CO₂ emissions by roughly 4 metric tons per year.

The power balancing act

Data centers are projected to keep increasing power demands until they become physically or financially impossible to expand. So, the total cost of ownership has become a focus for all datacenter architects as they balance the needs for performance from their customers with the reality of providing those services in a cost-effective manner.

Data center efficiency, as measured by the data processed vs. data moved around, is embarrassingly low. However, there are several ways to adjust efficiency, from cache management parameters to speculation priorities. Resource and job allocation over fabrics such as NUMA and CXL enable new classes of optimization.

The careful selection of energy efficient components such as voltage regulators can play a significant role in reducing the energy use of a data center. Every percentage of efficiency improvement leads to major reductions in CO₂ emissions, a leading cause of pollution. Voltage regulators, for instance, take a holistic view of the system solution, providing high efficiency coupled with methods for measuring and fine tuning the solution to achieve optimal power savings.

Software plays a huge role in efficiency as well, from the low-level allocation of data types to the choice of programming languages for each task. In addition, measuring system efficiency at runtime helps data center operators monitor the health of the system and give insight into ways to improve or limit power as needed. Next, telemetry information helps system software to understand where energy is being used.

Most importantly, TCO analysis requires a change in mindset from operations per second to operations per watt-hour, a major shift forced on the industry by skyrocketing power demand. The use of high efficiency voltage regulators helps reduce data center energy usage, which lowers the cost of providing data services.

Bill Gervasi is principal memory solutions architect at Monolithic Power Systems.

Related Content

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• Get a grip on your data center power efficiency
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• Why Data Centers Must Become System‑Aware
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• Space-Station Tech Pivots to Cool AI Data Centers
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• Data Centers in Space: A Brilliant Idea or Delusional?
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• Data center power meets rising energy demands amid AI boom
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The post Taming the beast: Memory efficiency in an AI/crypto world appeared first on EDN.

A fundamentally new approach is required to fuse AI-driven automation and multiphysics intelligence across the entire design and manufacturing flow. That was the crux of the keynote by Synopsys president and CEO Sassine Ghazi at the SAFE Forum 2026, held by Samsung Foundry in San Jose, California.

Ghazi especially mentioned design and technology co-optimization (DTCO) initiatives for synthesis and layout, as well as sign-off, delivering meaningful power, performance, and area (PPA) enhancements. He also talked about the design partnership between Samsung Foundry and Synopsys, which encompasses production-ready, AI-powered EDA tools, certified interface IP, and silicon-based test capabilities.

Hyung-Ock Kim, VP and head of the Foundry Design Technology Team at Samsung Electronics, echoed similar views, stressing the need for close alignment across design, test, and manufacturing to ensure the success of AI and multi-die designs on advanced nodes.

He also presented an update on Samsung Foundry’s collaboration with Samsung for production-ready, AI-powered digital and analog flows. “Our continued close collaboration with Synopsys delivers silicon-based, customer-validated solutions that help our customers reduce design integration risk, improve silicon predictability, and move confidently from design to production for their most innovative solutions,” Kim said.

Ravi Subramanian, chief product management officer at Synopsys, briefed on AI-powered digital and analog flows for Samsung’s second- and third-generation 2-nm processes. “As designs become more heterogeneous, customers need production-ready, silicon-proven solutions that address complexity and minimize risk from silicon to systems,” he said. “Our work with Samsung Foundry translates years of DTCO and silicon learning into enablement that helps our customers get their advanced designs to market quickly and with confidence.”

The partnership encompasses AI-powered EDA flows, multiphysics sign-off, interface IPs, and silicon-based test patters. Source: Synopsys

Below are the five key tenets of this design partnership between Samsung Foundry and Synopsys.

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1. Production-ready digital and analog flows for 2-nm process
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As part of DTCO initiatives, Synopsys Fusion Compiler delivers measurable power and performance improvements in the third-generation 2-nm class process compared to the second-generation 2-nm class process.

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1. Sign-off with certified multiphysics capabilities
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Synopsys PrimeShield process sensitivity analysis and PVT Explorer support design-specific optimization and engineering change order (ECO) decisions during sign-off. That leads to frequency improvement of up to 2.7% within 5% leakage current degradation. Moreover, Synopsys Totem-SC, a newly certified electromigration (EM) and IR drop analysis solution, improves silicon design power integrity and reliability in second-generation 2-nm and 4-nm class processes.

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1. 3DIC with hybrid copper bonding
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Samsung Foundry and Synopsys have joined hands to enable scalable 3D multi-die designs through certified multiphysics signoff solutions delivered within Synopsys 3DIC Compiler, a unified exploration-to-signoff platform being validated on a hybrid copper bonding (HCB) 3D test chip.

This platform brings together planning, implementation, and multiphysics analysis to enable co-optimization across integrated compute, memory, and advanced packaging systems for Samsung’s 3DIC solutions with HCB technology. And it replaces manual, margin-based approaches with automated, AI-driven system optimization to accelerate productivity and enhance the quality of results (QoR).

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1. Interface and foundation IP portfolio
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Synopsys offers a broad portfolio of IPs across Samsung Foundry’s advanced processes, ranging from 14-nm, 8-nm, and 5-nm processes to the latest 4-nm and second-generation 2-nm nodes. The interface IP offerings cover UCIe, PCIe 7.0, 112G/224G, MIPI, LPDDR6, DDR5 MRDIMM Gen2, and USB4. Likewise, its foundation IPs include embedded memories, logic libraries, GPIOs, security IP, and Silicon Lifecycle Management (SLM).

\n
1. AI-powered tests
\n

Samsung Foundry and Synopsys are also applying silicon-proven methodologies to design-for-test (DFT) and manufacturing test capabilities to reduce test cost and improve test quality for designs on advanced process nodes. Furthermore, physically aware tests and failure diagnosis at the die and multi-die level improve test quality and failure analysis turnaround time with results validated on silicon at Samsung Foundry.

For instance, Samsung Foundry teams employed Synopsys TestMAX along with AI-assisted automatic test pattern generation (ATPG) technologies to reduce test patterns and test cycles by up to 20%. Samsung Foundry customers leveraging these AI-powered, silicon-based design and manufacturing test capabilities acknowledge test efficiency improvements of up to 20%.

Related Content

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• AI features in EDA tools: Facts and fiction
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• EDA’s big three compare AI notes with TSMC
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• What is the EDA problem worth solving with AI?
\n
• How generative AI puts the magic back in hardware design
\n
• 4 basic steps in implementing an AI-driven design workflow
\n

The post 5 takeaways from Samsung Foundry’s design tie-up with Synopsys appeared first on EDN.

A welcome career transition (and employer-responsibility expansion) begs for a hardware-plus-software evolution. Hold his beer; this engineer’s got this.

As some of you may have already noticed (assuming you even care about such things), my relationship with EDN recently (and happily) re-deepened. After being a full-time as a (senior, eventually) technical editor from 1997 to 2011, I returned beginning a year later, this time as a content contributor. And now I’ve added associate editor to my EDN repertoire.

“Wait,” you might be asking, “isn’t Aalyia Shaukat the associate editor at EDN?” You’re part-right; for nearly four years, she was. And for a couple of recent months, she (somehow) worked a double shift of jobs. But she’s now the full-time editor-in-chief at Power Electronics News, where she’s already rockin’ the house with her talent abundance. And I’m grateful to follow in her EDN associate editor footsteps, along with continuing my own frequent content-contribution cadence.

What’s this all got to do with “de-commingling (or if you prefer simpler vocabulary, “separating”) LAN equipment”? An excellent question. Now that I’m more intimately interacting with the EDN website and other publication (and publisher, and corporate owner) resources and services, I needed to set up a standalone computer so that nothing attacking my home office LAN could make its way to the corporate network and other facilities, too. That said, I remained heavily broadband-reliant. And I wasn’t up for setting up a completely separate Comcast service connection just for a single (albeit also a singularly important) computer. What to do?

Just call me “guest”

That last part was actually the easiest part to solve, it turns out. My home LAN, as mentioned before, is based on a multi-node mesh implemented using multiple Google Nest Wifi routers, with the primary one connected to the cable modem in the furnace room.

One nifty nuance of the Google Nest Wifi system (shared by not only other Google LAN equipment generations and gear from other suppliers, mind you) is that you can set up a distinct “guest” network that by default (which I’ve left unchanged in my case) is packet-isolated from the main LAN beyond their shared WAN connection.

The computer I’m dedicating to my EDN associate editor work is one you’ve seen before; a Microsoft Surface Pro 7+ (SP7+):

along with my longstanding tech-gear companion, a Kensington Dock:

mated as so:

LAN-migrating the SP7+ was easy-peasy. I disconnected the wired Ethernet cable from the back of the Kensington Dock, switched the computer from my main “RockyMountainBri” wireless network to “RockyMountainBri-guest”, and…that was it. And since my Brother multifunction laser printer was right next to the computer, I didn’t even need to bother migrating the wireless network that the MFC was connected to, foregoing printing support for the rest of my LAN in the process. I just ran a USB cable from the Kensington Dock to it, and…I was done. Perhaps obviously, by the way, any real guests are no longer able to use my “guest” wireless network.

Split personality

How do I handle the fact that, still acting as a contributing editor along with my other contributor colleagues, I’m now in effect submitting content to myself for subsequent publication, now wearing my associate editor hat? My contributing editor workflow is unchanged, actually. The only thing that’s different is the email address I now send my stuff to.

It used to be that I’d submit content from my personal email account to Aalyia’s corporate email address. Now, instead, it’s my corporate email address that the goods go to. I’m still using one of my other systems for initial writing—typically but not always a Mac. But, to maintain “firewall” purity between my newly transformed associate editor work system and the rest, I exclusively receive corporate email (and don’t send or receive personal email) on the SP7+.

Going loc(al, not o)

And what about backing up and archiving all this content I’m now receiving? Regular readers may remember that I’ve long been a fan, along with a frequent implementer and upgrader, of network-attached storage (NAS) for such (and other) purposes. That said, unless I wanted to dedicate a NAS solely to my “guest” network and connect it exclusively over slow Wi-Fi, I was going to need to transition to some other solution.

Therein lies the admittedly and intentionally somewhat obscure title of this piece. Instead of network-attached storage, I wanted something locally tethered. It had to be at least dual drive configuration, with RAID 1 support so I didn’t lose everything if a hard drive died. And ideally it’d run hardware RAID to avoid bogging down the computer. Yes, I know, if the RAID controller fails, you’re dead in the water, too, which is why I also wanted something that was reasonably popular. That way, I could, if necessary, find a replacement to slot the HDDs into without too much trouble.

I figured I’d start my search using the term “DAS”, for direct-attached storage. Interface technologies I’d used in the past—Firewire, Thunderbolt, and eSATA among them—weren’t relevant to this particular hardware configuration, so I settled on USB 3.x, as fast a flavor as possible, over USB-C. My (perhaps imperfect) search yielded exactly one result, QNAP’s TR-002, which ironically is primarily intended to capacity-expand the company’s NASs but can also find use as a standalone storage peripheral.

Tomato, tomahto

At this point, I reset my lingo-options list, expanding beyond “DAS” to also include “enclosure”. That change helped a lot from a results-options list length standpoint. What I’ve ended up with is the Mercury Elite Pro Dual from a company I’ve mentioned multiple times before, Other World Computing (aka, OWC) and bought open-box (with 1-year warranty) for $167.50.

It’s hardware RAID-based, supporting four different operating modes (albeit only one at a time):

\n
• RAID 0 “Drive Striping”
\n
• RAID 1 “Drive Mirroring” (the mode I’m using)
\n
• Span, and
\n
• Independent Drives
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Its interface to the computer is 10 GBps USB 3.2; perhaps obviously, I’m direct-connecting it to the SP7+ versus going through the Kensington Dock intermediary. It also embeds a three-port hub, a particularly attractive proposition given the SP7+’s dearth of integrated connections. And here’s a rarity (as I’ve written about before); the hub’s USB-C and dual USB-A ports are all 10 Gbps peak bandwidth-capable, too.

Why, you might be asking, did I go with HDDs instead of SSDs? I’ll turn around and ask you a question in response to yours: have you priced SSDs lately? That said, HDD price tags are also skyrocketing lately, although they still hold a tangible edge over solid-state alternatives especially at higher capacities. And in my case, I thankfully was able to repurpose a couple of spare 3TB HDDs I’d already bought in the “before times” and still had sitting around unused (I’ll have more to say here in an already-planned upcoming follow-up post).

Software completes the magic trick

The last, but not the least, question: how to integrate it with my computer for mirroring and broader backup purposes? I planned on consistently using the SP7+’s upgraded-by-me 1 TByte SSD as primary storage of in-process and completed associated editor work, so one-way mirroring (versus two-way syncing) that portion of the SSD to external storage would be fine.

But I wanted that mirroring to be file-by-file, not lumped together into some unified-file or otherwise nonstandard format (Apple’s Time Machine, for example) that would make it difficult to resurrect the contents if primary storage in the computer failed, say, or if I needed to physically pass the external storage device to someone else. And, of course, I’m also looking for cheaper solutions, so open source or another free source would be best.

I found my solution in a two-part open-source program suite, developed and maintained by the FreeFileSync project and supporting Linux, MacOS and Windows platforms. FreeFileSync itself does the sync-and-mirror heavy lifting for both files and the folders containing them. And the closely related RealTimeSync monitors directories for content changes, which then kick off FreeFileSync (or any other operation more broadly).

This discussion thread was very helpful when I was setting up RealTimeSync and FreeFileSync on my system. And ever since then, it’s run like a charm; the only time it pauses is when it detects an abnormally large number of changes (multiple directories-and-files moved at once) and wants my OK before it proceeds.

Oh, and by the way…since I’ve got plenty of empty capacity available, at least at this early stage in my associate editor career, I’m also using the OWC Mercury Elite Pro Dual more broadly as a successor to the NAS for my ongoing computer-wide backup purposes using Windows’ built-in File History and (deprecated but still functional) Backup and Restore facilities that I’ve mentioned before. With that, I’ll wrap up for today. I hope what I’ve shared will be of help to at least some of you in similar configuration situations either now or in the future. As always, please share your thoughts on what’s worked (or not) for you in the comments!

—Brian Dipert is the associate editor, as well as a contributing editor, at EDN.

Related Content

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• The whole-house LAN: Achilles-heel alternatives, tradeoffs, and plans
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• The Microsoft Surface Pro 5 succession: Selections, motivations, and initial impressions
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• Beefing up backup
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• USB 3: How did it end up being so messy?
\n

The post De-commingling (?) LAN equipment: It’s all in what you call it appeared first on EDN.

Artificial intelligence (AI) silicon is increasingly defined not only by compute capability, but by how data moves through the system. Modern AI SoCs, edge AI processors, automotive compute platforms, and AI accelerators depend on large volumes of data moving among compute engines, memory systems, sensor interfaces, accelerators, chiplet interfaces, firmware controllers, and I/O.

This is why network-on-chip (NoC) architectures have become essential. An NoC provides the internal communication fabric that helps organize routing, arbitration, bandwidth allocation, quality of service, congestion management, and latency behavior inside complex AI silicon.

But it’s important to make a clear distinction.

An NoC is part of the chip execution architecture. It’s not the same as the external signaling interfaces that bring data into or out of the chip.

External signals may arrive through MIPI, SerDes, PCIe, CXL, UCIe, LPDDR, HBM, Ethernet, CAN, or other physical and protocol interfaces. Those interfaces use PHYs, controllers, and protocol layers to move signals into a form the SoC can process internally. Once inside the chip, the NoC routes transactions among internal blocks such as CPUs, NPUs, GPUs, DSPs, memory controllers, sensor-processing blocks, safety islands, and I/O controllers.

In other words, external interfaces move signals into and out of the silicon. The NoC organizes internal data movement inside the silicon. This distinction matters because data movement is not the same as evidence governance.

NoC is not the governance layer

An NoC can move data efficiently, but it does not determine whether a later system symptom was caused by NoC behavior, timing weakness, placement and routing (P&R), power delivery, package behavior, firmware scheduling, workload bursts, or thermal conditions.

For example, a system may observe:

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• Accelerator stalls
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• Latency spikes
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• Traffic congestion
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• Power bursts
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• Voltage droop
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• Timing-margin loss
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• Thermal hotspots
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• Memory-access delays
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• Chiplet-interface errors
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• Workload-dependent failures
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These symptoms may involve NoC activity, but NoC activity alone does not prove NoC causality.

A thermal hotspot may correlate with NoC traffic, but the root cause could also be local transistor density, P&R, clocking behavior, package thermal resistance, power-delivery weakness, firmware scheduling, workload concentration, sensor placement, board conditions, or cooling limitations.

A latency spike may appear in an NoC counter, but the underlying contributor could be memory-controller contention, cache behavior, firmware policy, workload burstiness, arbitration settings, clock-domain crossing, timing margin, or external I/O behavior.

This is the central point: NoC may be one possible contributor to observed AI silicon behavior, but it should not be assumed to be the source of the problem without admissible evidence.

Where SEGA-AI fits

SEGA-AI does not replace NoC architecture, RTL design, physical implementation, timing closure, P&R, verification, or post-silicon debug. Its role is different.

SEGA-AI defines how NoC-related observability, telemetry, counters, workload traces, firmware logs, power data, thermal data, package evidence, and system behavior are qualified before any root-cause conclusion or lifecycle-governance decision is made.

The contribution is not SEGA-AI sees a problem and knows the cause. The contribution is SEGA-AI governs the evidence path required before the system is allowed to assign cause, trigger corrective action, refine assumptions, or update lifecycle policy.

This distinction is essential for complex AI silicon because many physical, architectural, and operational mechanisms can produce similar symptoms.

\n
• A detected hotspot is a symptom
\n
• A detected latency spike is a symptom
\n
• A voltage droop event is a symptom
\n
• An accelerator stall is a symptom
\n

SEGA-AI asks whether the evidence behind that symptom is mature enough, synchronized enough, causally valid enough, and admissible enough to support a decision.

From symptom to evidence through CEMH

Consider a realized AI SoC where telemetry reports a localized hotspot during a high-throughput workload. At level 1, with raw data, the system has only a thermal sensor observation: a localized temperature rise was detected. This observation is useful, but it’s not yet decision-ready evidence.

At level 2, with interoperable data, the temperature reading can move into a diagnostic environment, firmware log, validation database, or fleet-monitoring system. But movement does not create authority. The hotspot may be visible and accessible, but its cause is still unknown.

At level 3, with normalized evidence, the observation is linked to the context required for interpretation:

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• Workload type
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• Timestamp and runtime epoch
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• Firmware policy state
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• NoC traffic counters
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• Accelerator utilization
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• Memory-controller activity
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• Voltage droop measurements
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• Clock and power state
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• Floorplan region
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• Thermal sensor location
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• Package thermal path
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• Board and cooling condition
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• Package lot and assembly history
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• Validation correlation status
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Only at this stage can the event begin to be compared across domains.

At level 4, with admissible evidence, the evidence must pass the Trusted Convergence Governance (TCG) gate. The system must confirm provenance, synchronization, realization-state validity, causal relevance, measurement confidence, and chain-of-custody integrity before the hotspot data can influence a convergence decision.

At level 5, with convergence-authoritative evidence, the system has enough qualified evidence to support bounded action or lifecycle refinement. That action may be a firmware policy adjustment, workload throttling, degraded mode, validation update, package constraint refinement, or future design-rule feedback.

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• The hotspot may be related to NoC congestion.
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• It may be related to accelerator placement.
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• It may be related to P&R density.
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• It may be related to package thermal resistance.
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• It may be related to voltage droop and increased local switching.
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• It may be related to firmware scheduling or workload concentration.
\n
• The purpose of SEGA-AI is to prevent premature conclusions.
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• A thermal sensor does not prove NoC causality.
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• An NoC counter does not prove package causality.
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• A voltage droop event does not prove timing causality.
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SEGA-AI requires that the evidence mature through Convergence Evidence Maturity Hierarchy (CEMH) and pass TCG admissibility before any root-cause conclusion or lifecycle-governance action receives authority.

The role of CEMH, TCG, and GFL

Within the SEGA-AI framework, three layers are especially relevant.

Convergence Evidence Maturity Hierarchy (CEMH) defines how information matures from raw observation into convergence-authoritative evidence. A thermal sensor value, NoC counter, voltage monitor, or firmware trace begin as raw or interoperable data. It does not become decision-ready evidence until it has been contextualized, synchronized, qualified, and connected to the correct realization state.

Trusted Convergence Governance (TCG) acts as the trust gate. It asks whether evidence preserves provenance, synchronization validity, realization-state consistency, causal relevance, and bounded authority before it influences a decision.

Governance for Lifecycle (GFL) asks whether the realized system can remain converged throughout operational life. It’s concerned not only with whether the chip worked at initial signoff, but whether chip, package, board, firmware, workload, and field behavior remain aligned over time.

Together, these layers prevent a common failure mode: mistaking observable behavior for proven causality.

Diagnostic evidence plan

This also changes how AI silicon should be planned before implementation. Here, SEGA-AI can contribute by helping define the diagnostic evidence plan.

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• Which NoC counters are needed?
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• Which congestion metrics should be exposed?
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• Which workload tags must be preserved?
\n
• Which timestamps and synchronization epochs are required?
\n
• Which voltage, thermal, clock, and power monitors are needed?
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• Which firmware traces must be connected to physical state?
\n
• Which package and board conditions must be tracked?
\n
• Which evidence fields are required to distinguish NoC behavior from timing, P&R, PDN, thermal, firmware, or package causes?
\n

This does not mean SEGA-AI designs the NoC. It means SEGA-AI asks what evidence must exist later so that realized-system behavior can be interpreted correctly. That is the bridge between design intent and lifecycle governance.

Why data movement alone isn’t enough

NoC architectures are essential because AI silicon needs scalable internal communication. But moving data correctly inside the chip does not automatically explain system behavior after realization. An NoC may deliver a packet correctly while the system still experiences thermal drift. Likewise, a controller may report a valid transaction while the package creates a local thermal bottleneck.

Next, a firmware trace may show a workload transition while the underlying voltage margin is collapsing. Or a sensor may report a hotspot while the causal chain remains ambiguous. This is why observability must become governed evidence before it can support lifecycle decisions.

The key question is not only: Did the data move? The real question is: Is the observed behavior mature enough as evidence to support diagnosis, intervention, or lifecycle refinement? This distinction becomes especially important in edge AI and ADAS systems.

In an ADAS platform, camera, radar, lidar, IMU, wheel-speed, steering, and vehicle-state data enter through physical interfaces and controllers. Inside the AI SoC, the NoC routes internal traffic among image processors, AI accelerators, CPUs, memory controllers, safety islands, and I/O blocks.

The AI accelerator may detect pedestrians, lanes, vehicles, or collision risk. But if a late response, thermal event, inference delay, or braking-decision uncertainty is observed, the system should not automatically blame the NoC, the AI model, the memory controller, or the package. It must first build an admissible evidence chain.

This matters because ADAS is not only a performance application; it’s a safety-critical realization environment.

A latency spike or inference delay may affect warning time, braking distance, steering support, or driver handoff. In that context, clean data movement is not enough. The system must know whether the evidence supporting the decision is synchronized, causally valid, realization-consistent, and authoritative enough for action.

For low-risk edge AI applications, a wrong output may create inconvenience or cost. For ADAS, a wrong output may affect human safety. That changes the required evidence maturity.

A safety-critical output should not receive full action authority simply because data moved correctly through the chip. It should be supported by level 5 convergence-authoritative evidence or by a pre-qualified safety envelope that has already been validated through admissible evidence.

In SEGA-AI terms, the chain is:

Input evidence → local inference → confidence and uncertainty → synchronization check → causality check → TCG admissibility gate → bounded output authority

This is why edge AI and ADAS show the difference between data movement and evidence governance. The NoC may help move sensor data, model data, and inference results; but SEGA-AI governs whether the observed behavior is trustworthy enough to support diagnosis, intervention, degraded mode, fleet learning, or safety-critical action.

From execution fabric to governance framework

The NoC is an execution fabric; SEGA-AI is a governance framework. The NoC helps the chip move data; SEGA-AI helps the system determine whether observed behavior can be trusted as evidence. And these are complementary roles.

As AI silicon becomes more complex, the industry will need both: data-movement architecture to move information efficiently inside the chip, and evidence-governance architecture to determine whether observed behavior can support root-cause analysis, corrective action, lifecycle refinement, or fleet learning.

This becomes increasingly important as systems move from design into package, board, validation, deployment, runtime adaptation, and field operation. And this discussion is not only theoretical. If realized AI systems require governed evidence, then implementation must account for evidence maturity from the beginning.

That means the design and validation plan must define not only what data moves, but what data must later be observable, timestamped, correlated, and qualified. For example, if post-silicon validation or field operation needs to distinguish NoC congestion from P&R density, package thermal resistance, memory-controller contention, or firmware scheduling, then the required evidence must be designed into the system earlier.

This includes counters, monitors, timestamping, workload tags, synchronization epochs, sensor placement, firmware traceability, package-state linkage, and validation correlation methods. In SEGA-AI terms, the theoretical model becomes practical only when it’s translated into implementation artifacts: evidence fields, admissibility checks, traceability rules, synchronization requirements, gate criteria, diagnostic workflows, and lifecycle feedback paths.

This is why the next step after governance theory is implementation specification. A system cannot govern evidence it never planned to observe.

Silicon governance complementing NoC

AI silicon performance depends heavily on data movement. NoC architectures are essential because they organize internal communication among compute, memory, accelerators, controllers, chiplet interfaces, and I/O. But NoC observability is not the same as causality.

A latency spike, hotspot, voltage droop, or accelerator stall may involve NoC behavior, but it may also be driven by timing, P&R, power delivery, package thermal paths, firmware policy, workload behavior, or system-level conditions.

However, the role of SEGA-AI is not to replace NoC design. The role of SEGA-AI is to govern the evidence required before symptoms become conclusions and before conclusions become decisions.

For AI silicon, the next challenge is therefore not only moving data efficiently. It’s qualifying observed behavior into admissible, causally grounded, convergence-authoritative evidence. In short, interoperability moves data; admissibility qualifies evidence; and governed convergence closes decisions.

Dr. Moh Kolbehdari is senior director of IC/packaging at Socionext US.

Related Content

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• Speeding AI SoC development with NoC-enabled tiling
\n
• How data movement defines performance for AI silicon
\n
• Why verification matters in network-on-chip (NoC) design
\n
• Taming the beast: Memory efficiency in an AI/crypto world
\n
• Automotive silicon in the era of AI, functional safety, and cybersecurity
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The post From AI silicon observability to governed evidence appeared first on EDN.

To how many significant digits does Pi (and its peers) remain relevant?

Some while ago, I downloaded a file of Pi calculated to one-hundred-thousand digits. A bit later, I downloaded a different file of Pi calculated to one million digits. I thought those were impressive, but just recently I read of a computer calculation of the value of Pi made to an insanely larger number of digits. I can’t find that article again but from memory, the calculation was run to two trillion digits.

The goal wasn’t to seek the value of Pi itself to that level of precision. It was a test of the computer, to see if it could run long enough to do that calculation without some kind of malfunction coming up. It was a test of the computer’s ability to run through very long computational processes without error. In that article, reference was made to NASA depending on the value of Pi to merely fifteen digits. This seeming disparity merited a look-see.

I looked up the definition of a parsec and found its numerical value in light years to a lot of significant digits, fourteen to be truthful. I then set up the geometry on which that number was based (Figure 1).

\nFigure 1 This graphic provides a visual definition of a parsec.

As the earth moves around the sun, a far-off object is observed for its apparent position in the sky. Because of parallax, there is an angular shift of that apparent position at earth’s two orbital extremes. Knowing the radius of earth’s solar orbit, half of that angular shift is taken as an angle which I call theta for which the distance to that object from the center of the sun may be calculated. The implicit assumptions are that the earth’s orbit is circular and that the sun is at the center of that circle which we know is not exactly so, but we do that anyway.

When the value of theta is one arc second or one degree divided by 3600, the distance D is defined as one parsec. Table 1 derives (with some admitted finagling which I will describe shortly) the distance of one parsec in terms of light years.

\nTable 1 The calculation detailed here derives parsecs in terms of light years.

The finagling part here is twofold. First, I used a value of Pi to fifteen significant digits, thus mimicking NASA. Secondly, I set the radius of earth’s solar orbit to precisely that value which yields the published value of one parsec that I found online.

That orbital radius looks just about right, but just how precise these numbers really are eludes me. For example, do we really know the earth’s orbital radius to that many significant digits? Earth’s orbit is not really circular. It is slightly elliptic. What precise refinements were made to establish the published value of D to so many significant digits? I have no idea.

Colloquially however, the value of one parsec is usually taken as 3.26 light years, which is good enough for general reading and good enough to satisfy my own curiosity. I’m perfectly happy with that fifteen digit value of Pi.

John Dunn is an electronics consultant and a graduate of The Polytechnic Institute of Brooklyn (BSEE) and of New York University (MSEE).

Related Content

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• \n
  \n
  • Successive approximation
  \n
  • Delta-sigma demystified: Basics behind high-precision conversion
  \n
  \n
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The post How Precise Must We Be? appeared first on EDN.

Makers and educators, we want to hear from you! Expert or novice, your perspective as an Arduino user matters – and right now, sharing it could win you something pretty special.

We’ve put together a short user survey to better understand how the community uses what we have to offer, what’s working well, and where we can do better. It takes about 10 minutes to complete, it’s open to everyone, and your answers directly inform how we develop our products, tools, and resources going forward.

The Arduino Mystery Box Giveaway is here!

To thank you for your time, we’re running a mystery box giveaway alongside the survey – from May 18 to September 1, 2026. 10 respondents will be randomly selected to receive one of 10 mystery boxes containing Arduino hardware and swag.

It’s quick, it’s open to all levels, and the more voices we hear from, the better we can serve the community. Share the link with your maker friends – the more the merrier!

Take the survey now!

Giveaway Full Official Rules are available here. No purchase necessary. Void where prohibited.

The Arduino logo is a trademark or registered trademark of Arduino S.r.l.

The post Tell us what you think – and enter for a chance to win one of 10 mystery boxes of Arduino gear! appeared first on Arduino Blog.

Factory lighting can be brutal. A label looks perfect from one angle and unreadable from another. A reflective pouch catches glare. A conveyor casts shadows. A package edge disappears under mixed LED lighting.

Traditional industrial vision systems solve these very real problems, and that’s why they became expensive. However, many inspection tasks don’t require a closed, high-cost smart camera. They just need a reliable prototype path: collect images, train a model, deploy locally, trigger an action, and improve. 

On UNO Q, the Linux side of the board can run the camera pipeline, OpenCV preprocessing, an Edge Impulse object-detection or classification model, and a local web dashboard. Meanwhile, the MCU side can handle encoder pulses, trigger timing, stack-light outputs, and reject-actuator logic. You can already browse Arduino® Project Hub for a variety of practical vision examples that combine UNO Q with Edge Impulse models. We highly recommend the one for a robot arm that recognizes people and offers gadgets through intuitive interactions, and the one for OCR (optical character recognition) with a two-stage text detection and recognition pipeline running locally with Arduino® App Lab, plus image classification examples using a USB webcam and Edge Impulse Linux runner. 

Real-world industrial applications are within reach

Imagine the following setup: a small conveyor rig with an overhead camera pointed at the product as it passes through an end-of-line station. A quantized model running locally detects pass/fail – checking for the right label, a properly seated connector, a sealed cap, or a surface defect – with inference times under 50 ms. The microprocessor running Debian hosts the dashboard made with Python and logs every result; the MCU triggers the operator’s alert system without waiting for a round trip to the cloud. No frames leave the board, no proprietary software license is required, and the same fixture can be reconfigured for a different product without rearchitecting the system from scratch. Sound like a dream? Nope, it’s real: just check up the setup IDT Solution validated in their open-architecture AOI proof of concept for automotive end-of-line inspection.

Want to learn even more? You can also use the UNO Q to run a defect classification model, such as a missing label, wrong color, missing cap, or damaged package. Train the first model in Edge Impulse. Deploy through Arduino App Lab. Run the application as a Debian service or Arduino App Lab app. Use the MCU for deterministic reject timing.

UNO Q turns vision into action

UNO Q has the potential to become the leading SBC for its price and power category, because of the real value it offers. 

1. Industrial vision without industrial pricing. Build credible inspection prototypes without committing to proprietary smart-camera systems.

2. Better inspection under real lighting. Use multiple camera views, local preprocessing, and optimized vision models to improve robustness under glare, shadow, and reflective surfaces.

3. AI plus deterministic action. Run inference on Linux; trigger conveyors, lights, and reject mechanisms through the MCU.

\n
1. \n

The real promise of UNO Q is not just that it can run a vision model. It is that it can turn vision into action.

A traditional camera can capture an image. A cloud model can classify it later. But an industrial inspection system needs more than recognition. It needs timing, reliability, local decision-making, and a way to respond immediately when something is wrong.

Edge AI for machine vision: from concept to working prototype

By combining Debian Linux, Edge Impulse, local AI inference, and deterministic MCU control, developers can build inspection systems that see the product, understand the defect, log the result, and trigger a physical response – all at the edge.

This means a faster path from concept to working prototype. For developers, it means open tools, flexible deployment, and real-world control. For manufacturers, it means machine vision can move beyond expensive, closed systems and become something more accessible, adaptable, and scalable.

That is how industrial vision becomes practical, repeatable, and affordable – and it is exactly the kind of edge AI workflow UNO Q was built to unlock.

Ready to build your first AI camera inspection system? Explore UNO Q and start prototyping real-world inspection systems today.

Arduino, UNO and the Arduino logo are trademarks or registered trademarks of Arduino S.r.l.

The post Industrial-grade vision inspection, made accessible by the Arduino® UNO™ Q board appeared first on Arduino Blog.

Carlo Prisco and Fabio Marchese from PriscoZen had a clear goal from the start: not a technical demo, but a real, working platform that could bring machine control, software logic, and visual quality inspection together in a single compact system. Something they could demonstrate live, evolve over time, and show that industrial automation doesn’t have to mean a traditional PLC in every scenario. The result is ZenCell – and its story is a good example of how innovation, more often than not, emerges through iterations and a progression of improvements, rather than a single eureka moment. 

Where it started: Arduino^®Mega board + Raspberry Pi

The first version of ZenCell was built around a practical architecture: a Mega 2560 Rev3 handling input and output signals, a Raspberry Pi as the central brain coordinating machine logic and the operating cycle, and a Keyence camera for visual inspection. Logic was distributed across two boards, but it worked – well enough that cycle times were in the range of 1.8 to 2.2 seconds.

The team tested the system first at home, validating the overall logic and machine behavior in early-stage conditions. Then they took it further: ZenCell was integrated alongside a three-axis industrial robot next to a molding press, where it held up just as well. The architecture proved its validity not just as a concept, but in conditions close to real production – and it was open, integrated, and flexible.

The shift: from two boards to one

Once the Arduino^® UNO Q board was released, PriscoZen saw an opportunity to greatly improve their solution. Thanks to its dual-brain architecture, UNO Q combines an MPU running Linux with an MCU handling real-time control – exactly the split that Raspberry Pi and Mega were covering separately, now unified on a single compact platform. This allowed Prisco and Marchese to rethink how the system was organized.

In ZenCell V1 – which will début at Maker Faire Caserta 2026 (May 30-31, 2026) – UNO Q is the true engine of the system: hosting the dedicated ZenCell software, managing the cycle logic, coordinating all connected devices, and handling identification peripherals like QR code and barcode readers directly. The result is a cleaner, more centralized architecture, with cycle times brought down to a range of 0.56 to 0.68 seconds.

ZenCore: the software layer that ties it all together

Alongside the hardware evolution, Prisco and Marchese developed ZenCore – the software platform running on ZenCell V1. Accessible through a local web interface with no complex client software required, ZenCore centralizes operational supervision, workflow and recipe management, I/O signal handling, diagnostics, and vision system integration in a single environment.

The long-term vision is a node-based, visual approach to automation logic – connecting devices, commands, states, and sequences in a way that is reusable and adaptable across future applications.

The next step for ZenCell

The roadmap for ZenCell V2 takes the platform further still, with plans to replace the Keyence camera with an open industrial camera and build a proprietary pipeline for image acquisition, dataset development, and defect-recognition model training – all running locally on the next-generation platform.

From a distributed two-board prototype to a centralized system built around a single board’s dual architecture: ZenCell is a clear example of what happens when engineers with the right skills and a concrete vision find the right tools to bring it to life.

Arduino, Mega, and UNO are trademarks of registered trademarks of Arduino S.r.l.

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Lumissil’s IS32FL3776 matrix LED driver brings expressive intelligent signal displays (ISDs) to software-defined exterior automotive lighting. With 36 constant-current channels providing 60 mA each, it drives dynamic LED light matrices up to 36×6 with as many as 216 individually addressable LEDs.

Automotive ISD systems use matrix LED patterns to communicate vehicle intent, safety status, driver-assistance cues, and brand identity. The IS32FL3776 enables compact LED designs used in RGB mini LED displays, full-width front light strips, grille lamps, automated driving system marker lamps, and other expressive vehicle lighting functions.

The driver features high-resolution, high-frequency dithered PWM for fine brightness adjustment and smooth animations without flicker or camera banding. For improved system efficiency and thermal performance, the IS32FL3776 uses DCFB adaptive control to optimize the LED supply rail while maintaining sufficient headroom for proper current regulation. A software-configurable architecture supports either internal operation or external PMOS drive for power sequencing in larger matrix configurations.

The IS32FL3776 is available for sampling and volume production, with evaluation hardware and reference designs provided to facilitate system development.

IS32FL3776 product page 

Lumissil Microsystems 

The post LED driver animates exterior vehicle lighting appeared first on EDN.

Three digital multiphase controllers from AOS enable Intel IMVP9.3 Vcore power delivery in high-performance mobile systems. When paired with the company’s DrMOS and Smart Power Stage devices, the AOZ71049QI, AOZ71149QI, and AOZ71146QI form a complete power solution for Intel Panther Lake and Wildcat Lake mobile processor architectures.

The buck controllers use AOS’s advanced transient modulation (A²TM), a hybrid approach that combines digital tuning with analog efficiency. By integrating variable-frequency hysteretic peak current-mode control with advanced phase current sensing, they deliver fast transient response and balanced current sharing across both transient and DC loads. They also maintain low quiescent power across all Intel IMVP9.3 power states, helping maximize battery life in laptops and notebooks. Key features are summarized below:

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• Flexible configurations: Up to 4+2+1+2 phase outputs for Core (IA), Graphics (GT), Auxiliary (SA), and LPCORE domains
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• Low quiescent current: 5.9 mA at PS0 in 3+2+1+1 configurations
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• Power management: Autonomous phase shedding and auto-DCM to reduce power loss
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• Compatibility: Supports industry-standard DrMOS and driver + MOSFET power stages from multiple vendors
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• Acoustic noise suppression: Integrated features reduce audible noise under dynamic load conditions
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The AOZ71049QI, AOZ71149QI and AOZ71146QI are available in production volume, with a lead time of 12 to 16 weeks. Prices start at $2.66 in 1000-piece quantities.

Alpha & Omega Semiconductor 

The post Multiphase controllers optimize mobile Vcore power appeared first on EDN.

Manufacturing is at a pivotal moment. Global supply-chain volatility, increasing energy costs, workforce shortages, and growing expectations for quality and customization are forcing factories to rethink how they operate. Traditional automation, optimized for predictability and repetition, struggles to cope with today’s variability and speed of change.

The smart factory represents a decisive shift: production environments that can sense, interpret, and adapt in real time. Central to this shift are three tightly connected technology domains: machine vision, intelligent sensing, and edge AI. Together, they enable factories not just to collect data, but to turn it into insight and action where it matters most.

Figure 1 The notion of smart factory marks a decisive shift in modern manufacturing. Source: Renesas

The limits of conventional automation

Conventional automation systems excel at executing predefined logic. However, they are inherently reactive. When processes drift, materials vary, or equipment degrades, intervention is often manual, time‑consuming, and costly.

Key pressures accelerating the move toward smarter automation include:

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• Greater product diversity driven by mass customization
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• Higher quality expectations that allow little tolerance for defects
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• Skilled labor shortages across engineering and maintenance roles
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• Soaring downtime costs, particularly in highly automated lines
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Addressing these challenges requires automation systems that are more perceptive and context-aware systems capable of learning from data rather than simply enforcing rules.

Below is a quick recap of smart factory’s three key design building blocks: machine vision, intelligent sensing, and edge AI.

Machine vision: From inspection to interpretation

Machine vision is one of the most visible pillars of the smart factory. Once limited to basic presence checks or rigid defect criteria, today’s vision systems can interpret complex scenes and adapt to variation.

Seeing beyond pass or fail

Traditional, rule-based vision systems perform well under tightly controlled conditions but tend to break down when lighting, materials, or product designs change. Modern vision approaches increasingly incorporate learning-based techniques that recognize patterns instead of relying on fixed thresholds.

Figure 2 Modern vision systems recognize patterns instead of relying on fixed thresholds. Source: Renesas

This evolution enables machines to distinguish acceptable variation from true defects, adapt to new product versions with minimal retraining, and provide richer information for downstream decision-making.

Broader roles on the factory floor

Machine vision now plays a central role in:

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• In-line quality assurance, detecting cosmetic, structural, and assembly issues
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• Robot guidance, enabling flexible pick-and-place and assembly operations
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• Traceability, supporting serialization and regulatory compliance
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• Safety monitoring, detecting unsafe conditions or human proximity
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As processing moves closer to where images are captured, vision becomes more responsive and resilient, key traits for real-time factory environments.

Figure 3 Machine vision technology is quickly acquiring the key traits required in real-time factory environments. Source: Renesas

Intelligent sensing: Adding awareness to automation

While machine vision provides visual insight, intelligent sensing fills in the rest of the picture. Parameters such as vibration, temperature, current, torque, pressure, and acoustics reveal what is happening inside machines and processes.

From measurement to meaning

Intelligent sensors are no longer passive components. Increasingly, they embed local processing and diagnostics, enabling them to filter and contextualize raw signals, detect subtle behavioral changes, and reduce unnecessary data transmission.

Instead of reporting isolated values, sensors can now indicate conditions such as early wear, imbalance, or inefficiency.

The power of sensor fusion

True process understanding emerges when multiple sensor types are combined. By correlating visual data with physical and environmental measurements, factories gain a far more reliable and nuanced view of operations.

For example, a visual anomaly combined with abnormal vibration data may indicate tool degradation rather than a material flaw. This holistic view reduces false alarms and accelerates corrective action.

Edge AI: Intelligence at the point of action

Edge AI ties machine vision and intelligent sensing together, enabling factories to interpret complex data locally, without relying on constant cloud connectivity.

Why the edge matters

Manufacturing environments demand capabilities that centralized systems struggle to provide:

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• Low-latency decision-making for time-critical control
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• Operational autonomy in environments with limited connectivity
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• Data sovereignty and IP protection
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• Scalable deployment across many machines and lines
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Edge AI meets these needs by bringing inference and decision logic directly to machines.

Figure 4 Edge AI, the third key building block in smart factory designs, ties machine vision and intelligent sensing. Source: Renesas

Practical impact on operations

With edge AI, factories become more intelligent and proactive in their operations. Instead of reacting to problems after they occur, systems can predict potential failures in advance and help avoid costly disruptions. Processes can also be adjusted in real time to account for changes in materials or environmental conditions, ensuring consistent quality and efficiency.

In addition, AI-driven systems can identify unusual patterns and anomalies that were not explicitly programmed, enabling earlier detection of issues. At the same time, more intuitive and responsive human–machine interactions improve safety and usability on the shop floor. Altogether, this represents a clear shift from reactive control toward adaptive, self-optimizing operations.

Convergence: Creating intelligence through integration

The greatest gains emerge when machine vision, intelligent sensing, and edge AI are designed as a unified system rather than isolated capabilities.

Consider a high-mix production line:

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• Machine vision identifies subtle quality deviations
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• Intelligent sensors monitor mechanical and electrical behavior
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• Edge AI correlates these inputs to identify emerging issues
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Instead of scrapping products or stopping the line, the system can adjust in real time, maintaining quality while maximizing throughput. This distributed intelligence also simplifies factory architectures. Decisions are made close to the process, improving responsiveness and system robustness.

Designing for sustainable smart factories

Achieving this level of intelligence is not just a technical challenge, it is a system and ecosystem challenge. Manufacturers need platforms that simplify integration across sensing, processing, connectivity, and security, while supporting long product lifecycles typical of industrial environments.

As adoption accelerates, successful smart factory strategies share several traits:

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• Scalability, allowing intelligence to be added incrementally
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• Interoperability, avoiding vendor lock-in
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• Lifecycle support, including long-term availability and maintenance
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• Energy-efficient design, balancing performance with sustainability
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Smart factories built on these principles are better equipped to adapt, not just to current challenges, but to future uncertainty.

In the final analysis, smart factory is not defined by a single technology, but by how technologies work together. Machine vision gives machines eyes. Intelligent sensing provides awareness. Edge AI delivers understanding.

With the right enablement and ecosystem support, manufacturers can move beyond reactive automation toward systems that continuously learn, adapt, and improve. In doing so, they transform data into decisions, and factories into resilient, future-ready operations.

Suad Jusuf is director of product marketing at Renesas Electronics. His work centers on defining distinctive value, empowering differentiation, and accelerating customer success through integrated MCU/MPU platforms, AI tools, and system‑level enablement and offerings.

Special Section: Smart Factory

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• Rethinking machine vision in industrial automation
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• Smart factory: The rise of PoE in industrial environments
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• Precision lasers boost safety and efficiency in smart factories
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• Tale of 3 sensors operating in smart factory environments
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• From edge AI to physical AI in smart factories: A shift in how machines perceive and act
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• Robots: Why AI alone will not deliver the next leap in automation
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• How emerging robotics standards will shape next-gen automation
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The post How machine vision, intelligent sensing, and edge AI are powering smart factory appeared first on EDN.

Portable power station design apparently isn’t easy. So suggests this engineer’s most recent two case studies, not to mention the long-term history (kudos to Kurt Vonnegut for the inspiration).

My first writeup last month discussed why one battery (or a few) in a larger cluster always seems to drain faster than the others, and how this imbalance would affect the system powered by that multi-battery cluster. The answer depended in part on whether the batteries were connected in a series, parallel or a hybrid combo of the two, to “boost the effective voltage (serial) and/or increase overall system runtime (parallel)”. Here’s how I concluded that piece:

I’m covering today only situations where the installed batteries are either non-rechargeable or are removed for recharging. Multi-battery packs recharged in situ (while installed inside a portable power unit, for example) translate to an even more complicated scenario involving, among other factors, the critical importance (and difficulty) of balancing the various cells within the likely series/parallel cluster.

At that point in time, for readers who wanted to know more about this topic, I referenced a Vitron Energy white paper I’d previously recommended in that same piece for other reasons, which also explored this topic at length. Here’s an example of what I’m talking about in the form of a quote from that same white paper:

If a large battery bank is needed, we do not recommend that you construct the battery bank out of numerous series/parallel 12V lead acid batteries. The maximum is at around 3 (or 4) paralleled strings. The reason for this is that with a large battery bank like this, it becomes tricky to create a balanced battery bank. In a large series/parallel battery bank, an imbalance is created because of wiring variations and slight differences in battery internal resistance.

And later in that section, as further elaboration:

When creating a lead-acid battery bank with a higher voltage, like 24 or 48V you will need to connect multiple 12V batteries in series. But there is one problem with connecting batteries in series, and this is that batteries are not electrically identical. They have slight differences in internal resistance. So, when a series string of batteries is charged, this difference in resistance will cause a variance in terminal voltages on each battery. Their voltages become “unbalanced”. This “unbalance” will increase over time and will lead to one of the batteries being constantly overcharged while the other battery is constantly undercharged. This will result in a premature failure of one of the batteries in the series string.

Again, I commend the entire white paper to your attention, not only because it delves in greater detail into the topics discussed in the two excerpts I selected but also because in doing so, it covers not only lead-acid but also lithium-based and other emerging chemistries such as “flow”.

I wrapped up that prior writeup by saying that “I’ll likely have more to say about these topics in future posts as well.” I didn’t necessarily think at the time that I’d be revisiting rechargeable in situ batteries this quickly…but then again, I also didn’t think that, a short time later, I’d personally experience what I still suspect was the outcome of an unbalanced multi-cell battery bank (along with a couple of other functional hiccups, details of which I’ll also share).

The DOA DELTA 3 Smart Extra Battery

I’ve had my EcoFlow DELTA 3 “stack”, the combo of a DELTA 3 Plus and its companion Smart Extra Battery, for one day shy of a year as I write these words in late April:

Until recently, all’s been well. It had only received a couple of firmware updates, all of which had been drama-free. And although it won’t seemingly power my refrigerator reliably, Xcel Energy’s increasingly frequent (or at least so it seems) power outages have provided plenty of other opportunities for me to tap into its stored-electron stash. The most recent outage (again as I write this …another is sooner-or-later-likely-sooner inevitable) in mid-March thankfully lasted only a bit more than seven hours, not several days, but alas, the “stack” didn’t survive it.

During the outage, I’d dragged upstairs its DELTA 2 base unit-plus-smart extra battery “stack” siblings to run an interior lights and recharge flashlights and various mobile devices:

When the utility company-sourced premises electricity came back up just after midnight, I took the DELTA 2 “stack” back downstairs to the workbench in the furnace room, its normal on-standby location. I’d left the DELTA 3 gear there; the base unit’s front panel display was now illuminated but that of the smart extra battery wasn’t, nor seemingly was the latter more broadly functional any longer. And looking more closely, I noticed an “Error 726” indicator on the base unit display that I’d never seen before:

I hit up Google search for suggestions, which were scant, dubious (I don’t think “turn off the unit and wait a few hours for the cells to rebalance themselves” makes much if any sense, particularly given that the only way to turn the unit off is to unplug it first) and more generally indeterminate save for the revelation that Error 726 indicates that “cell voltage differences are too great”. My next and increasingly common step was to publish a Reddit post. One respondent pointed me toward some Facebook group traffic that I’d already come across. Another noted that he/she had experienced the same issue after a recent firmware update, which I’d also done. And a third offered a “Possible it’s a bad cell” suggestion. Hold that thought.

Base unit BMS reset attempts were ineffective; it was also running the latest-available firmware:

I hooked up a fan to one of the AC outputs to drain the base unit’s batteries, in the hope that a full recharge might resurrect its cognizance of the smart extra battery. No dice; the base unit worked fine standalone but threw an Error 726 with the smart extra battery connected. So, I reached out to EcoFlow technical support, who confirmed that the smart extra battery had gone bad and offered to send me a replacement in exchange for my failed unit.

Two weeks later, the new smart extra battery was in my hands. Connecting it to the base unit initially resulted in the generation of another error code in the latter, the nebulous “Error 014”:

After a brief panic, and acting on a hunch, I checked to see if the base unit needed a firmware update before the two devices could be sympatico. Indeed, that was the case, two update cycles’ worth, in fact:

And, at least as of today, the setup once again seems to be working OK, leaving me with one lingering question: what went wrong in the first place?

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• Was it a hardware failure, such as (but not necessarily) an unrecoverable cell-imbalance issue, in my specific original smart extra battery?
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• Was there a broader fundamental hardware flaw in initial smart extra battery units, suggested by the prompt to do a firmware update (which I hadn’t seen before) when I plugged in the replacement?
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• Did a firmware update to the base unit initiate the failure sequence in the first place, as the comments of one of the respondents to my Reddit post indicates might be the case?
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• Or were the firmware-update timings (both prior to the original-unit failure and after installation of its replacement) purely coincidental?
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Reader theories (and broader thoughts) are as-always welcome in the comments! And now, speaking of botched firmware updates…

A DELTA 2 double-whammy

Regular readers may recall that I’ve had issues after doing firmware updates on EcoFlow gear before. Generally speaking, I’ve therefore subsequently waited for an appropriate period, combing Reddit and relevant Facebook groups for posted evidence of others’ troubles, before taking the plunge myself. However, when I got prompted for an update to the DELTA 2 in late February, I (over)confidently decided to plunge ahead absent any preparatory research:

After all, the previous update I’d done to the DELTA 2 back in late December had gone well. I was so overoptimistic, in fact, that I updated my RIVER 2 at the same time:

The RIVER 2 survived the update just fine. The DELTA 2 on the other hand…

I admittedly didn’t immediately notice the issue, because it only happened occasionally. With the combo “awake”, everything seemed to be fine (well, mostly…keep reading). But at some random point after the units displays turned off (I stuck with the default “5 minute” setting), the power LED on the smart extra battery would extinguish, the base unit’s fan would kick on and perpetually run at low speed, and it would unceasingly (generally) or cyclically (briefly) draw ~20W of power from the AC outlet connected to it:

Punch either unit’s front panel power switch and the displays would wake up, the fan would stop and the trickle charge would cease…until after the displays turned back off again, that is. Lather, rinse, repeat. The trickle-charge behavior particularly worried me, because I didn’t want to end up with an overcharged, overheated and potentially exploded-and-burning battery situation on my hands. So, after several cycles of BMS resets and draining-then-recharging the battery sets, all of which “fixed” the issue only temporarily, I reached out to EcoFlow tech support once again with the proactive suggestion that a firmware downgrade might be in order.

They agreed. I never received (again, keep reading) their first attempt to “push” me a rollback from v1.0.2.176 to firmware v1.0.2.163, but the second attempt was successful:

The DELTA 2 “stack” is once again stable, at least from a charging standpoint. And although it took a while for another invitation to update back to firmware v1.0.2.176 to appear, leaving me wondering if either my “rollback” package had been customized to suppress the subsequent update or EcoFlow had pulled firmware v1.0.2.176 completely:

Turns out I just didn’t wait long enough (and yes, I declined when the update invitation eventually arrived):

Unfortunately, EcoFlow doesn’t publish firmware version histories for its devices, so I couldn’t check for an answer to my question that way. And customer service’s silence in (non-)response to my repeated queries about this particular topic weren’t helpful either (in contrast, I’m compelled to note, to their overall general excellent support).

Connectivity troubles

While I was in communication with EcoFlow, I also brought up an unrelated DELTA 2 issue that I’d been having on-and-off, albeit seemingly more frequently with the passage of time, with the base unit. After some random time period, hours-to-days after I’d established Wi-Fi connectivity, it’d drop Wi-Fi and revert to Bluetooth-only communication with my controlling smartphone:

Other times, even when Wi-Fi was supposedly still operational:

the DELTA 2 base unit, therefore entire “stack”, became “invisible” when I was attempting to reach it from outside my LAN via the EcoFlow “cloud” intermediary:

EcoFlow tech support suggested that the IoT module inside the unit might be gradually failing. I almost didn’t bother pressing the issue further—returning the unit for repair or replacement is something of a hassle, further complicated by the fact that the included flammable batteries mean that I can’t just drop it off at a FedEx Office location but need to arrange for front-door pickup, and then there’s the delay for a replacement unit to arrive—while the loss of Wi-Fi connectivity is annoying, it’s not a functional “death sentence”.

But then EcoFlow confirmed what I’d already suspected, that the IoT module also implements the Bluetooth subsystem, whose functional loss would completely sever further communication with the unit. Couple that with the fact that I’ve been promised a brand-new (not refurbished) replacement, with a zero-cycle fresh battery pack, and it was an offer I couldn’t refuse. I’m awaiting a return-shipping label as I type these words; I’ll report back on the status of the replacement unit via a posted comment on this post once published.

Design is hard

You may have already noticed a commonality to both primary issues noted in this writeup, as well as those in prior EcoFlow problem-themed coverage from me: the smart extra battery. I’m guessing that it’s relatively uncommon for base unit owners to also have this additional-charge (not to mention additional credit card charge) storage peripheral. As such, the prevalence of user problems is also likely to be uncommon. Therefore, I suspect, it’s relatively easy for smart extra battery firmware-related issues in particular to slip through any EcoFlow pre-release testing cracks.

In no way am I making excuses for the various EcoFlow issues I’ve come across; I’m just striving to be pragmatic about root causes. As I noted at the beginning of this writeup, battery pack design is fundamentally challenging. Make a device increasingly “smart” and the level of difficulty further ramps up. Is EcoFlow unique in this regard? I don’t know. I welcome feedback from owners of other manufacturers’ portable power stations (as well as from both EcoFlow and other manufacturers’ representatives themselves) regarding their comparative reliability. And I’d also appreciate insights from other EcoFlow owners re the commonality-or-not of their experiences. Sound off with your thoughts in the comments, please!

—Brian Dipert is the associate editor, as well as a contributing editor, at EDN.

Related Content

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• Single-battery failures in multi-battery arrangements: diagnosing selective cell derangements
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• EcoFlow’s DELTA 3 Plus and Smart Extra Battery: Product line impermanence curiosity
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• EcoFlow’s Delta 2: Abundant Stored Energy (and Charging Options) for You
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• Portable power station battery capacity extension: Curious coordination
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• Firmware-upgrade functional defection and resurrection
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The post More EcoFlow woes: So it goes appeared first on EDN.

This week’s latest iteration of Google’s yearly developer event reiterated the company’s significant AI commitment. What’s different from messaging and examples past? Maturity.

One of the technologies showcased in the most recent edition of my previous-year retrospective series, published on New Year’s Day, was agentic AI. An overview excerpt from that earlier coverage follows:

Here’s what Wikipedia says about AI agents in its topic intro:

“In the context of generative artificial intelligence, AI agents (also referred to as compound AI systems or agentic AI) are a class of intelligent agents distinguished by their ability to operate autonomously in complex environments. Agentic AI tools prioritize decision-making over content creation and do not require human prompts or continuous oversight.”

And what about the aforementioned broader category of intelligent agents, of which AI agents are a subset? Glad you asked:

“In artificial intelligence, an intelligent agent is an entity that perceives its environment, takes actions autonomously to achieve goals, and may improve its performance through machine learning or by acquiring knowledge. AI textbooks define artificial intelligence as the “study and design of intelligent agents,” emphasizing that goal-directed behavior is central to intelligence. A specialized subset of intelligent agents, agentic AI (also known as an AI agent or simply agent), expands this concept by proactively pursuing goals, making decisions, and taking actions over extended periods.”

A recent post on Google’s Cloud Blog included, I thought, I concise summary of the aspiration:

“Agentic workflows represent the next logical step in AI, where models don’t just respond to a single prompt but execute complex, multi-step tasks. An AI agent might be asked to “plan a trip to Paris,” requiring it to perform dozens of interconnected operations: browsing for flights, checking hotel availability, comparing reviews, and mapping locations. Each of these steps is an inference operation, creating a cascade of requests that must be orchestrated across different systems.”

I suggested there that last year’s rapid evolution of agentic AI technology and products based on it wasn’t a one-off; that the maturation and proliferation trends would undoubtedly continue in the coming year and beyond. We’re nearing the 2026 mid-point and, judging from what Google showcased at yesterday’s keynote, I wasn’t offbase with my earlier perpetuation prediction:

But I’m getting ahead of myself…

Android Show: I/O Edition 2026

Google extended the trend it initiated last year by delivering a separate Android-specific showcase one week ahead of the main event:

Company representatives covered a lot of ground in only a bit more than a half hour, including pending enhancements to Android Auto and “Continue On”, an in-beta conceptual clone of Apple’s Handoff. But two other topics particularly caught my eye. Generally speaking, Google is fundamentally integrating Gemini Intelligence even more than previously into the core of both Android and its Chrome browser, including both anticipatory awareness of what you might need next and the agentic “chops” to independently (potentially) tackle such tasks on your behalf.

The central reason why I find this trend interesting is contextual in nature. Both Amazon (again) and OpenAI are reportedly working on smartphones based on brand new AI-based—specifically agentic, generative and personalized—operating systems. Going “clean slate” from a software standpoint does have at least some advantages, conceptually speaking at least, but it also tends to result in a “heavy lift” with respect to application development, internally and especially from a third-party standpoint. Conversely, Google’s building on a longstanding Android foundation.

Consider that contrast, too, in the context of the other key Android Show tidbit that I want to pass along today. Confirming longstanding rumor, Google announced that it is seriously re-engaging in the tablet market with Android (where, to clarify, it remains a “player” today, primarily courtesy of its Samsung partnership, albeit on a limited basis versus Apple iPad alternatives), as well as expanding Android into computing form factors that were traditionally serviced by Chrome OS, all with a new operating system version code-named “Aluminum”.

The coexistence of the two operating systems had always been awkward at best. They’re both built on a Linux foundation, but that’s kind of like saying that a Trabant and a Ferrari both hail from a Ford Model T heritage. I’m not trying here to infer a vehicle-analogous comparison between the two operating systems with respect to “sleekness”, price or anything like that, only generally proffering that they’re notably dissimilar. Different code bases, different development teams and schedules…over time, Android and Chrome OS had increasingly diverged, to their shared detriment.

And what does “Aluminum” mean for Chrome OS fortunes long-term? Unclear; the latter’s only notable success has been in the education market, but it’s been a notable success there, so Google needs to be careful about how it hand-holds these key customers during the transition (which I’d suggest is a matter not of if, but when). Event-delivered reassurances included that support-timeframe schedules for existing Chrome OS-based products would continue to be honored in full, that new Chrome OS-based products were still in the development pipeline from partners, and that at least some existing Chrome OS-based hardware would be upgradeable to whatever the marketing moniker for “Aluminum” ends up being. That said, if new Chrome OS hardware is still being announced when the decade turns in a few years, I’ll be shocked.

Foundation AI evolutions

Now for the main event. AI has been front and center in Google I/O messaging for a while now, as The Verge and I joked about two years back:

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@verge \n

Pretty sure Google is focusing on AI at this year’s I/O. #google #googleio #ai #tech #technews #techtok

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♬ original sound – The Verge

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And it was more of the same this year. For those of you who’ve been wondering what the term “foundation model” (or variants of that name) means, I’ll start out with a Wikipedia-sourced definition:

In artificial intelligence, a foundation model (FM), also known as large x model (LxM, where “x” is a variable representing any text, image, sound, etc.), is a machine learning or deep learning model trained on vast datasets so that it can be applied across a wide range of use cases. Generative AI applications like large language models (LLM) are common examples of foundation models.

Building foundation models is often highly resource-intensive, with the most advanced models costing hundreds of millions of dollars to cover the expenses of acquiring, curating, and processing massive datasets, as well as the compute power required for training. These costs stem from the need for sophisticated infrastructure, extended training times, and advanced hardware, such as GPUs.

This all in contrast to dataset- and application-specific models. Wikipedia again:

Adapting an existing foundation model for a specific task or using it directly is far less costly, as it leverages pre-trained capabilities and typically requires only fine-tuning on smaller, task-specific datasets.

Last year at I/O, Google shared updates on v2.5 of its Gemini model family (standard, Flash and Pro), which had been introduced a few months earlier. Gemini v3 subsequently arrived last November. And now we’re up to Gemini family v3.5. Commensurate with the update, another term is in circulation for us to sort out: “Frontier model”. NVIDIA with the definition this time:

Frontier models are the most advanced AI models available at a given moment, trained on massive datasets to deliver state-of-the-art performance across many tasks, representing the leading edge of AI capability. They typically power advanced reasoning, image and text generation, and agentic workflows.

Translation: a fancy way of saying “next generation”. Gotta love those marketeers.

More generally, snark aside, I admittedly was particularly gob smacked by this subset of the event-opening keynote remarks by CEO Sundar Pichai:

These stories of how people are using AI are the best measure of progress. To understand the scale at which people are adopting AI, there is another great proxy — tokens, the fundamental units of data our models process, many representing a problem being solved.

Two years ago, we were processing 9.7 trillion tokens a month across our surfaces — a huge number. Last year at I/O, that grew to roughly 480 trillion tokens. Fast forward to today, that number jumped 7x to over 3.2 quadrillion per month. [Editor note: token maxxing? Likely, to a degree. Still…]

It tells an important story about our products and how others are building as well — especially developers and enterprises:

\n
• Over 8.5 million developers are now building new apps and experiences with our models monthly.
\n
• Our model APIs are now processing roughly 19 billion tokens per minute.
\n
• Over the past 12 months, over 375 Google Cloud customers each processed more than one trillion tokens, representing incredible demand for AI from across industries.
\n

Today we have 13 products with over a billion users each. Five of those have more than 3 billion users. [Editor note: and they’re all AI-enhanced, if not AI-centric]

Multimodal and agentic enhancements

Back in December 2024, within a broader attempt to forecast the year to come, I opined:

Large language models (LLMs), which I rightly showcased at the very top of my 2023 retrospective list, are increasingly impressive in their capabilities. But they’re also, admittedly somewhat simplistically speaking, “one-trick ponies”. As their name implies, they’re language-based from both input (typed) and output (displayed) standpoints. If you want to speak to one, you need to first run the audio through a separate speech-to-text model (or standalone algorithm); the same goes for spitting a response back at you through a set of speakers. Analogies to images and video clips, and other sensory and output data, are apt.

Granted, this approach is at least somewhat analogous to human beings’ cerebral cortexes, which are roughly subdivided into areas optimized for language, vision and other processing functions. Still, given that humans are fundamentally multisensory in both input and output schema, any AI model that undershoots this reality will be inherently limited. That’s where newer multimodal models come in. Vision language models (VLMs), for example, augment language with equally innate still and video image perception and generation capabilities. And large multimodal models (LMMs) are even more input- and output-diverse. Think of them as the deep learning analogies to the legacy sensor fusion techniques applied to traditional processing algorithms, which I ironically alluded to in my 2022 retrospective.

Enter the new Gemini Omni multimodal model:

Last year, Nano Banana brought Gemini’s intelligence to image generation and editing. Since then, it’s helped millions of people restore old photos, design from sketches and visualize ideas in ways that weren’t possible before. From the start we built Gemini to be natively multimodal from the ground up, and now we’re taking the next step.

We’re introducing Gemini Omni, where Gemini’s ability to reason meets the ability to create. Omni is our new model that can create anything from any input — starting with video. With Omni, you can combine images, audio, video and text as input and generate high-quality videos grounded in Gemini’s real-world knowledge. You can also easily edit your videos through conversation.

Today, we’re rolling out the first model in the Omni family: Gemini Omni Flash, to the Gemini app, Google Flow and YouTube Shorts. In time we will support output modalities like image and audio.

And what about burgeoning agentic AI assistants such as OpenClaw? How’s that saying go—”Imitation is the sincerest form of flattery”—albeit this time with innate Google services and account-data access?

We’re also introducing Gemini Spark, a 24/7 personal AI agent that helps you navigate your digital life. Spark represents a big shift for Gemini, transforming it from an assistant that can answer your questions into an active partner that does real work on your behalf and under your direction.

Gemini Spark runs on Gemini 3.5 and uses the Antigravity harness. It’s deeply integrated with the Workspace tools you rely on daily, like Gmail, Docs, Slides and more. Even better, because it is a cloud-based agent, Spark keeps working in the background even when you close your laptop or lock your phone. That combination means Spark is ready to take complex tasks off your plate so you can be more present for what matters most.

“Intelligent Eyewear”

Last but not least, a few words about head-located wearables, including those with integrated displays. Google seems to be reluctant to refer to them as “smart glasses” (or VR headsets, for that matter). Gee, I wonder why? And why? Snark off (again). As regular readers may already recall, I’ve been following this market quite closely in recent years, even personally investing in a few trendsetting product examples. And we’ve in-parallel been hearing about (and I’ve been writing about) Google’s Android XR operating system and application suite for augmented, virtual and hybrid reality systems for a while now, too.

Well, the reality behind the hype is finally coming to market starting this fall. Supposedly. Conceptually, they sound a lot like Meta’s counterparts (albeit perhaps a bit sleeker) which I’d suggest have been meaningful from an implementation standpoint since at least the October 2023 unveil of the second-generation AI Glasses. That said, Meta’s success has to date been held back by (among other factors) a dearth of third-party support. Here’s a reality calibration: even if Google and partners’ competitive devices are no better off in this regard, their inherent coordination with the aforementioned “Google services and account data” will still give them a “leg up”. More generally, you’ve got to admit this was one heck of a compelling live demo suite:

We shall see.

Wrapping up

There was plenty more interesting news released at the Tuesday keynote and more broadly across the two-day event (which is still underway as I type these words mid-day on Wednesday). Browse other writeups on the Google event portal page, along with coverage at 9to5Google and elsewhere. And then share your thoughts with me and your fellow readers in the comments!

The post Google I/O 2026: Agentic AI gets serious appeared first on EDN.

Ground-referenced loads are common in industry. This circuit implements current loop conversions for them.

Recently, there have been several published Design Ideas on converting 0/20mA to 4/20mA current and 4/20mA to 0/20mA current as full-circle current loop conversions. However, these circuits have all focused on floating loads. It’s common to also come across loads that are ground-referenced. The circuit in Figure 1 addresses this alternative requirement, converting 4/20mA current to 0/20mA current for feeding grounded loads.

Wow the engineering world with your unique design: Design Ideas Submission Guide

\nFigure 1 In this 4/20mA to 0/20mA converter for grounded loads, R4 and RB can be replaced by multi-turn potentiometers for tuning purposes.

How does it work? Input current of 4-20mA feeds into R1 and is converted into 0.4V – 2.0V, which is buffered by U2A. U1 generates a reference current of 1mA which is is fed into R4, and which converts it to 0.4V. This converted current is buffered by U2B. U2C subtracts the two voltages.

Next, let’s look at the positive input of U2D. There are two currents:

\n
• One current going through Ra=
\n
• Another current going through Rb= –
\n

Since the negative input of U2D is grounded, these two currents must be same:

= where I ref*R4 is 0.4V

Iout =

Select the values of Rb and Rc such that Rb/Rc =124. Substituting the values of Ra, Rb, Rc and R1 from Figure 1:

Iout =

Hence, Iout= (Iinput-4 mA)*1.25. For example, if the I input is 20 mA, I out= (20-4)*1.25=20mA. And if the I input is 4mA, I out= (4 – 4) * 1.25=0mA.

How do you tune the circuit? Implement R4 and Rb as multi-turn potentiometers. R1 conversely should be a precision 100 ohm resistor. Adjust R4 such that voltage across it is 0.4 V. Feed 20mA current from the precision current source as the Iinput and adjust Rb to get 20mA as Iout. Repeat this exercise by feeding the circuit with 4mA and 12mA.

Simulation test results follow:

These results suggest that the circuit delivers high accuracy, with error no higher than 0.5%, except with a 4mA input. The error and associated accuracy can be improved by selecting high-end operational amplifiers such as instrumentation amplifiers with negligible offset and a high common-mode rejection ratio (CMRR).

Q2 prevents the output current from exceeding a few mA above the 20mA input threshold, as a safety measure. R5, R6, and R7 should be identical in value. And also implement R8 as a multi-turn potentiometer. The resultant tuning capability helps to reduce the output to near-zero for a 4mA input.

Jayapal Ramalingam has over three decades of experience in designing electronics systems for power & process industries and is presently a freelance automation consultant.

Related Content

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• Silly simple precision 0/20mA to 4/20mA converter
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• Combine two TL431 regulators to make versatile current mirror
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• A 0-20mA source current  to 4-20mA loop current converter
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The post 4/20mA to 0/20mA loop current converter for grounded loads appeared first on EDN.

There is a growing architectural tension at the heart of modern AI infrastructure. The processors that enabled the deep learning revolution—graphics processing units (GPUs)—remain the dominant engines of large-scale training and inference. Yet the computational profile of frontier language models is evolving in ways that increasingly expose the structural assumptions embedded in GPU design.

Memory wall undermining GPU efficiency in LLMs

A profound bottleneck lies on the memory wall, the growing performance gap where processors can execute arithmetic operations far faster than memory systems can supply data, causing increasingly powerful compute units to sit idle while waiting on bandwidth- and latency-limited data movement.

Using the Nvidia H100 as a reference point, modern GPUs deliver multiple petaflops of FP8 tensor throughput and several terabytes per second of high-bandwidth memory access. On paper, arithmetic capacity is immense. In practice, trillion-parameter-class large language models (LLMs) are frequently memory-bound. Arithmetic intensity during inference can fall below 10 FLOPs per byte, which means that performance is limited less by compute units and more by how quickly parameters can be fetched and activations moved.

Energy considerations reinforce this imbalance. A floating-point multiply-accumulate is inexpensive relative to a high bandwidth memory (HBM) access, and cross-chip communication can cost orders of magnitude more energy than local arithmetic. See Table 1.

Table 1 Here is a comparison among capacity, energy consumption, bandwidth, and latency in a typical memory hierarchy. Source: Author

As model size grows, an increasing share of system energy is spent moving data rather than computing on it. The arithmetic units stall while waiting for weight tensors to arrive, and effective throughput becomes a function of bandwidth and latency rather than raw FLOPS. The challenge compounds when models exceed single-device memory capacity and must be distributed across multiple accelerators.

Frontier LLMs challenging foundations of GPU architecture

The historical success of GPUs in machine learning emerged from an unusually strong alignment between hardware structure and model behavior. Modern GPUs from companies such as Nvidia and AMD are fundamentally throughput-oriented processors built around the single instruction multiple threads (SIMT) execution model.

Groups of threads—warps on Nvidia architectures, wavefronts on AMD architectures—execute instructions in lockstep. Maximum efficiency is achieved when threads follow identical execution paths, access memory in predictable patterns, and sustain dense arithmetic workloads with minimal synchronization overhead.

This design originated in graphics rendering, where millions of pixels or vertices undergo nearly identical operations in parallel. The same architectural assumptions proved highly effective for early deep learning systems, particularly convolutional neural networks and dense transformers. Large matrix multiplications, regular tensor shapes, and high arithmetic intensity mapped naturally onto GPU tensor cores and wide vectorized execution pipelines. Under sufficiently large batch sizes, GPUs can sustain exceptionally high utilization because computation dominates memory latency and control-flow overhead.

Frontier LLMs, however, are evolving away from the dense and homogeneous workloads that originally favored GPU architectures.

Modern LLM systems increasingly incorporate conditional computation: mixture of experts (MoE) layers, dynamic token routing, retrieval augmentation, speculative decoding, adaptive context management, variable sequence lengths, and sparsity-aware attention mechanisms. These techniques improve scaling efficiency at the model level by reducing the amount of computation performed per token while preserving or increasing representational capacity. They also introduce irregularity into execution patterns, precisely the condition under which SIMT architectures become less efficient.

The key issue is not simply “warp divergence” in the narrow classical GPU sense where threads within a warp follow different branches of a control-flow statement. In many MoE implementations, tokens routed to different experts are regrouped before execution specifically to minimize intra-warp divergence.

The deeper architectural tension is broader: SIMT processors are optimized for spatially and temporally coherent workloads, while modern frontier inference increasingly behaves like sparse, dynamically scheduled computation with uneven work distribution and heavy communication dependencies.

In dense transformers, nearly every parameter participates in every token evaluation. Computational intensity remains high, tensor dimensions are regular, and work scheduling is relatively predictable. In sparse MoE systems, by contrast, only a small subset of experts may activate for a given token. A model with 16 experts and top-2 routing, for example, activates only a fraction of total parameters at each inference step. Although this dramatically improves parameter efficiency from a modeling perspective, it also fragments execution into uneven and dynamically changing workloads.

The consequence is reduced effective hardware utilization, not necessarily because every warp is internally diverging, but because the overall system struggles to maintain uniform occupancy, balanced scheduling, and continuous tensor-core saturation. Some experts become overloaded while others sit idle.

Token batches routed to a given expert may be too small to fully utilize matrix engines efficiently. Memory access patterns become less regular. Kernel launch granularity deteriorates. Synchronization overhead increases. The result is that the theoretical arithmetic throughput of the GPU becomes increasingly difficult to translate into sustained application-level throughput.

Furthermore, interactive AI workflows, especially AI agents that respond step by step, are difficult for GPUs to run efficiently. GPUs work best when they can process very large batches of data at once. In LLMs, this usually means combining many user requests together into large matrix operations. Large matrix operations are efficient because they involve much more computation than data movement, keeping the GPU fully occupied.

But interactive systems need low latency: the model must respond immediately instead of waiting to accumulate a large batch of requests. That means the batch size stays small. Small batches create smaller matrix operations that are less efficient on GPUs. The GPU spends more time moving data around and less time doing computation. As a result, GPU utilization drops. So, there is a trade-off. Large batches lead to high GPU efficiency but higher latency. Conversely, small batches cause low latency but worse GPU efficiency.

Agentic workflows usually prioritize responsiveness, which is why they are harder to run efficiently on GPUs.

The resulting inefficiencies are often obscured by headline FLOP metrics. Modern accelerators advertise enormous peak throughput numbers, but peak throughput reflects idealized dense execution under carefully tuned conditions. Real-world frontier inference frequently operates far from these conditions.

Effective utilization may decline substantially when workloads become routing-heavy, communication-bound, latency-sensitive, or dynamically imbalanced. In practice, the limiting resource increasingly shifts from raw arithmetic capability to orchestration efficiency across memory systems, interconnects, and distributed scheduling layers.

The hidden GPU complexity tax

Alongside these architectural mismatches lies another challenge: the growing software and optimization burden required to extract acceptable performance from GPU systems.

GPUs do not automatically deliver near-peak efficiency. High performance requires extensive manual optimization across multiple abstraction layers. Developers must orchestrate host-device memory transfers, optimize tensor layouts, tune kernel launch parameters, manage register pressure, balance shared-memory usage, fuse operations to reduce synchronization overhead, and carefully align workloads with hardware-specific execution characteristics. Small deviations in tensor dimensions, sequence lengths, routing distributions, or batch composition can materially reduce throughput.

As models become more dynamic, optimization itself becomes more fragile. Kernels tuned for one generation of hardware may perform poorly on another. Code paths optimized for dense transformers may degrade under sparse routing conditions. Performance engineering increasingly depends on vendor-specific toolchains such as CUDA, custom compiler stacks, graph schedulers, and specialized communication libraries tightly coupled to a particular hardware ecosystem.

The cumulative effect is a growing “complexity tax” surrounding GPU-centric AI infrastructure. The cost is not merely electrical power or silicon area, but engineering specialization, portability constraints, software maintenance overhead, and system fragility. As frontier models continue shifting toward sparse, distributed, and conditionally executed architectures, the tension between SIMT-oriented hardware assumptions and emerging AI workloads is becoming increasingly difficult to ignore.

Alternative AI processing architectures are mandatory

These pressures have catalyzed interest in alternative accelerator architectures designed explicitly around transformer workloads and data movement efficiency. Systems such as the TPUs developed by Google emphasize systolic arrays and compiler-driven dataflow scheduling to improve determinism and reduce divergence overhead.

Cerebras Systems has pursued wafer-scale integration, placing tens of gigabytes of SRAM directly on-chip in its wafer-scale engine to minimize off-chip memory traffic and reduce partitioning complexity. Graphcore designed its intelligence processing unit (IPU) around fine-grained parallelism and distributed local memory, explicitly targeting irregular and sparse workloads.

Drawing on more than two decades of architectural expertise and 14 silicon tapeouts, VSORA developed an approach replacing the SIMT computational model with a dataflow architecture specifically engineered to overcome the memory wall. At its core is a massive flat register file spanning several megabytes, designed to supply data directly to large arrays of compute engines organized into wide, deeply pipelined execution paths.

Anticipating the evolving requirements of edge inference and future AI algorithms such as those for autonomous driving (AD L3-L5) applications, it also designed and embedded highly programmable processing cores capable of executing an extensive library of DSP operations with low latency and high efficiency.

While each approach involves trade-offs and varying degrees of ecosystem maturity, they share a common premise: future AI workloads are constrained less by arithmetic throughput and more by data orchestration, locality, and communication efficiency.

The next compute frontier

The broader trend in AI systems reflects a shift in the dominant bottleneck. During the convolutional era, compute capacity measured in TFLOPS was the primary metric. Early transformer models balanced compute and memory bandwidth. Frontier LLMs at trillion-parameter scale are now constrained primarily by memory movement and interconnect efficiency. As sparsity and conditional activation become central architectural features, the efficiency of routing and dataflow scheduling begins to outweigh peak arithmetic density.

GPUs remain foundational to AI infrastructure, particularly in training. Their ecosystem maturity, programmability, and unmatched dense training throughput ensure continued relevance, particularly during large-scale pretraining where arithmetic intensity remains high and workloads are relatively regular. However, as models grow more conditional, more distributed, and more memory-bound, the architectural friction becomes increasingly visible.

The future of AI acceleration will likely reward designs that privilege data locality, minimize cross-device communication, and execute sparse patterns natively rather than emulating them within a dense SIMT framework.

The decisive question for next-generation systems is no longer how many floating-point operations per second can be delivered in isolation. It is how efficiently data can be moved, routed, and scheduled across increasingly complex and sparsely activated models.

Lauro Rizzatti is a business development executive with VSORA, a technology company offering silicon semiconductor solutions that redefine performance. He is a noted chip design verification consultant and industry expert on hardware emulation.

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The post GPUs: A high-throughput architecture confronting a workload shift appeared first on EDN.

Regardless of the applications, most artificial intelligence (AI) chip designers face the same challenges. Whether it’s cloud data centers, edge devices, automotive platforms, or industrial robotics, optimal performance now depends on how efficiently data is moved.

When data movement is delayed, even the fastest compute engines are left waiting, reducing throughput, increasing latency, and wasting power.

As AI designs continue to grow in complexity, managing massive data flows through fixed, point-to-point connections no longer scales efficiently. Designers are now dealing with hundreds of compute engines and memory instances, each with different performance requirements, all of which must move data simultaneously.

A network-on-chip (NoC) brings order to chaos by providing a scalable, shared communication infrastructure that moves data where it needs to go with controlled latency and bandwidth. With built-in mechanisms for congestion management, traffic prioritization, and workload isolation, NoCs help teams deliver consistent, predictable performance while staying within tight power, area, and timing budgets.

Different markets, same bottleneck

Whether in hyperscale cloud infrastructure or inside an embedded vision processor, the core problem is data bottlenecks. The end markets differ, but the underlying architectural constraint remains the same. In the cloud, the goal is maximum throughput. Training clusters push bandwidth into the terabytes-per-second range. Massive GPUs and AI accelerators continuously ingest and process vast datasets. In large data center GPUs, more than 80% of dynamic energy is consumed by data transfers to and from DRAM. That energy is not spent on computing. It is spent moving bits.

At the edge, priorities flip. Systems such as autonomous vehicles, robotics, and smart cameras demand microsecond-level latency, strict determinism, and ultra-low power consumption. Edge AI devices may spend up to 90% of inference time waiting on memory I/O.

This is the invisible drain on AI performance.

Why NoC architecture matters

The NoC is the backbone that determines how efficiently data flows within a system-on-chip (SoC) or across multiple dies. However, the NoC must be optimized correctly. If not, the entire system slows down, regardless of how powerful the compute cores may be.

AI designs often rely on wide parallel interfaces between IP blocks. As system innovation increases, routing congestion, timing closure issues, and power overhead become more difficult to manage. An NoC addresses these challenges by packetizing traffic. Transactions are broken into packets and routed across a structured fabric, much like off-chip networking. This approach significantly reduces wiring complexity.

A wide AXI interface can require hundreds of signals; for example, a given AXI bus interface that requires 280 signals can be reduced to 150 by packetizing transactions. Fewer wires mean less congestion, simpler routing, easier timing closure, reduced silicon area, and lower dynamic power, as shown in the figure below.

Here is an outline of the advantages of packetized data with NoC IP Source: Arteris

Equally important, an NoC decouples IP blocks from transport details. Designers integrate heterogeneous CPUs, GPUs, NPUs, memory controllers, and accelerators without manually wiring hundreds of signals between blocks. The network fabric handles transport abstraction. This level of decoupling does more than simplify integration within a single die. It also lays the groundwork for the next major shift in system design, where functionality is distributed across multiple dies and coordinated at the system level.

From monolithic dies to systems of systems

The separation of IP from transport becomes critical as designs transition to chiplet-based architectures. The shift enables teams to optimize each piece of silicon independently for its specific function and power trade-offs. It also improves yield, lowers costs, and makes it easier to increase compute capacity by adding or reusing chiplets as requirements change.

Within each die, a coherent NoC uses standard protocols such as AMBA CHI or ACE. Non-coherent fabrics connect peripherals and specialized engines into the broader system. Across dies, UCIe enables high-speed die-to-die communication. In advanced multi-package systems, coherent and non-coherent NoCs communicate seamlessly across chiplet boundaries.

The result is effectively a system of systems, with multiple specialized silicon components orchestrated into a unified compute engine. The NoC fabric spans the entire package, coordinating traffic between dies and subsystems.

In this environment, the interconnect is no longer just a supporting block. It shapes the entire system architecture. Every AI system, whether in the cloud or at the edge, has to strike the right balance among three things. Bandwidth must keep GPUs, XPUs, and AI engines fully utilized. Latency must remain low to support real-time inference and control. Efficiency must hold power and thermal budgets within limits as systems expand.

Designers also need a practical way to grow compute resources without redesigning the interconnect. Modular tiling approaches address that need. Each tile includes its own network interface unit and can be replicated across an NPU array. Need more compute? Add more tiles. The fabric scales without requiring a complete redesign.

Closing the architectural loop

In AI SoCs, designing the NoC requires more than defining the logical topology. Engineers should introduce physical awareness early in the design process. That means using floorplan information, estimated wire distances, and timing constraints. Physical awareness must be built directly into the design flow.

A modern NoC design flow includes:

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1. High-level architectural modeling and simulation
\n
2. Integration of physical constraints through virtual floor planning
\n
3. Automatic insertion of pipeline stages with built-in timing analysis
\n
4. Closed-loop export of constraints to physical synthesis tools
\n

This approach bridges the gap between architectural intent and layout reality. In production designs, physically aware NoC automation has demonstrated the ability to reduce total wire length by roughly 26%, cut maximum latency by half, and improve overall productivity by an order of magnitude. Tasks that once required weeks of manual tuning can now be completed in less than a day.

Cache hierarchy and data locality

Interconnect optimization must be paired with effective cache architecture. Multi-level cache hierarchies, including L1, L2, and L3, store frequently used data close to the compute engines, reducing memory access latency. Without an effective cache hierarchy, CPU utilization can drop to single digits.

In some AI SoC regions, last-level non-coherent caches improve data availability without participating in a full coherency protocol. Workloads that do not require tight synchronization, such as certain signal-processing or multimedia tasks, benefit from this approach, which simplifies the design while improving throughput. By increasing data locality, the cache structure reduces reliance on external memory and stabilizes interconnect traffic.

The reality of AI SoC design

The cost of developing leading-edge SoCs has risen from under $100 million a decade ago to more than $700 million today. So, each design iteration or silicon re-spin carries enormous financial risk.

Manual integration processes, fragile scripting, and misaligned hardware-software interfaces amplify that risk. Automated SoC integration flows that validate IP early, maintain consistent specifications across teams, and compile millions of registers in minutes can significantly reduce development time and errors.

Arteris addresses these architectural demands with interconnect IP purpose-built for complex AI platforms where efficient data transport determines overall system behavior. Its FlexNoC and Ncore solutions provide configurable non-coherent and coherent fabrics that support heterogeneous compute clusters and multi-die designs, reducing communication bottlenecks that limit utilization.

By aligning scalable interconnect architecture with disciplined implementation methodology, these interconnect solutions enables design teams to translate system intent into silicon more predictably in an era defined by rising complexity and cost sensitivity.

Automation and physically aware design are no longer optional optimizations. They are survival tools in the AI decade.

Andy Nightingale, VP of product management and marketing at Arteris, has over 39 years of experience in the high-tech industry, including 23 years in various engineering and product management roles at Arm.

Related Content

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The post How data movement defines performance for AI silicon appeared first on EDN.

The Sensors Converge 2026 conference showcased some of the latest advances in sensor and sensing solutions for applications ranging from wearables and smartphones to industrial and automotive. The show, with over 160 exhibitors, also highlighted the industry’s shifting focus to edge AI and smart, connected systems with demos that showcased real-world applications in edge AI, robotics, and autonomous systems.

While sensor manufacturers continue to focus on shrinking solutions and package sizes, this year’s product introductions also indicate an increased need for lower power consumption. Here is a sampling of new sensors featured at this year’s show.

Vibration sensors across wearables and industrial

Upbeat Technology showcased its latest family of low-power MEMS vibration sensors and vibration processing units (VPUs), including the UPM01 and UPM02 series with a UP201/301 dual-core RISC-V AI microcontroller (MCU), aimed at high-quality voice clarity and predictive intelligence in a small footprint.

Suited for space-constrained wearables applications, the UPM01/UPM02 VPU, also called a bone-conduction microphone, measures 3.2 × 2.5 mm, and the UP201 dual-core RISC-V AI MCU measures 3.0 × 3.0 mm. Together, they create Upbeat’s Tiny AI Engine that provides on-device intelligence to wearables, industrial systems, drones, and consumer electronics. The solution enables “crystal-clear voice” in open wearable stereo (OWS) headsets, smart glasses, and intelligent voice recorders and delivers predictive maintenance for industrial automation.

The UPM01 series offers multiple interface variants: the UPM01A (analog), UPM01Ax (higher-sensitivity analog), UPM01D (digital), and UPM01Dx (higher-sensitivity digital). The UPM02 provides analog and digital options with a higher signal-to-noise ratio (SNR) for applications in which audio clarity is critical, the company said.

The UPM01 extends the frequency response of conventional MEMS vibration sensors from 5 Hz to 11.3 kHz and delivers an SNR of 60 dB(A) for a more accurate sound capture, while the UPM02 offers a frequency response range from 5 Hz to 5.4 kHz and an exceptionally high SNR of up to 68 dB(A).

Both series consume minimal power and can operate for extended periods on a single battery charge, making them suited for mobile devices, wearables, and other battery-powered applications.

The UP201/UP301 heterogeneous dual-core RISC-V edge AI platform targets energy-efficient deep-learning applications, enabling AI analysis closer to the data source for fast response and lower bandwidth usage. Delivering ultra-low-power, always-on intelligence, the platform enables continuous sensing with minimal power and instant wake-up for intensive AI tasks.

Mass-production shipments for the UPM01/UPM02 have started, with the UP201/UP301 scheduled to ship in October 2026.

Upbeat also unveiled its UP301 + UPM01 Falcon Demo Kit, described as a ready-to-run evaluation platform for machine-vibration analysis. Aimed at engineers who want to prototype and validate predictive maintenance solutions, the kit includes a UP201 dual-core RISC-V AI MCU EVB, variable-speed motor, two UPM01D FPCs, power adapter, and access to the Falcon graphical user interface (GUI), the Upbeat Vibration Analysis Suite GUI software. The demo kit is available for purchase at www.upbeattechtw.com/products/demo-kits.

Other demonstrations included OWS headsets, smart glasses with AI voice interaction, a smart AI voice recorder, a factory machine-vibration application, and smart AI toys with touch-gesture recognition.

Ahead of the show, STMicroelectronics announced its wide-bandwidth, three-axis vibration sensor, aimed at saving space and energy in industrial and automotive condition-monitoring applications. With an extended temperature range of −40°C to 125°C, the IIS3DWBG1 enables vibration monitoring in harsh environments.

The IIS3DWBG1 offers a selectable, full-scale acceleration range of ±2/±4/±8/±16 g and can measure accelerations with a bandwidth up to 6 kHz with an output data rate of 26.7 kHz. Housed in a 2.5 × 3-mm LGA-14L package, the MEMS sensor is suitable for industrial condition-monitoring systems, in which sensor placement and mounting are critical to measurement accuracy.

The small size and wide operating temperature range allow the flexibility to place small, externally attached sensors at optimal diagnostic locations while enabling integration inside smart motors and smart gearboxes, ST said.

In addition, the low power consumption delivers long-lasting operation in battery-powered applications. The sensor’s wide bandwidth and high resolution simplify capturing patterns associated with defects or wear, as well as equipment setup issues such as looseness and misalignment.

The IIS3DWBG1 can also detect electromechanical vibrations in coils, transformers, snubber capacitors, busbars, connectors, and general vibrations originating in the power electronics module, such as traction inverters. This enables automotive OEMs to extend remote diagnostics to cover power modules, as well as traction inverters in electric vehicles.

Thanks to a flat frequency response from DC to above 6 kHz (−3 dB point) and noise density of 75 µg/√Hz in three-axis mode, the sensor detects extremely small vibrations, providing enhanced early warning to prevent equipment failures. The sensor is highly resistant to mechanical shocks, according to ST, and integrates digital features including a configurable low-pass or high-pass filter with selectable cutoff frequency, an embedded FIFO, interrupts, a temperature sensor, and self-test capability.

The IIS3DWBG1 is in production now. An evaluation kit is available.

AMR and TMR sensors

Murata Manufacturing Co. Ltd. introduced its ultra-low-power anisotropic magnetoresistance (AMR) sensors, the MRMS166R and MRMS168R. These sensors are designed to increase battery life in healthcare, wearable, and IoT devices. The MRMS166R is claimed as the first AMR sensor to combine an average current consumption of 20 nA with operation from a 1.2-V supply, enabling extended battery life in coin-cell-powered systems.

These solid-state magnetic sensors detect the presence or absence of a magnetic field and generate an output signal that system logic uses to control functions such as transitions between active and sleep modes. This provides contactless switching without mechanical components, improved reliability, and support for sealed, miniaturized designs, Murata said.

This automatic switching between active and sleep modes is widely used in battery-powered devices to reduce standby power consumption and extend operating life, Murata said. Applications include healthcare, such as capsule endoscopes and medical patches; wearable devices, including AR glasses and wireless earbuds; and security-related IoT devices, such as door-open/close-detection systems and smart locks.

These devices commonly use silver oxide coin batteries (typically 1.55 V) that place constraints on available capacity and operating voltage. This means AMR sensors used as magnetic switches must minimize current consumption while maintaining stable operation at a low voltage, Murata said.

To address these challenges, Murata redesigned the AMR sensor’s internal circuitry, enabling ultra-low current consumption and operation down to 1.2 V. This significantly reduces battery consumption during standby operation, supporting device operation for more than two years in typical use.

The MRMS166R operates over a 1.2-V to 3.6-V supply range (1.5 V typ.) with an average current consumption of 20 nA and a maximum current output of 1 mA. The MRMS168R operates over a 2.0-V to 3.6-V supply range (3.0 V typ.), with an average current consumption of 80 nA and a maximum output current of 12 mA, providing higher output drive capability for devices requiring increased load current. Both devices are housed in a compact package measuring 1.0 × 1.0 × 0.4 mm (0.04 × 0.04 × 0.02 inches). The MRMS166R and MRMS168R sensors are now in mass production.

MultiDimension Technology Co. Ltd. debuted its tunneling magnetoresistance (TMR) TMR2531 (±1,000-Gauss linear range) and TMR2539 linear sensors (extended ±1,500-Gauss linear range) for smartphone cameras at Sensors Converge. Available in production quantities, these ultra-compact TMR linear sensors are designed for high-precision smartphone optical image stabilization (OIS) applications.

These sensors enable micron-level displacement measurement in voice coil motor (VCM) modules, allowing VCM driver ICs to precisely correct camera shake in real time during photo and video capture, MDT said. They measure the z-axis perpendicular magnetic field amplitude via a Wheatstone full-bridge configuration with four high-SNR TMR elements.

Periscope-style telephoto lenses have pushed OIS precision requirements into the micron scale to control prism positioning over extended motion ranges, MDT said. The new TMR sensor technology addresses these challenges with a high SNR, broad linear measurement ranges, and high immunity to magnetic interference, making it suited for advanced camera autofocus and OIS solutions in flagship smartphones.

Both series offer a 1.0-V to 5.5-V supply voltage and a shielding capability of ±3,000 Gauss for stable operation in interference-prone VCM environments. They are housed in a small DFN4L package (0.8 × 0.5 × 0.25 mm) for constrained VCM designs.

Faster sensor development

TDK Corp. introduced two development tools at Sensors Converge to simplify evaluation of TDK sensors. The InvenSense SensorStage software is an evaluation platform to simplify development and accelerate data analytics for TDK’s SmartMotion inertial measurement units (IMUs) and TMR magnetometers, while SensorGPT uses AI to generate simulated datasets to improve and accelerate development of edge AI IoT devices.

The all-in-one platform SensorStage bridges the gap between simple GUIs and custom test benches, offering advanced visual analytics and automated scripting to help engineers move from setup to insight without manual configuration, TDK said. SensorStage enables evaluation of complex, on-chip algorithms for applications in OIS, wearables, AR/smart glasses, and IoT with a future-proof architecture that supports existing and upcoming high-performance sensors.

The SensorStage platform is paired with the SmartMotion development board. Together, sophisticated on-chip features including machine-learning algorithms, the APEX engine for Gyro Assisted Fusion, motion and event detection, and chip-level power consumption are visualized. This delivers precise calibration and faster time to market for complex designs.

SensorStage is currently available for InvenSense ICM-456xx and ICM-426xx SmartMotion IMUs and will soon be available for additional InvenSense MEMS sensor solutions.

SensorGPT uses generative AI, signal processing, statistical methods, and simulations to create and manage sensor data at scale. Particularly aimed at smart IoT and ambient IoT applications, the AI tool streamlines model development and deployment, reducing time and cost, while enhancing the performance and efficiency of edge AI models and applications, TDK said.

SensorGPT sensor data synthesis trains generative models with limited real-world data to learn underlying patterns and generates synthetic data that mimics real-world data. It reduces the reliance on real-world data through intelligent sensor data synthesis, cutting data-collection efforts from 80% to nearly 10%, according to TDK, which enables faster, more scalable edge AI development.

The AI tool leverages physics-based and mathematical models to simulate and generate synthetic sensor data and uses mathematical and computational techniques to simulate data reflecting the dynamics and characteristics of real sensor outputs, TDK explained.

Other features include data-augmentation techniques that automatically transform existing sensor data into diverse datasets spanning a range of conditions and scenarios, while the assisted annotation streamlines the labeling of training data, which improves the quality for model training.

SensorGPT generates a 90% similarity between synthetic and real-world sensor data. This enables the use of the synthetically generated data for faster edge AI solution prototyping, testing, and deployment. It reduces edge AI model-building time from five-plus months down to a few weeks, according to TDK.

The post Sensors Converge 2026: Smarter and lower-power sensors appeared first on EDN.

Pen plotters used to be very common in the engineering world, as they were economical for “printing” large technical drawings. They’re still around, but digital-only workflows and alternative printing methods have reduced their presence. But Elliot Madsen is an engineering student fascinated by his discipline’s history, so he constructed his own pen plotter using an Arduino^® UNO Q board and parts from an old 3D printer.

A pen plotter is just a machine that moves a pen around, relative to the paper, in the X and Y axes (plus lifting in Z). That’s why they were ideal for technical drawings that tend to be large and composed entirely of lines.

That kind of motion system also closely matches that of an FFF/FDM 3D printer, which is why Madsen was able to build his pen plotter using parts — like stepper motors, aluminum extrusion, and pulleys — from a 3D printer. He chose a CoreXY kinematic setup, with a solenoid-actuated lifter for the pen. (As a bonus, the solenoid provides a nice “clacking” noise when in use.) Madsen then added a clever vacuum table to hold down paper via four 12V fans, eliminating the need for mechanical clamps.

To control it all, Madsen selected the UNO Q. By leveraging the board’s dual-brain architecture, he was able to run the control software on the Linux side and then interface with stepper motor drivers directly through its STM32U585.

After setup, this pen plotter runs based on simple commands from the terminal, which means it can be controlled over SSH. Just tell it to plot with any arguments you like and add the path to the file.

It works great and is especially well-suited to the kinds of technical drawings that were the bread-and-butter of pen plotters for decades.

The post Old 3D printer becomes new Arduino UNO Q-controlled pen plotter appeared first on Arduino Blog.

Resistor networks are a great way to improve the gain accuracy and gain temperature drift of your system compared to designs using discrete resistors. One common motivation for improving gain accuracy and drift is that the initial system accuracy is good enough to skip calibration altogether. A common drawback of resistor networks is that there are a limited number of gain or attenuation options available, unlike discrete designs that can accommodate an essentially unlimited number of gain and attenuations.

This article shows how it’s possible to achieve 340 different gains and attenuations from just 10 resistor network ratios.

Take the case of RES11A, a resistor network that contains two resistor-divider networks (R_G/R_IN) in each package. The device is available in 10 product variants for different resistor ratios, with each variant identified by a suffix. For example, RES11A90 is the 9-to-1 ratio variant (see Figure 1).

You can use it to set gain on an operational amplifier or as an attenuator. The tolerance and drift of the resistors in the divider track closely, yielding significantly better attenuation accuracy and lower temperature drift than discrete resistors at a comparable price. RES11A, for example, has a worst-case tolerance of ±0.05% and temperature drift of ±2ppm/°C.

Figure 1 The above diagram highlights the functional blocks of the RES11A90 resistor network. Source: Texas Instruments

Swapping the input and output provides two different attenuations

The RES11A resistor network has 10 different resistor ratios, so you might think that you can only get 10 different attenuation values for this device. Keep in mind, however, that it’s not possible to swap the input and output of the attenuator, so each network can achieve at least two different attenuations.

Figure 2 shows how RES11A90 operates first as a 0.1 V/V and then a 0.9 V/V attenuator by simply reversing the connections. Thus, you can get at least 20 different attenuations from the 10 unique networks.

Figure 2 Swapping inputs and outputs on RES11A90 yields two different attenuations. Source: Texas Instruments

Combining both halves unlocks even more options

Generally, only one of the resistor pairs is active at a time when using RES11A as either an attenuator or a single-ended amplifier feedback network. But you can place the unused pair in series or parallel with either R_IN or R_G. Since all the resistors in the network were deposited in the same wafer processing step, they all have good ratio matching and drift matching.

Thus, the ratio, and drift accuracy of the combined divider will typically be the same as the individual dividers, although the worst-case ratio accuracy widens to ±0.1% with a ratio drift of ±4ppm/°C. Figure 3 illustrates how placing R_G2 in parallel with R_G1 achieves an attenuation of 0.818 V/V.

Figure 3 Using both halves of RES11A90 helps achieve a unique attenuation. Source: Texas Instruments

10 resistor network ratios, 34 configurations each

Different series and parallel combinations of both halves yield 34 different attenuations. Since there are 10 different variants of the network, the total attenuations possible with RES11A is 340 (34 × 10 = 340). Even accounting for duplicates, there are many unique attenuations. Figure 4 shows all 34 possible configurations.

Figure 4 Here are 34 possible attenuator configurations for the RES11A resistor network. Source: Texas Instruments

Manually sorting through so many options to determine which attenuator configuration meets your requirements isn’t practical. TI’s free Analog Engineer’s Calculator software tool identifies the best RES11A configuration to achieve your target attenuation or gain. Figure 5 illustrates how the calculator can find the resistor configuration for a target attenuation of 0.818 V/V.

Figure 5 The tool determines the RES11A configuration to achieve a 0.818 V/V attenuation. Source: Texas Instruments

Gain applications and compatible devices

While this article focuses on attenuation, RES11A also works well for setting gain on a single-ended or differential amplifier. In the case of a single-ended amplifier, combining both network divider halves results in many different gain values. Figure 6 shows the RES11A gain tool in the Analog Engineer’s Calculator to find different attenuations and gains.

Figure 6 This is how the tool finds gain of 3.5 V/V.

The tool also supports the RES21A and RES31A resistor networks, which share the same ratios as RES11A but scale overall resistance by a factor of 10 and 100, respectively. Thus, you can address your gain or attenuation requirement for RES11A and just substitute RES21A or RES31A if you require a higher overall resistance.

Ten ratio variants. Thirty-four configurations each. Three hundred forty reasons to leave the discrete resistor drawer closed.

Art Kay is applications engineer at Texas Instruments.

Related Content

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• Analog Devices Design Tools: ADIsimRF
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• Why I’m fine with my calculator’s tiny decimal point
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• Choosing and using resistive power splitters and dividers
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• Splitting voltage with purpose: A guide to precision voltage dividers
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The post How many attenuations can you get from 10 resistor networks? appeared first on EDN.

What makes a market success? Is there a Swiss-made sensor inside? Or maybe a wrist strap? What happened to the basics: cost-effective reliable functionality? (And yes, get off my lawn, you kids!).

Back in late March, I detailed my experiences setting up TP-Link’s entry-level Tapo H100 smart IoT hub and wirelessly mating it with a Tapo T315 smart temperature and humidity monitor a few rooms over:

along with, for good measure, a Tapo T300 smart water leak sensor downstairs. The Tapo T315 was effective in several respects: proving that the two DREO humidifiers (one of them also “smart”) were functioning effectively, and that whatever humidity sensing technology was being harnessed in conjunction with my furnaces was not functioning effectively and should be ignored going forward.

Display-optional when the data’s already app-visible?

The Kindle-reminiscent 2.7” e-ink display built into the T315 was convenient for at-a-glance monitoring of both humidity and temperature…that said, truth be told, I can count on the fingers of one hand, without using any of them more than once (and maybe even some of them at all) how many times I’ve looked at it since setting it up. To wit, at the end of that late-March writeup, I noted:

I’ve also got a redundant Tapo H100 smart hub and T300 smart water leak sensor, both sitting on the shelf, queued up for teardown, along with a display-less sibling of the T315 hygrometer, the Tapo T310 Smart Temperature and Humidity Sensor.

The Tapo T300 is still sitting on my teardown pile, although I plan to get to it soon (I promise, barring any out-of-my-control delay factors, of course). The Tapo H100 was dissected toward the end of last month. And today, you get the Tapo T310. I’ll as usual start with outer box shots, as usual accompanied by a 0.75″/19.1 mm diameter U.S. penny for size comparison purposes:

Marketing hype? Reality? A bit of both?

The back panel notes that the sensor is “high-accuracy”. The product page further elaborates that it’s “Swiss-made”. What is this, a watch (analogy)?

We’re releasing version 0.55.0 of the Arduino^® Core on Zephyr today, and it’s a meaningful one. This update resolves one of the most common friction points users have reported, adds support for two widely-used libraries, and brings us noticeably closer to our June target for marking this core stable and ending the BETA program. Concurrently, we’ll begin deprecating the corresponding cores based on mbedOS.

If you’ve been following the beta, this one is worth updating to.

Unified monitor and serial

The single most requested fix in this cycle was simple and reasonable: Serial.println() should just work.

On previous releases, users running the Arduino^® UNO Q board had to be intentional about how they routed output — adding #include and being mindful of target differences between IDE 2 and Arduino^® App Lab. That friction is gone in 0.55.

We’ve reworked how outputs are routed and introduced a transparent alias, so printing to Serial or Monitor now delivers the expected result in both Arduino IDE 2 and Arduino App Lab. No bridge header required. If your existing sketch includes Arduino_RouterBridge.h, it’ll still compile cleanly; it’s just redundant now.

Print to your monitor without thinking about it.

New library support

Real-Time Clock (RTC): Projects running on Zephyr-supported boards can now use a reliable RTC to track time independently of uptime counters. Sync with a network time server, maintain a running clock with full calendar features, and build time-aware applications with confidence.

CAN Bus: The CAN library opens the door to automotive and industrial applications right from your UNO Q. Add a small CAN transceiver to your setup and you have everything you need to prototype automotive dashboards, robotics control systems, or any device network built on the CAN fieldbus standard.

Also in the Zephyr 0.55 release

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• Dynamic Interrupts for UNO Q
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• shiftIn / shiftOut functions for serial data reading and writing on pins
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• Zephyr workqueue support for managing low-priority interrupts\n
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  • Fixes compilation of libraries that hard-require wiring_private.h and pins_arduino.h
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  • Plenty of bug fixes: PWM, WiFi, and more
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Board support

Nicla Vision joins the supported lineup with this release. 

The full compatibility list as of 0.55.0:

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• UNO Q
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• Arduino^® Portenta H7
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• Portenta C33
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• Arduino^® Opta board
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• Arduino^® Giga Display Shield
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• Arduino^® Nano Matter board
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• Nano 33 Bluetooth^® LE
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• Arduino^® Nicla Sense board
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• Nicla Vision
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How to get started

Search for “zephyr” in the Arduino IDE Board Manager, install the 0.55.0 release, and you’re ready to go. Check our full release notes available on GitHub and read our troubleshooting article for more information.

Contribute to the beta program!

This is your opportunity to shape the future of Arduino development! We welcome feedback, bug reports, and contributions to the core. Visit the GitHub Issues page to report bugs or suggest features. Your feedback will play a critical role in refining this integration and unlocking new possibilities for embedded systems.

Visit the Arduino Core-Zephyr GitHub repository today and start exploring this exciting new platform! Thank you for being a part of the Arduino community.

Thank you for being part of this!

Arduino, UNO, Portenta, Opta, Giga, Nano, and Nicla and the Arduino logo are trademarks or registered trademarks of Arduino S.r.l.

The post Arduino Core on Zephyr 0.55: Getting ready for the final mile appeared first on Arduino Blog.

Four fundamental forces of nature—gravity, electromagnetism, strong nuclear force, and weak nuclear force—govern all known physical interactions in the universe. Of these four, gravity is the one with which we are all personally familiar, as we deal with it in our daily routine. Knowing these forces, along with the other defining constants of the International System of Units (SI), form the foundation of much of modern science and engineering (Figure 1).

Figure 1 This wallet card displays the fundamental constants and other physical values that will define a revised international system of units. Source: NIST

A good semi-technical, highly readable overview of the development of metrology, the people who made it happen, and its role in civilization and the industrial and technology revolution is the book “Beyond Measure: The Hidden History of Measurement from Cubits to Quantum Constants” by James Vincent (Figure 2).

Figure 2 This enjoyable book provides great insight into the hard-fought efforts of metrologies over the centuries, even if they were not called that. Source: W. W. Norton

The gravitational constant, informally dubbed “big G”, determines the strength of the attraction between two masses anywhere in the universe. It’s approximately 6.67 x 10^-11 meters³/kilogram-second². It is, of course, associated with Isaac Newton’s brilliant insight and law of universal gravitation, published in 1687, which states that every particle in the universe attracts every other particle with a force directly proportional to the product of their masses and inversely proportional to the square of the distance between them (Figure 3).

Figure 3 We can thank Isaac Newton for this simple equation that quantifies all-pervasive yet mysterious gravity. Source: Wikipedia

This “big G” is distinct from “little g”, which describes the acceleration that an object experiences due to the gravitational pull of a large mass, such as Earth, and it varies from location to location. For instance, the value of little g is approximately 9.8 meters/second² at Earth’s surface but only 1.62 meters/second² on the Moon.

The first implicit measurement is attributed to Henry Cavendish in a 1798 experiment with an accuracy of about 1%, which is impressive considering the year and available tools and technology. Yet, while other fundamental physical constants are known to 6 or more digits of confidence, measurement of this oldest-known force to comparable precision has eluded physicists, and it’s known with confidence only to about 4 digits.

While a better value for G wouldn’t affect the lives of most people or projects, there are some cases for which it would be needed, and it’s also a part of the broader science “quest”.

Why is G so hard to measure? There are three main reasons:

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• Gravity is the weakest of the four fundamental forces of physics; for comparison, it’s approximately 10³⁸ times weaker than the strongest force.
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• The masses used in the experiment must fit inside a relatively small, constrained space of the experimental lab, and small masses generate small gravitational forces.
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• Since gravitational force is inherent by every object, it’s extremely challenging to make sure the force you measure in the laboratory really comes from the intended mass.
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What was the next step?

Trying to determine G to higher accuracy has been an ongoing project for many institutions and researchers. I recently came across a news report from National Institute of Standards and Technology (NIST) site summarizing the 10-year quest led by physicist Stephan Schlamminger to improve that measurement (“NIST Weighs In on the Mystery of the Gravitational Constant”).

His team’s strategy was to painstakingly replicate a precision experiment conducted by the International Bureau of Weights and Measures (BIPM) in Sèvres, France, in 2007, which provides the value of G in use now. To do this, the team not only improved the precision of the physical parts of the experimental setup but also dived deeper to more fully identify sources of error, and then either reduce them or work out ways to have them self-cancel.

The basic arrangement is very simple and begins with a torsion balance similar to the one used by Cavendish (Figure 4). He placed two lead balls on opposite ends of a wooden beam horizontally suspended at its center by a thin wire. Nearby, he positioned two much heavier masses, suspended separately.

Figure 4 The traditional Cavendish experiment for measuring the strength of gravity was a torsion balance with an “optical” readout. Source: NASA

The gravitational attraction between the smaller and heavier masses caused the wooden beam to rotate, twisting the wire until the torque it exerted by counterbalancing the gravitational force. The motion of the wooden beam, measured with a mirror and light pointer, indicated the value of big G.

The Schlamminger team upgraded to eight cylindrical metal masses. Four of the cylinders sat on a rotating carousel, resembling four candlesticks in an old-fashioned chandelier. The other four smaller masses were placed inside the carousel, on a disk suspended by a ribbon of copper-beryllium about the thickness of a human hair.

They then added a modern-day “twist” not available to Cavendish: applying a voltage to electrodes placed alongside each of the inner masses (Figure 5). These voltages created an electrostatic torque that twisted the wire in a direction opposite to the gravitationally induced torque. By carefully setting a voltage that exactly counterbalanced and nulled the gravitational torque, the researchers prevented the torsion balance from rotating. The magnitude of the voltage provided another estimate of big G.

Figure 5 The latest version of the torsion balance is loosely based on the Cavendish design, but adds advanced features, including electrostatic torque nullification. Source: NASA

Of course, the actual unit is larger and much more sophisticated (Figure 6).

Figure 6 The NIST version of the Cavendish torsion balance bears little resemblance in actual implementation. Source: NASA

What’s the result?

The Committee on Data of the International Science Council, or CODATA, issues recommended values of fundamental physical constants. Its recommended numerical value for big G is a four-digit number with a measurement uncertainty of 22 points per million. To put this in perspective, a watch that runs 22 ppm late would measure the year 12 minutes too long.

So, to cut to the chase: How did the team do? Bluntly, not as well as they would like. In fact, their answer differed significantly from the BIPM number—which would be OK if it was “more correct” —but it had greater uncertainty as well. It was 0.0235% lower than the result that the researchers had attempted to replicate and is at odds with the CODATA figure.

I won’t try to summarize the project, as it has so many nuances and details. Fortunately, the published Metrologia paper titled “Redetermination of the gravitational constant with the BIPM torsion balance at NIST” is not a dry, academic-style presentation of the project. Instead, it’s a fascinating, highly readable 30-page recounting of a story that begins with an overview of the history of G measurement, then goes on to review the project step by step, covering the rationales for each step; the improbable, possible, and likely sources of error; the dilemmas they addressed; the qualitative issues as well as the quantitative analysis; and much more.

You could almost say it could be the basis for a scripted TV show or even a movie, perhaps not as dramatic as the 2023 Oppenheimer but still a “grabber.” As a very nice consideration for the readers, the paper begins with a full list of acronyms and abbreviations, which I wish all papers would do. It even includes a group photo of the 40+ team participants.

There’s one other interesting aspect of the project that I have very rarely seen. Schlamminger worried that he might unconsciously skew his measurement so that it agreed with the value of G that researchers found in the French experiment. To satisfy his own meticulous standards, he asked a colleague to scramble the data.

To accomplish this, colleague at NIST’s Mass and Force Group multiplied each Source Mass value by an unknown factor (1 + r) with r ∈ [−1 × 10⁻³, +1 × 10⁻³], stored in a secure envelope to be hidden from Schlamminger until the work was complete. This random offset number for the masses served to “blind” Schlamminger to the actual measurement he was taking.

By employing that strategy, Schlamminger would not know the actual value of big G that his team had measured. The envelope with the secret number was unsealed on a conference stage at the July 2024 Conference on Precision Electromagnetic Measurements (CPEM), and Schlamminger and his team finally found out the somewhat disappointing real results of their work.

Related Content

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• What if Gravitational Constant G Isn’t?
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The post Measuring G: The ultimate metrology challenge? appeared first on EDN.

Batteries eventually die, whether due to excessive recharge cycles, deep-discharge, or other factors. Capacitors, in contrast, often don’t hold charge long enough. What’s an engineer to do?

When the Pentax Q compact digital camera that I told you about last month:

showed up at my front door, I excitedly opened the packaging, tossed the battery on the charger to rejuvenate it, then slotted the battery inside the camera, bayonet-mounted a lens to the body, pressed the power button to turn the Q on, and…was immediately prompted to enter the current time and date, along with the desired format for the latter:

Not a huge surprise, at least at first. The Pentax Q is nearly a decade-and-a-half old at this point, after all. I figured that the camera had been sitting around without a primary battery in it—or maybe that primary battery had just drained—with draining of the backup battery (commonly referred to as the CMOS battery in functionally-equivalent PC settings storage terminology) following in short order.

So, after thoroughly testing the camera to make sure it was otherwise operating properly, I popped the primary battery back out to top it off again, then slotted it back in the camera body and let everything sit overnight to recharge the backup battery.

Drained brains

The next day, I turned the Pentax Q back on and…once again was immediately prompted to enter the current time and date, along with the desired format for the latter. What the heck? I hit Google and learned that mine wasn’t remotely a unique issue. Unsurprisingly, in retrospect, the embedded battery had exceeded its maximum recharge cycle count and/or had experienced deep discharge degradation from which it was unable to recover. CR2032 cells on PCBs are admittedly prone to suffer similar fates:

with one key difference; they’re much easier to access and replace. I trust you’ll resonate with my reluctance to disassemble my photographic antique and attempt similar surgery on it. Yes?

At the end of the day, of course, this is a First World problem, the latest in an admitted long list that I’ve shared with all of you over the years. Time, date, location and directly related settings are the only ones that don’t survive primary-cell separations and drains; all the others (including the all-important user interface language setting, critical for someone who’s fond of Asian-sourced electronics but can’t visually-or-otherwise understand any Asian dialects) are generally stored in nonvolatile memory instead of battery-backed SRAM (because, speaking of cycles, these other settings change comparatively infrequently and are therefore unlikely to hit the max-rewrite cycle count of the EEPROM, flash memory or other technology housing them).

Imperfect workarounds and alternatives

If I could just remember to plug my primary battery-housing camera in to recharge every once in a while, I might also dodge the flaky-backup-battery issue that way…except that the Pentax Q can’t be recharged over its proprietary USB-derived connector. And anyway, I avoid recharging primary batteries in situ whenever possible, in case the cells were to swell and permanently embed themselves in the battery compartment. And speaking of ejecting batteries, I’ve found at least two other hacks:

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• Have a spare fully-charged battery sitting nearby, and pop out and replace the drained battery with it really quickly (the backup battery’s charge storage capability apparently isn’t completely neutered, only severely compromised)
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• Or just hit “cancel” after seeing the initial-settings screen to skip past it…with the obvious downside that subsequently logged date and time info will be (quite) incorrect!
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What about so-called “supercapacitors” (aka, ultracapacitors) as an implementation alternative to conventional backup batteries?

The obvious key advantage here is that they support near-infinite recharge cycle counts. They also have comparatively high output power density (translation: high output current, although this attribute isn’t necessary in the application we’re discussing today) and there’s also no worry about the overheating-induced thermal runaway (translation: heat, smoke, flame) to which batteries are prone to varying degrees depending on implementation-technology specifics.

Nothing’s perfect in real life

Alas, there are also downsides. Although you can, to my previous high output power density comment, drain ‘em really fast, they also drain comparatively fast all by themselves (in weeks, versus months or even years for batteries), even in the absence of a load…which kind of defeats the purpose of using them for long-shelf-life settings-backup purposes, yes? Plus, as the above image suggests, they tend to have comparatively poor storage density. Translation: they’re huge in both linear size and volume in comparison to a comparable battery alternative.

Comparative size isn’t so much of a problem with an available volume-rich application such as a desktop computer or server. In a camera, or even a laptop computer, or any other diminutive device for that matter, it’s more likely to make a supercapacitor a non-starter. Alas, as I alluded to earlier, those same compact form factors are also more likely to be difficult-to-impossible to disassemble in order to do a backup battery swap, so…

Walk into any modern fulfillment center or high‑precision inspection site and the pattern is unmistakable: robots are becoming smarter, more autonomous, and more deeply embedded in daily operations. They navigate cluttered aisles, collaborate with people, and execute tasks that once required years of human experience.

Yet behind the impressive demos and AI‑powered autonomy lies a quieter, more stubborn truth. The frameworks governing how these robots behave, communicate, and integrate with the rest of the factory are still playing catch‑up.

For years, robotics innovation has moved faster than the standards meant to ensure safety, reliability, and interoperability. That was manageable when robots lived in structured, predictable environments. But now that they’re entering aircraft wing boxes, nuclear vessels, medical labs, and public spaces, the gap is no longer sustainable.

The industry is reaching a point where the convergence of ISO/TC 299 and ASME Model‑Based Enterprise (MBE) frameworks is becoming essential. Together, they are laying the foundation for the next decade of automation.

Through my work in robotics and engineering standards, I’ve seen how the absence of a unified digital thread slows down certification, complicates integration, and turns validation into a guessing game. The industry is ready for a shift, and these standards are the mechanism for that shift.

Synergy: Behavior meets mechanical truth

In robotics, reliability is a marriage of autonomous behavior and physical reality. You cannot have one without the other. The relationship is best understood through a simple metaphor: a driver and a map.

ISO/TC 299 is the driver’s manual. It defines how a robot should behave when a human enters its workspace, how collaborative systems maintain predictable safety envelopes, and how mobile fleets negotiate shared space. These behavioral expectations create consistency across vendors and applications, which is critical as multi‑robot systems become the norm.

ASME MBE, particularly ASME Y14.41, is the map. It provides machine-readable geometry, tolerances, and load paths that tell the robot what the world looks like and how its own structure behaves under stress. It is the robot’s mechanical truth, which is the foundation for accurate motion planning, stiffness modeling, and digital twin fidelity.

When these two systems operate independently, problems emerge. A robot may follow every safety rule perfectly, but if it doesn’t understand its own deflection under load, it can still “safely” drill a hole in the wrong place. I’ve seen this disconnect repeatedly in real deployments: behavior and mechanical truth treated as separate concerns, even though they collide on every project.

The future of robotics depends on eliminating this separation.

Standards in action: Solving the validation gap

Consider a high‑precision assembly task inside a Brownfield environment. A long‑reach robot is working in an aircraft hangar where the temperature rises throughout the day. The robot plans its path using a static CAD model, unaware that its arm has expanded by a millimeter due to thermal drift. In a traditional setup, the robot executes the plan anyway, and the error shows up only after inspection and is often too late to avoid rework.

In a standard-integrated environment, the workflow looks very different. The robot pulls its geometry and stiffness information from an ASME Y14.41 model, uses ISO/TC 299 to manage safe behavior when a human enters the cell, and continuously adjusts its trajectory by comparing sensor feedback with its digital thread. The result is a sub‑millimeter accurate operation that remains safe and reliable even as conditions change.

This is not hypothetical. In aerospace and energy applications, thermal drift, compliance, and load‑path uncertainty are among the most common sources of failure. Standards give robots the context they need to correct these issues in real time.

A similar story plays out in dynamic warehouses. Mobile robots constantly encounter shifting pallets, narrowing aisles, and unpredictable human movement. ISO/TC 299 governs how they yield, reroute, and negotiate shared space. ASME MBE ensures that the robot’s internal map reflects real geometry rather than outdated floor plans. When a pallet is slightly misaligned, the robot doesn’t just detect it, it understands how that misalignment affects its own kinematics and load stability. This combination prevents collisions, downtime, and cascading errors that can shut down an entire facility.

The economic advantage: Eliminating the hidden tax

Beyond the engineering benefits, there is a major economic argument for this convergence. Today, companies pay a hidden tax in the form of custom integration. Every robot vendor uses a different data model, forcing end‑users to build expensive bridges between incompatible systems. These one‑off integrations accumulate over time, creating brittle automation ecosystems that are difficult to scale and nearly impossible to maintain.

When ISO governs behavior and ASME governs data, robots become vendor‑agnostic. A new robot can be dropped into an existing digital thread, and it will immediately understand the factory’s geometry, safety rules, and tolerances. Deployment times shrink from months to days. Total cost of ownership drops because automation no longer forms isolated islands that require constant reinvention.

In my experience, the companies that adopt standards early see the benefits almost immediately: fewer integration failures, faster certification cycles, and a more predictable automation roadmap. Standards don’t slow innovation; they accelerate it by removing friction.

The era of deterministic robotics

The last decade of robotics was defined by intelligence in AI, perception, and autonomy. The next decade will be defined by determinism. Robots will need to be predictable, traceable, and grounded in mechanical truth. The convergence of ISO/TC 299 and ASME MBE is pushing the industry toward systems that are not just automated, but self‑aware and self‑correcting.

From what I’ve seen in industry, the organizations that embrace this convergence early will be the ones shaping the next era of automation. As robots expand into more complex and safety‑critical environments, this integrated framework will influence the future of robotics as much as any breakthrough in neural networks.

The companies that act now will define the next generation of automation and the standards that make it possible.

Santosh Yadav is a hardware development engineer at Amazon Robotics and an IEEE Senior Member. His work focuses on the intersection of mechanical reliability and standardized automation frameworks.

Special Section: Smart Factory

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• Rethinking machine vision in industrial automation
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• Smart factory: The rise of PoE in industrial environments
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• Precision lasers boost safety and efficiency in smart factories
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• Tale of 3 sensors operating in smart factory environments
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• From edge AI to physical AI in smart factories: A shift in how machines perceive and act
\n
• Robots: Why AI alone will not deliver the next leap in automation
\n

The post How emerging robotics standards will shape next-gen automation appeared first on EDN.

Automotive silicon design is entering a phase where functional safety, cybersecurity and artificial intelligence (AI) can no longer be treated as separate concerns. In connected, software-defined vehicles, safety outcomes depend not only on protection against random hardware faults, but also on resilience to malicious interference and software vulnerabilities. As a result, many of the decisions that determine system safety are now made at the silicon architecture level.

When ISO 26262 was first published in 2011, it marked a major step forward in structuring functional safety for automotive electronics. But the vehicles being designed today are fundamentally different. Autonomous driving, electrification, AI-based perception, vehicle-to-everything (V2X) connectivity, and centralized compute architectures were not primary considerations at the time.

The core objective remains unchanged: to avoid hazards to people. However, the way this objective is achieved is now deeply tied to how safety is architected into semiconductor devices.

Functional safety is no longer just a system-level concern; it’s a design-time challenge for ASIC and SoC engineers. For many safety-critical functions, whether ISO 26262 targets can be met depends on decisions made in the earliest stages of silicon architecture.

A growing and converging standards landscape

The industry has responded to new challenges by expanding the safety and security framework. ISO 26262:2018 addresses functional safety in road vehicles, while ISO 21448 (SOTIF) considers hazards arising from insufficient or incorrect system behavior. ISO/PAS 8800:2024 begins to address the safety implications of AI-based systems.

Alongside these, ISO/SAE 21434 introduces requirements for automotive cybersecurity, and platform-level schemes such as PSA Certified, while not automotive-specific, are shaping expectations for secure-by-design silicon, roots of trust, and independently evaluated security assurance.

In practice, these frameworks cannot be applied in isolation. Safety and cybersecurity requirements must be interpreted together and traced into silicon architecture, verification strategies, and ultimately the safety case. This convergence increases complexity, but it also reflects the reality of modern automotive systems: safety now depends on both fault tolerance and system integrity.

Figure 1 Functional safety is now a silicon architecture problem that must be addressed alongside cybersecurity and AI from the earliest stages of design. Source: EnSilica

Safety is implemented in silicon

In today’s vehicles, many critical safety mechanisms are implemented directly in hardware. Fault detection, redundancy schemes, error correction, watchdogs, and safe-state control are embedded within ASICs and SoCs. Typical techniques include lockstep CPU architectures for execution monitoring, ECC-protected memories to detect and correct bit errors, and dedicated safety islands that supervise system health and enforce safe-state transitions.

These mechanisms are responsible for ensuring that faults are either corrected or managed in a way that prevents hazardous behavior. Increasingly, they must also be robust against unintended interactions and deliberate manipulation, not just random faults.

This creates a fundamental shift. Functional safety is no longer something that can be added at the system level; it must be designed into silicon architecture from the outset. Decisions around redundancy affect area and cost. Diagnostic features influence power consumption and performance. Detection latency must be balanced against system constraints. These trade-offs are often made before the full system context is completely defined.

At the same time, safety mechanisms are only effective if the system enforcing them remains trustworthy. Ensuring that trust is now a core architectural concern.

Cybersecurity as a determinant of safety

Cybersecurity is no longer adjacent to functional safety—it’s a determinant of it. A system that meets ASIL targets for random faults may still be unsafe if it can be compromised through software, interfaces, or update mechanisms. In connected vehicles, a maliciously induced fault can have the same or greater impact than a hardware failure.

At the silicon level, this translates into requirements for hardware roots of trust, secure boot, run-time integrity checking, and domain isolation. These mechanisms ensure that only authenticated software can control safety-critical functions and that faults or compromises in non-critical domains cannot propagate into safety paths.

From a design perspective, this expands the traditional fault model. In addition to random hardware failures, engineers must now consider adversarial conditions such as fault injection attacks, privilege escalation, and corrupted firmware. Safety architectures must be capable of detecting, containing, and responding to both types of failure.

The limits of the V-model in silicon development

ISO 26262 promotes the V-model as a structured development approach, moving from requirements to implementation and back through verification. While this provides a useful framework, it does not always reflect how safety-critical ASICs are developed in practice.

Silicon design requires early decisions that cut across the V-model structure. Process technology selection, architectural partitioning, testability, and diagnostic coverage must all be considered at a very early stage. These decisions directly influence safety mechanisms and compliance with ASIL requirements.

In reality, ASIC development is highly iterative, moving between architecture, implementation constraints, and verification. The goal is not strict adherence to a linear process, but maintaining traceability, safety intent, and configuration control throughout the design cycle.

Traditional safety analysis is under pressure

Safety analysis methods such as failure modes and effects analysis (FMEA) and fault tree analysis (FTA) remain foundational. However, their application at the ASIC level is becoming increasingly challenging.

Modern automotive SoCs integrate CPUs, AI accelerators, high-speed interfaces, and complex interconnect structures on a single device. Applying traditional analysis techniques at this scale is difficult, often requiring abstraction that introduces uncertainty.

As complexity increases, the question is no longer whether analysis has been performed, but whether it’s sufficient to capture all relevant failure modes, particularly when both accidental faults and adversarial conditions must be considered.

Toward simulation-driven safety verification

To address these challenges, the industry is moving toward more dynamic, simulation-driven approaches. Fault simulation, long used in semiconductor tests, is increasingly applied in a functional safety context.

Instead of simply identifying faults, the focus shifts to system response. When a fault is injected, engineers must determine whether it is detected, whether it is corrected, and whether the system transitions to a safe state within the required time.

This approach integrates safety analysis with design verification and provides more concrete evidence that safety mechanisms operate correctly under realistic conditions. Increasingly, safety metrics such as single-point fault metric (SPFM) and latent fault metric (LFM) can increasingly be supported by fault-injection and simulation-based evidence, alongside analytical safety analysis.

Figure 2 The fault injection verification flow demonstrates how the design contains, detects, and correct faults. Source: EnSilica

AI moves the challenge further into silicon

AI introduces both new risks and new opportunities for functional safety. On the hardware side, AI workloads are implemented in dedicated accelerators within automotive SoCs, further shifting safety responsibility into silicon.

Designers must consider how these accelerators behave under fault conditions and how their outputs are monitored and validated. On the system side, AI raises fundamental challenges around verification. Unlike deterministic logic, AI systems exhibit probabilistic behavior influenced by data and operating conditions.

AI also reinforces the convergence between safety and security. Ensuring the integrity of inputs, models and execution becomes critical, as corrupted data or manipulated models can lead directly to hazardous behavior.

Memory safety and system integrity

One emerging approach to improving robustness is the use of hardware-enforced memory safety. Capability-based architectures, such as CHERI, provide fine-grained control over memory access, reducing the likelihood that software defects or exploitable vulnerabilities propagate into safety-critical behavior.

By mitigating broad classes of memory-corruption vulnerabilities at the hardware level, these techniques contribute to both system integrity and functional safety, particularly in complex software-defined environments.

Designing for long-term security

Automotive systems are expected to operate reliably over long lifetimes, often exceeding a decade. This introduces additional challenges for cybersecurity.

Cryptographic mechanisms that are secure today may not remain so over the lifetime of the vehicle. As a result, there is growing interest in cryptographic agility and support for post-quantum cryptography (PQC), particularly for secure boot, firmware updates, and vehicle communications.

These considerations further reinforce the need to treat security as a foundational aspect of silicon design, rather than a feature added later in the development process.

However, the automotive industry does not need to abandon existing safety standards; instead, it must adapt how they are applied in the context of semiconductor design. Take, for instance, functional safety, which is no longer just a system integration challenge. It’s a silicon architecture problem that must be addressed alongside cybersecurity and AI from the earliest stages of design.

At the silicon level, the distinction between safety and security is becoming increasingly artificial. Safety mechanisms must operate correctly in the presence of both accidental faults and malicious interference. This requires a unified architectural approach, where safety, security and system integrity are designed, verified, and validated together.

As vehicles become more intelligent, connected and autonomous, the role of custom silicon in delivering safe operation will only grow. The standards still matter, but increasingly, it’s silicon that determines whether those standards can be met in practice.

Enrique Martinez-Asensio is functional safety manager at EnSilica. He has more than 35 years of experience in the semiconductor industry, having worked on mixed-signal IC design and technical support and management in several semiconductor companies.

Related Content

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• Automotive Cybersecurity: Attacks Keeps Growing
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• Enabling functional safety in automotive processors
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• Approaches to functional safety in automotive design
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• Automotive processor IP complies with ISO 21434 cybersecurity
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• ISO/SAE 21434: Software certification for automotive cybersecurity
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The post Automotive silicon in the era of AI, functional safety, and cybersecurity appeared first on EDN.

A scenic view, once so charming, has been irretrievably ruined. Will it happen again?

Four astronauts have just circled the Moon and returned safely back to Earth. This (Artemis II, if you’ve been living under a rock for the last month-plus) is quite an achievement, and my saying so is admittedly quite an understatement. But I am disturbed by a thought regarding future lunar plans, and not just those of the United States but of other nations as well.

I have read of the near-future possibility of setting up permanent facilities on the lunar surface. Any such installations will experience day and night cycles, which we see from here as lunar phases. When enveloped in darkness, these lunar facilities will therefore undoubtedly also require artificial light sources. My concern is that these light sources will be visible from Earth. We will no longer have today’s lunar darkness. Our view of the Moon will be permanently despoiled.

Such despoilage has happened before. Consider the following two views of Diamond Point on Oahu in the Hawaiian Islands (Figure 1). The upper image is a screen shot from a movie starring Annette Funicello that dates from 1965 (I think I have that right), while the lower view was taken only a few decades later, in 2020:

\nFigure 1 These views of Diamond Point were taken in 1965 (upper) and 2020 (lower)

The once beautiful view of the natural landscape is now blocked by buildings and piers. The scenic view that was once so charming has been ruined. And sadly, that loss is irretrievable, at least within our lifetimes.

It looks like we are about to do the same thing to our Moon.

John Dunn is an electronics consultant and a graduate of The Polytechnic Institute of Brooklyn (BSEE) and of New York University (MSEE).

Related Content

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• 1st manned Apollo mission launches, October 11, 1968
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• Apollo 11 launches, July 16, 1969
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• Apollo 11 makes 1st manned landing on the Moon, July 20, 1969
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• Apollo 17 lands on moon, December 11, 1972
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The post Despoilage appeared first on EDN.

Bird feeders seem to attract both birds and squirrels in equal measure. But while birds tend to eat just a little when they’re peckish, squirrels are voracious and will happily gobble up all of the seeds — leaving nothing to entice birds. To keep the squirrels at bay, David Groom leveraged the Arduino® UNO Q to build a “bird-only feeder” called BirdFeedR.

BirdFeedR dispenses bird seed on demand, but only when it recognizes a bird. If something else, like a rascally squirrel, tries to get involved, BirdFeedR will simply refuse to do anything. It will log the event as something detected, but it won’t dispense food unless that thing is a bird.

Groom was able to easily pull that off without spending a fortune, thanks to the UNO Q along with a USB webcam. He was even able to take advantage of Arduino® App Lab‘s Detect Objects on Camera example, which is made possible through the Video Object Detection Brick. That works using the FOMO (Faster Objects, More Objects) model from Edge Impulse and performed so well that Groom used it as is. It runs on the SBC (single-board computer) brain of the UNO Q and communicates with the MCU (microcontroller) via the standard Bridge calls that make the UNO Q so powerful.

On the MCU side, the Arduino sketch simply tells the STM32 to sweep a servo motor a handful of times. The servo motor actuates a mechanism to push bird feed out from the hopper and on to a platform where the birds can get to it. 

Groom even made use of the onboard LED matrix to display a big “X” if the thing detected isn’t a bird, or an adorable bird face if the thing detected is a bird. Now he can rest easy, knowing dastardly squirrels aren’t chowing down on the bird seed.

More details on the project can be found in Groom’s Hackster write-up.

The post BirdFeedR is a bird-only feeder that keeps thieving squirrels away appeared first on Arduino Blog.

Documenting a project is just as much work as the project itself. Capturing photos and video, listing parts, and describing each step takes a lot of time — which is why so many people don’t bother. But that documentation is critical if you want to share your work, which is why Kevin McAleer had the genius idea to create a “self-documenting workshop” called Nibsy.

While the details of a project vary dramatically, write-ups, and tutorials tend to follow pretty standard formulas. That includes a list of components, a description of each step, and visuals. Because there is a consistent workflow, it is possible to automate the documentation process. AI makes that automation much more effective, as it can make sense of everything and wrap it up into a presentable package.

McAleer used the dual-brain Arduino® UNO Q to pull off that automation. The STM32 microcontroller detects the start of work through either a button press or sensing current on McAleer’s soldering iron. That tells the Qualcomm Dragonwing QRB2210 processor brain to start recording the environment.

It records two things: audio as McAleer speaks and explains what he’s doing, plus images from an overhead webcam that points down at the desk. McAleer’s spoken explanations give the AI context, including critical information like the names of components and information about the connections he’s making. The explanations, plus image analysis, let the AI determine which image frames to keep for the documentation. All the while, the UNO Q’s onboard LED matrix displays icons representing the system’s status.

The AI in question is Claude’s Sonnet model, which offers a good balance of performance, cost, and capability. That does most of the work of sifting through the recorded data. Then, at the end of a session, Claude’s top-of-the-line Opus models refines that and distills it down into a project log or tutorial, ready to publish to McAleer’s blog.

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A few months ago, UncleStem built a completely functional 7:1 scale Arduino UNO Rev3 development board. That was a big hit, for obvious reasons. But what can you do with an Arduino of that size? The answer is: create a matching 7:1 scale turtle robot for it to control.

This is a great pairing, because turtle robots are often the first big projects that new Arduino users tackle — usually soon after blinking an LED. Just like with the oversized Arduino, UncleStem wanted to honor that tradition with the power of enlargement. 

He started by building a classic example of a normal-sized turtle robot from a kit. That is, of course, controlled by an UNO Rev3. The Arduino turns the two motors through an L298N dual H-bridge driver and avoids obstacles using an ultrasonic sensor. The ultrasonic sensor is on a servo-actuated panning mount, so it can “look around” for the optimal path when it runs into anything. The frame is just a piece of laser-cut transparent acrylic.

With that as a reference, UncleStem began building the scaled-up version. Most of the components are 3D-printed shells that match the mundane originals, but that contain the closest functional matches. For example, the drive motors are 12-24V geared units intended for kids’ ride-on vehicles. The “L298N” hides a pair of high-power 300W drivers suitable for those motors. A laser-cut plywood panel replicates the L298N’s PCB.

UncleStem progressed through all of the components in the same manner. He even made giant jumper cables to connect the components together.

The best part is that the mega turtle robot functions just like the original. It looks around with its ultrasonic sensor to find ways around obstacles, which is really fun to watch. 

The post Massive 7:1 scale Arduino UNO gets matching 7:1 scale turtle robot appeared first on Arduino Blog.

The evolution of automotive safety is moving from the exterior to the interior, opening a new frontier: in-cabin sensing. Its emergence marks a shift from passive vehicle shells to active systems capable of detecting and safeguarding occupants. However, implementing radar-based in-cabin sensing presents multifaceted engineering challenges, including privacy considerations, real-time data processing, and functional safety, all under strict regulatory umbrella.

Radar has become the preferred modality for in-cabin applications, offering privacy by design, effectiveness through interior materials, and immunity to lighting conditions. Crucially, it detects micro-motions such as breathing and heartbeat.

Why in-cabin sensing Is becoming mandatory

In-cabin sensing includes systems that monitor driver behavior, track occupant presence, detect vital signs, and recognize gestures within the vehicle. With the push for in-cabin sensing in response to global demand for higher safety standards, in-cabin sensing is moving from a “nice-to-have” to a “must-have” feature set.

Figure 1 In-cabin sensing is increasingly becoming a must-have feature in modern vehicles. Source: Cadence Design Systems

Tragic incidents involving children left in hot cars and drowsy driving have prompted regulators and safety organizations to act, making in-cabin sensing essential for top safety ratings.

Regulatory bodies are shifting focus from external crash prevention to interior safety measures. Programs like Euro NCAP’s Child Presence Detection (CPD), effective in 2025, and the U.S. Hot Cars Act highlight the importance of interior monitoring to prevent child fatalities and assess driver alertness. While traditional camera systems face privacy and lighting challenges, radar technology, especially 60 GHz frequency-modulated continuous wave (FMCW) radar, offers a superior, privacy-preserving solution for next-generation intelligent cockpits.

Why radar is emerging as a preferred modality

Radar technology offers a unique set of capabilities that make it the optimal choice for the complex environment of a vehicle cabin. Unlike cameras, which can be obstructed by poor lighting or raise privacy concerns, radar provides robust, non-intrusive sensing and offers many benefits.

Privacy by design

In an era where data privacy is paramount, radar offers a distinct advantage. It does not capture detailed visual images of faces or bodies. Instead, it detects presence and movement through point clouds. This allows the system to monitor occupants effectively without recording sensitive personal visual data, making it far more acceptable to privacy-conscious consumers.

Seeing the unseen (non-line-of-sight)

One of the most profound advantages of radar is its ability to penetrate materials. A camera cannot see a child covered by a blanket or sleeping in a rear-facing car seat obstructed by the driver’s seat. Radar, however, can detect the micro-movements of breathing or a heartbeat through clothing, blankets, and even seat materials (excluding steel). This non-line-of-sight (NLOS) capability is crucial for reliable CPD.

Environmental robustness

Radar is immune to lighting conditions. It functions just as effectively in pitch-black darkness as it does in blinding sunlight, ensuring continuous protection day or night. Furthermore, its performance remains robust despite temperature fluctuations, humidity, or vibrations—common factors in the automotive environment.

Why 60-GHz FMCW radar specifically?

As OEMs and Tier 1 manufacturers evaluate their platform choices, the FMCW-versus-ultra-wideband (UWB) debate often arises. While UWB has had success in consumer electronics and certain automotive access systems, FMCW radar aligns more naturally with the requirements of high-volume automotive in-cabin sensing deployments.

FMCW offers a lower cost structure, simpler integration path, and superior feature scalability. It supports multi-use sensing—from occupant monitoring and CPD to vital signs and gesture recognition—all within a unified signal-processing pipeline.

FMCW also avoids security challenges such as relay or “man-in-the-middle” vulnerabilities sometimes associated with UWB applications. Taken together, these factors make FMCW at 60 GHz the “sweet spot” for OEMs targeting a multi-model rollout between 2026 and 2030.

Challenges in engineering the intelligent cabin

Implementing radar-based in-cabin sensing is not without its challenges. It represents a multifaceted engineering hurdle that requires the convergence of precision sensors, high-speed signal processing, and functional safety compliance.

The processing challenge

Detecting the subtle rise and fall of a sleeping infant’s chest amidst the noise of a moving vehicle requires immense computational precision. The radar processing pipeline involves complex stages, including the Range FFT (Fast Fourier Transform), the Doppler FFT, and sophisticated clutter-removal algorithms.

Statistics show 99.9% accuracy in CPD using radar. To achieve this high accuracy, engineers must employ advanced digital signal processing (DSP) technologies. Solutions like the Tensilica Vision 110 DSP are designed specifically for these high-performance, low-power requirements.

Figure 2 Here is a radar processing pipeline for a child presence detection use case. Source: Cadence Design Systems

By offloading complex mathematical operations such as 8-bit and 16-bit MACs to a dedicated DSP, automotive designers can achieve the required frame rates (around 50 FPS) while adhering to strict power and thermal constraints.

Integrating AI and machine learning

The future of in-cabin sensing lies in the fusion of traditional signal processing with machine learning (ML). While traditional algorithms excel at determining distance and speed, ML is essential for classification. Is the object a bag of groceries or a child? Is the driver blinking due to fatigue or just natural movement? Object segmentation is performed by running AI models on a radar dataset.

Advanced radar architectures now support AI-driven classification, allowing the system to learn and adapt. This capability enables features like gesture recognition for touchless control of infotainment systems, adding a layer of comfort and convenience alongside safety.

Applications beyond safety: Comfort and autonomy

While safety mandates are the primary driver, the potential of radar-based in-cabin sensing extends well beyond user experience and autonomous operation.

Health and wellbeing

The sensitivity of 60-GHz radar enables vital sign monitoring. Systems can continuously track heart and breathing rates without physical contact.

Figure 3 This radar processing pipeline serves vital signs monitoring (HR/BR). Source: Cadence Design Systems

In the event of a medical emergency, the vehicle could detect the driver’s distress and autonomously pull over or alert emergency services.

Enhancing autonomy

As we progress toward L3 and L4 autonomy, the vehicle needs to know not just where it is, but also how its occupants are doing. In a handover scenario where the car needs the driver to take control, the in-cabin sensing system must verify that the driver is alert, present, and ready. Radar provides this verification reliably, acting as a core intelligence layer that builds trust in machine-driven environments.

Operational efficiency

For emerging mobility models like robotaxis, radar offers practical benefits. It can detect the number of passengers for billing purposes, ensure no objects are left behind, and even automatically manage trunk operation.

The silicon imperative: Efficient DSPs and AI at the edge

In-cabin radar workloads demand a unique blend of high-throughput DSP operations and compact neural-inference capabilities. Traditional MCUs lack the parallelism required for FFT-heavy pipelines, while dedicated NPUs often exceed cost and power envelopes for cabin modules. A new category of radar-optimized DSPs has emerged as the right balance—programmable, efficient, and capable of supporting both classical signal processing and radar-trained neural networks.

These processors must deliver high MAC throughput, robust SIMD capabilities, and efficient memory architecture while operating within tight thermal constraints. Their flexibility enables quick algorithmic iteration, which is essential in a domain where radar datasets continue to expand across body sizes, seating layouts, and vehicle architectures.

The road ahead

As vehicles advance toward autonomous operation, in-cabin sensing will become a core intelligence layer that predicts occupant needs, safeguards their well-being, and builds trust in machine-driven environments. The integration of radar into the vehicle cabin is redefining what it means to be safe on the road.

For automotive OEMs and Tier 1 suppliers, mastering scalable, radar-based sensing architecture is no longer optional, but is a determinant of future leadership. By leveraging powerful DSP platforms and embracing the unique capabilities of FMCW radar, engineers are not just meeting regulations; they are designing a safer, more intuitive driving experience.

The guardians are no longer just on the bumper; they are inside, ensuring that every journey ends as safely as it began.

Amit Kumar is director of Automotive Product Management and Marketing for Tensilica DSPs at Cadence. He has more than 20 years of design experience in the semiconductor and IP segments. Amit has held product marketing, application engineering, business development, and key strategic management roles with a specialization in automotive ADAS/AD and robotics applications.

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The post The guardians inside: How radar is redefining in-cabin sensing appeared first on EDN.

The current robotics narrative is heavily weighted toward artificial intelligence (AI). The prevailing assumption is that more parameters, larger models, and better reinforcement learning pipelines will eventually grant machines human like dexterity. This belief has shaped research agendas, funding priorities, and public expectations.

However, for engineers designing hardware that must survive millions of high-velocity cycles at companies like Amazon Robotics, a different truth is apparent. In the lab, the focus is on the brain, but on the production floor, robots fail for mechanical reasons far more often than algorithmic ones.

In high duty cycle environments, the primary drivers of unplanned downtime are wear, compliance, thermal drift, misalignment, and mechanical fatigue. These are not failures of perception or planning. No amount of neural network tuning can compensate for a linkage that deflects under load or an end effector that cannot maintain repeatability. As the industry continues to chase AI-centric solutions, it risks overlooking the fundamental engineering disciplines that determine whether a robot succeeds in the physical world.

The robotics community is at a crossroads. The last decade has delivered extraordinary advances in machine learning, but the physical reliability of robotic systems has not kept pace. The result is a widening gap between what robots can demonstrate in controlled environments and what they can sustain in real production settings.

Closing this gap requires a shift in mindset. The next leap in robotics will not come from larger models or more training data. It will come from better mechanisms, better actuation, and better physical architectures.

The reliability gap

The industry has spent a decade optimizing the brain while neglecting the body. This imbalance has created what can be described as the reliability gap. As a technical judge for MassChallenge and for university capstone programs at Worcester Polytechnic Institute and Boston University, I have observed a recurring pattern.

Startups and student teams often present systems that segment objects perfectly in simulation, classify scenes with remarkable accuracy, and demonstrate impressive reinforcement learning policies. Yet when these systems are deployed in the physical world, they fail after only a few hours of operation.

The reason is straightforward. AI amplifies a robot’s capability, but the mechanism defines the physical boundary. If a kinematic chain introduces unpredictable hysteresis, software cannot compensate its way to a reliable solution. If a transmission loses stiffness under load, no amount of perception accuracy will restore positional integrity. If an end effector cannot generate stable contact forces, even the most advanced grasping model will fail.

The robotics industry must acknowledge a practical reality. Software and AI are essential, but they cannot overcome fundamental mechanical limitations. The most successful robotic systems in history have not been those with the most advanced algorithms, but those with the most deterministic mechanical behavior. Reliability is not an emergent property of software. It’s engineered into the physical system from the beginning.

Determinism and the voyager philosophy

True industrial progress requires a return to mechanical rigor, specifically a focus on what can be called deterministic mechatronics. This philosophy suggests that the most successful robotic systems are those engineered for passive stability, predictable behavior, and graceful failure. A useful analogy comes from deep space engineering.

Voyager 1, launched nearly half a century ago, remains operational in one of the harshest environments imaginable. NASA has occasionally uploaded new command sequences, performed resets, and adjusted subsystems to extend its life. These interventions succeed because the underlying mechanical and electrical systems were engineered for extreme reliability. The spacecraft’s longevity is not the result of software alone or hardware alone, but the synergy between robust physical design and intelligent control.

Industrial robotics should adopt this same mindset. The next leap in automation will come from kinematic architectures that reduce inertia, precision transmissions that maintain sub-millimeter accuracy under load, and actuation strategies that prioritize physical determinism. The goal is not to diminish the role of AI, but to ensure that AI is built on a stable mechanical foundation.

A deterministic mechanism reduces the burden on perception and control. It narrows the solution space. It transforms a difficult control problem into a manageable one. When the physical system behaves predictably, the software becomes simpler, more robust, and more efficient.

Case study: The apparel challenge

The manipulation of non-rigid materials, such as apparel, provides a clear example of this principle. Handling folded fabric is traditionally viewed as an AI problem. The common assumption is that complex pose estimation, dense depth reconstruction, and advanced vision models are required to manage the noise introduced by folds and wrinkles.

However, breakthroughs in this field, including those protected under U.S. Patents 11268223 and 11939714, demonstrate that the solution is primarily mechanical. By designing a compliant yet deterministic gripping architecture, the physics of the material can be used to the machine’s advantage.

When the kinematic chain is engineered to minimize shear forces, the physical interaction becomes predictable. When the mechanism constrains the degrees of freedom in a way that aligns with the material’s natural behavior, the need for complex perception is reduced.

In these systems, AI still plays a meaningful role. It identifies features, guides sequencing, and handles variability. But it succeeds because the underlying mechanism provides a stable substrate. The machine does the heavy lifting so the software can remain efficient. This balanced approach is what the industry needs. Instead of using software to compensate for mechanical unpredictability, the mechanism is engineered to reduce the burden on software.

This approach scales. It is robust. It is repeatable. And it is the foundation on which industrial grade automation must be built.

A new hierarchy of design

To unlock the next stage of automation, the engineering community must rebalance its priorities. The hierarchy of design must shift.

First, the industry must invest in mechanism research and development with the same intensity it brings to AI. For every dollar spent on perception, equal resources should be allocated to transmissions, linkages, and end effectors. Mechanisms are not a solved problem. They are the frontier that will determine the next decade of progress.

Second, the industry must build reliability-first architectures. Robots should be engineered with the longevity of aerospace systems, not the lifecycle of consumer electronics. This requires a shift in mindset. Reliability is not a feature. It’s a design philosophy.

Third, the industry must foster a new breed of roboticists. The next generation of engineers must be equally proficient in kinematics and PyTorch, equally comfortable with finite element analysis and neural network training and equally invested in mechanical determinism and algorithmic efficiency. The future belongs to engineers who can bridge the physical and digital domains.

Finally, the industry must resist the temptation to chase demos. The goal is not to produce systems that perform well in controlled environments, but systems that operate reliably in the real world. The measure of success is not a viral video, but a robot that performs millions of cycles without failure.

The next decade of robotics

Artificial intelligence is an extraordinary amplifier, but it’s not the foundation of robotics. Intelligence can only be as effective as the physical vessel through which it acts. The next decade of robotics will be defined by the engineers who recognize that mechanisms, transmissions, and physical architectures are not secondary considerations. They are the core of the system.

The future of robotics does not belong to the AI-first approach or the mechanism-first approach. It belongs to the integration of both into a single, reliable, and deterministic system. When the body and the brain evolve together, automation will finally achieve the scale, reliability, and capability that the industry has been pursuing for years.

This is the mechanism-centric future of robotics. And it’s long overdue.

Santosh Yadav is senior mechanical engineer and robotics researcher at ASME MBE Standards Committee.

Special Section: Smart Factory

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• Rethinking machine vision in industrial automation
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• Smart factory: The rise of PoE in industrial environments
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• Precision lasers boost safety and efficiency in smart factories
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• Tale of 3 sensors operating in smart factory environments
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• From edge AI to physical AI in smart factories: A shift in how machines perceive and act
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The post Robots: Why AI alone will not deliver the next leap in automation appeared first on EDN.

Simple analog circuits manage multi-PSU powerup and shutdown sequences.

In projects containing digital and/or analog circuits, multiple power supplies are used, generally 5V DC for digital circuits and 15V DC for analog circuits. Some projects also use 24V or 48V DC as the third power supply. In many cases, these power supplies need to be switched on in sequence, commonly 5V DC first and 15V DC next, with a time delay in-between. Subsequently switching them off necessitates implementing this sequence in reverse, i.e., first in/last out (FILO) in total, with 15 VDC first and 5V DC next and again with a time delay in-between.

Wow the engineering world with your unique design: Design Ideas Submission Guide

In MCU-based projects, this sequencing can be achieved through an appropriate software routine. For non-MCU projects, conversely, Figure 1 shows a simple analog circuit that accomplishes this function for two power supplies:

\nFigure 1 A simple analog circuit controls the powerup and shutdown sequencing of two power supplies. 

How does this circuit work? Fundamentally, it employs the charging and discharging of capacitor C1 to achieve both power supply sequencing and the interim time delay. SW1 is a two-pole ON/OFF switch. When it is pressed, 5V is applied first through one pole and then through the second pole. 0V applied to the base of Q5 creates an open circuit. Next, C1 gets charged through R8.

The voltage at C1 rises per the following formula:

 v= V(1-e^-t/T)

Here V=5V and T=R8xC1. R9, R10 and R11 serve as voltage dividers to set the references for comparators U1B and U1A.

When the rising voltage v crosses through the first reference voltage set by R11, the U1B output goes HIGH, saturating Q1. This transition causes Q2 to conduct and connect to the 5V output.  Capacitor voltage v, further rising, next crosses through the second reference voltage set by R10+R11. Now the U1A output goes HIGH, saturating Q4. Q3 now also conducts, with 15V also made available at the output.

For switching off, although SW1 is now opened, 5V initially continues to be fed to the output through the ongoing conduction of Q2. The base of Q5 goes HIGH, causing it to saturate. C1 resultantly starts discharging through R12. The voltage v at C1 decreases as per the formula:

v=Ve^-t/T

When this voltage goes below the reference voltage 2 set as the input to U1A, its output goes LOW. Q4 and Q3 now turn OFF. Hence, the 15V DC output is switched OFF first. As the capacitor voltage further decreases with the passing of time, it goes below the reference 1 set at the input of U1B. Its output now also goes LOW, turning Q1 and Q2 OFF. The 5V output, switched OFF last, implements the desired FILO sequence.

Notably, this design doesn’t employ a constantly power-consuming watchdog circuit. For different time delays, accordingly select R9, R10 and R11 to set the desired reference voltages. High current power supplies can be handled by using suitable MOS switches (Q2 and Q3).

You can expand this concept to cover any number of power supplies to be operated in a time-delay FILO sequence. For example, Figure 2 shows a derived analog circuit, this time supporting three power supplies:

\nFigure 2 An analog circuit derived from the previous one controls the powerup and shutdown sequencing of three power supplies, with the concept further as-needed expandable.

The video below demonstrates the operation of Figure 2’s circuit with three power supplies in a FILO sequence.

Jayapal Ramalingam has over three decades of experience in designing electronics systems for power & process industries and is presently a freelance automation consultant.

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The post Single switch controls sequential operation of multiple power supplies appeared first on EDN.

When structures bend, stretch, or compress, engineers need a way to translate that invisible mechanical stress into measurable data. Strain gauges do exactly that—tiny sensors that convert deformation into electrical signals with remarkable precision.

From monitoring bridges and aircraft wings to ensuring the reliability of everyday electronics, strain gauges are the quiet workhorses that make stress visible, quantifiable, and actionable.

How resistance reveals stress

At the heart of every strain gauge lies a deceptively simple principle: when a conductor or semiconductor is stretched, its electrical resistance changes. Engineers harness this effect by arranging strain gauges in a Wheatstone bridge circuit, amplifying tiny resistance shifts into measurable voltage signals.

It’s a clever translation—microscopic deformations become clear electrical outputs. Narratively, this is where the magic happens: the silent stress within a bridge girder or aircraft fuselage suddenly speaks in numbers, allowing designers to predict failures, validate models, and ensure safety long before cracks appear.

Stress signals in the real world

A strain gauge is the sensing element itself, while a strain gauge sensor is the complete packaged device that integrates the gauge with wiring, housing, and often signal conditioning for practical measurement. That distinction becomes critical when sensors are deployed in demanding environments.

Consider aerospace wing testing: engineers attach arrays of strain gauges across critical points of an aircraft wing. As the wing flexes under simulated flight loads, each gauge’s resistance shifts, feeding signals into a monitoring system. The sensor assemblies ensure those delicate gauges survive vibration, temperature swings, and handling. This is where theory meets reality—tiny resistance changes become the data that validates aerodynamic models, ensures passenger safety, and drives innovation in lighter, stronger aircraft designs.

Civil infrastructure offers another compelling example. Bridges endure constant stress from traffic, wind, and temperature cycles. Embedded strain gauge sensors provide early warnings of fatigue, helping engineers schedule maintenance before cracks or failures occur. In this narrative, strain gauges are not just measuring stress, they are safeguarding lives and economies by keeping critical structures resilient and reliable.

A technical note: A strain gauge directly measures strain (physical deformation). From this measurement, we determine the internal stress—the intensity of the forces resisting that deformation—using the material’s known stiffness.

Strain gauge vs. load cell vs. FSR

Since this post is focused on strain gauges, here is a quick distinction. A strain gauge measures material deformation as a resistance change, forming the basis of precise force sensing. A load cell builds on this, packaging strain gauges into a calibrated transducer for accurate weight and force measurement in industry. By contrast, a force-sensing resistor (FSR) is a low-cost sensor whose resistance shifts with pressure—handy for relative force detection in consumer and robotic applications, but far less precise.

Figure 1 Strain gauges and force-sensing resistors convert mechanical input into changes in electrical resistance, yet their responses vary in linearity, sensitivity, and application scope. Source: Author

So, in essence, when designers and engineers need to measure force, two of the most widely used technologies are force sensing resistors and strain gauges. Both convert mechanical input into changes in electrical resistance, yet their principles, accuracy, and applications differ greatly.

A force sensing resistor is a thin, flexible, polymer-based sensor whose resistance decreases as pressure is applied to its surface. A strain gauge, on the other hand, is made of fine metallic foil or wire arranged in a grid and bonded to a stable substrate. Rather than detecting direct pressure, it measures strain—the deformation of the material it is attached to. As the material stretches or compresses, the strain gauge deforms as well, producing a slight change in resistance. This change is typically measured using a Wheatstone bridge circuit for precise results.

Similarly, load cells build upon strain gauge technology by integrating one or more gauges into a mechanical structure that translates applied force into measurable strain. This makes load cells highly accurate and reliable devices for quantifying weight and force in industrial, commercial, and scientific applications.

Figure 2 A compact button-type load cell, based on strain-gauge technology, delivers compression measurements in space-limited applications. Source: ATO

Wheatstone bridge configurations for precision strain measurement

In practical applications, strain measurements typically involve very small changes rather than large strain values. Detecting these minute variations requires precise measurement of small resistance changes. A Wheatstone bridge circuit (WBC) is widely used for this purpose, as it translates subtle resistance shifts into measurable voltage outputs.

A standard Wheatstone bridge consists of four equal resistors arranged in a square. An excitation voltage is applied across one diagonal, while the output voltage is measured across the other. In its balanced state, the bridge produces zero output voltage. For strain measurement, one or more resistors are replaced with active strain gauges, whose resistance varies in response to external forces acting on the structure.

To achieve higher sensitivity and improved accuracy, different Wheatstone bridge configurations are employed: quarter-bridge, half-bridge, and full-bridge. In a quarter-bridge, a single resistor is replaced with a strain gauge. A half-bridge uses two strain gauges, while a full bridge replaces all four resistors. These configurations not only enhance measurement precision but also help compensate for temperature effects, making them essential in modern strain gauge instrumentation.

Figure 3 Diagram illustrates a quarter Wheatstone bridge, where one resistor is replaced by the strain gauge. Source: Author

Selecting the right strain gauge

Selecting the right strain gauge requires balancing geometry, resistance, and environmental compatibility to achieve accurate measurements while controlling installation costs. Options range from simple linear gauges for uniaxial stress fields to rosette configurations—rectangular, delta, or tee—for analyzing complex or unknown stress directions, and bridge arrangements for enhanced sensitivity and thermal compensation.

The choice of grid orientation and gauge length must align with the material’s homogeneity and the stress distribution being measured. Equally important are electrical parameters such as the nominal resistance, which determines compatibility with the measurement circuitry, and self-temperature compensation, which offsets thermal effects to maintain accuracy and improve signal-to-noise ratios under fluctuating operating conditions.

Environmental and installation considerations in strain measurement

As stated before, strain gauges are inherently sensitive to temperature variations, and changes in temperature can alter their electrical resistance. If not properly compensated or controlled, this effect can introduce significant measurement errors.

Beyond temperature, external factors such as humidity, moisture, vibration, and electromagnetic interference can also degrade performance and accuracy. Appropriate protective measures—such as encapsulation, shielding, and environmental sealing—are therefore essential to ensure reliable operation.

Equally important is the bonding of the strain gauge to the surface of the substrate. A strong, uniform bond ensures that the gauge accurately follows the strain of the underlying material. Achieving this can be challenging when working with dissimilar materials or irregular surfaces. Poor bonding may result in signal instability or inaccurate readings, undermining the integrity of the measurement system.

Practical strain gauge systems: Bridges, amps, and test kits

In a Wheatstone bridge, the strain gauge serves as the variable resistor whose resistance shifts under mechanical deformation, producing a differential voltage proportional to strain. Because this resistance change is extremely small—often less than 0.1% of the gauge’s nominal value—the bridge must be energized with a stable excitation source and paired with an amplifier stage to extract the signal from noise.

For basic designs, a differential amplifier can provide initial signal conditioning, but for precision applications, an instrumentation amplifier (INA) is preferred due to its superior common-mode rejection and high input impedance.

Keep in mind that the bridge configuration depends on accuracy requirements: a quarter-bridge offers simplicity, a half-bridge adds temperature compensation, and a full-bridge delivers maximum sensitivity. The choice of amplifier ensures the bridge’s delicate balance is preserved while enabling reliable strain measurement.

Today’s compact strain gauge amplifiers make the entire measurement workflow far more straightforward by integrating multiple critical functions into a single, easy-to-use module. Not only do they provide clean signal gain and low-noise performance, but many also feature built-in excitation voltage sources, eliminating the need for external supplies.

They often include automatic bridge balancing to correct minor mismatches in resistance, ensuring the Wheatstone bridge remains stable and accurate. With high input impedance, filtering options, and sometimes digital outputs, these amplifiers reduce design complexity, accelerate setup, and deliver reliable strain data. For engineers, this means less time spent on circuit design and more confidence in capturing precise measurements across lab and field applications.

Figure 4 Compact strain gauge amplifier modules meet growing demand for industrial strain measurements, where miniature size and easy setup are essential. Source: Transmission Dynamics

Moreover, when it comes to strain gauge test kits, they offer a practical, all-in-one pathway for converting mechanical stress into precise electrical signals. These kits typically include gauges with standard resistances (120 Ω or 350 Ω), along with surface preparation tools, adhesives for secure bonding, and protective coatings to ensure durability in challenging environments.

Once integrated into a Wheatstone bridge, the kit enables detection of minute resistance changes defined by the gauge factor, directly linking strain to output voltage. Thus, strain gauge kits simplify what would otherwise be a complex measurement workflow, making them indispensable across fields ranging from structural health monitoring and aerospace stress testing to advanced biomechanics.

That wraps up today’s dive into strain gauges. From foil to semiconductors, the evolution continues—and now it’s your turn to engineer what comes next.

T. K. Hareendran is a self-taught electronics enthusiast with a strong passion for innovative circuit design and hands-on technology. He develops both experimental and practical electronic projects, documenting and sharing his work to support fellow tinkerers and learners. Beyond the workbench, he dedicates time to technical writing and hardware evaluations to contribute meaningfully to the maker community.

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The post Strain gauges: Turning stress into signal appeared first on EDN.

Diminutive? Definitely. Flexible? Indubitably. Safety-cognizant? Thankfully…unless you activate “FORCE” mode, that is (hopefully intentionally).

A bit more than a year ago, within a blog post that talked about (potentially) resurrecting dead lead-acid batteries, I noted that I’d recently added additional members to my battery-charger stable. Historically, I’d relied on a legacy-design DieHard model, one of the two which, loudly humming and dubiously still working, I subsequently turned into a teardown target:

The others were all newer designs, solid-state (vs transformer-based) and both more flexible in their supported battery voltages and technologies and more feature-rich. Specifically, today I’ll be focusing on the NOCO Genius 1, a 1A trickle charge two examples of which I’d acquired on promo discount from Amazon’s Warehouse-now-Resale) site intending to tear one of ‘em down:

Walking while chewing gum

I’d teased the feature set a year-plus back, then focusing (given the overall writeup topic slant) on its battery-rejuvenating chops. Here’s the fuller feature-set list, requoted from the Amazon product page (from which, by the way, I’d acquired today’s dissection victim for only $20.12, ~1/3 off the current brand-new $29.95 price tag, which in and of itself also isn’t bad, or if you prefer, half off the $39.95 MSRP):

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• MEET THE GENIUS 1 — Similar to our G750, just better. It’s 35% smaller and delivers over 35% more power. It’s the all-in-one charging solution – battery charger, battery maintainer, trickle charger, plus desulfator.
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• DO MORE WITH GENIUS — Designed for 6-volt and 12-volt lead-acid (AGM, Gel, SLA, VRLA) and lithium-ion (LiFePO4) batteries, including flooded, maintenance-free, deep-cycle, marine and powersport batteries.
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• ENJOY PRECISION CHARGING — An integrated thermal sensor dynamically adjusts the charge based on ambient temperature, preventing overcharging in hot weather and undercharging in cold, ensuring optimal battery performance.
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• CHARGE DEAD BATTERIES — Charge batteries from as low as 1 volt, or use Force Mode to manually charge completely dead batteries down to zero volts. Perfect for recovering deeply discharged or neglected batteries.
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• BEYOND MAINTENANCE — Keep your battery fully charged without worrying about overcharging. Our smart charger constantly monitors the battery, allowing you to leave it connected safely – indefinitely – for worry-free maintenance.
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• RESTORE YOUR BATTERY — Precision pulse charging automatically detects and reverses battery sulfation and acid stratification, restoring your battery’s health for improved performance and extended lifespan.
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• COMPATIBLE — Charges and maintains all types of vehicles, including cars, automobiles, motorcycles, mopeds, lawn mowers, ATVs, UTVs, tractors, trucks, SUVs, RVs, campers, trailers, boats, PWCs, jet skis, classic cars, and more.
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• WHAT’S IN THE BOX — Includes a 1A charger, a direct wall plug-in, 110-inch DC cable with battery clamps, and integrated eyelet terminals, and 3-year warranty. Proudly designed in the USA.
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It’s pretty tiny (that’s the aforementioned G750 behind it in the following photo, by the way); 3.62in (92mm) high, 2.32in (59mm) wide and 1.26in (32mm) deep, and weighing only 0.77lb (0.35kg):

And the manufacturer was even thoughtful enough to include a preparatory teardown diagram on the website product page:

(Simple) assembly required

Let’s see how close reality comes to matching that conceptual image, shall we? This charger arrived absent its packaging, so what you’ll see first (as usual accompanied by a 0.75″/19.1 mm diameter U.S. penny for size comparison purposes) is the other, ~$3 more, charger’s box:

Wonder what happened to the original “tab” for retail-display hanging purposes?

Opening up the box…

you’ll find user guide (also accessible here as a multi-language PDF, plus the product spec sheet) and promo literature, plus, in this particular case, the aforementioned formerly-MIA tab:

along with, of course, today’s two-part patient:

the base unit:

and the remainder of the cabling, including the battery terminal clamps:

Here’s the male-and-female connector pair that mates ‘em:

And what’s that lump partway down the “remainder of the cabling” span?

It’s a (user-replaceable, which is nice) fuse, as at least some of you may have already guessed. 2A is, IMHO at least, a reasonable choice considering the device’s 1A-max output specs:

Before putting the “remainder of the cabling” to the side, here’s a closeup of those “integrated eyelets” mentioned earlier in the bulletized feature list:

And this stock shot shows how to make ‘em usable:

A high degree of integration

Now for the base unit. Before diving inside, here are some real-life overview shots to augment the earlier stock ones:

You’ve probably already noticed the ultrasonic welds around the outside, holding the halves together. Regular readers may already recall that they’re a longstanding bane of mine. This time, since it was convenient to do so and I was under no delusions that the charger would be salvageable/reusable post-teardown anyway, I took a hacksaw to ‘em in conjunction with a vise:

Here’s what the inside of the back half looks like, revealing AC prong connections to the PCB:

And speaking of which, here’s our first look at the PCB itself, specifically the backside:

Nothing here is particularly surprising, nor is the broader fact that DC conversion circuitry dominates the landscape, given the physical proximity to the AC source. Most notable, probably, is the diminutive size of the two transformers, explained in part (but only in part) by this particular unit’s trickle-current characteristics. For the rest of the (hint: solid-state) story, we’ll need to see the other side of the PCB. No better time than the present:

Taking (which?) temperature

With the normally-restraining screws now removed:

and in the process of lifting the PCB out of the remaining chassis half:

I happened to notice, down by the DC cable exit point, two more wires alongside a NTC1 notation on the PCB:

I’m (fairly confidently) assuming that they reference a negative temperature coefficient (NTC) thermistor. My initial reaction, and one that in retrospect I admittedly clung to far too long, was that it somehow was used to ascertain if the battery itself was overheating, a situation which would compel the charger to “cut the juice”. Problem being, though, that there are only two wires (DC positive and negative) in the cable running from the main unit to the battery, so the thermistor would end up being nowhere near the battery itself (PDF).

In grasping at straws, I surmised that perhaps the battery temperature was being indirectly determined by the transferred temperature of the connected cabling, which admittedly seemed increasingly silly the more I thought about it. But then I re-read the device specs prior to sitting down to write and realized that what the thermistor was actually measuring was (probably) just the ambient environmental temperature. “An integrated thermal sensor dynamically adjusts the charge based on ambient temperature, preventing overcharging in hot weather and undercharging in cold, ensuring optimal battery performance.” Yeah, that’s it. Ahem.

Onward. Interesting PCB topside two-level sandwich, eh?

And speaking of which:

here’s the inside of the front half of the chassis:

And the PCB topside itself:

The largest IC, the one with the white dot on it and located at lower right on the top (of the two-PCB sandwich) mini-PCB, is the “brains” of the operation, an ABOV Semiconductor A96G148GR 8-bit 8051-class microcontroller with integrated flash memory. On the other (top) end, toward the center, is the multi-function toggle switch, which puts the charger in various operating modes, surrounded by a ring of LEDs, including two more toward the bottom. And to its far left is the multi-pin connector that mates the mini-PCB with its larger sibling below it.

I almost stopped at this point, clinging to the delusion that maybe I’d glue everything back together again in fully-functional form. But curiosity-while-writing eventually got the better of me (and anyway, that was a silly idea), so I rotated the assembly by 90° so the PCB markings could be read right-side-up and let ‘er rip:

Ok, now I’m done!

A (potentially fatal?) forcing function

In closing, let’s revisit that just-referenced multi-function toggle switch, specifically in the context of the “unless you activate “FORCE” mode (hopefully intentionally), that is” comment in this article’s subtitle. Quoting from the user guide:

Here’s the ominous bit:

Force Mode. [Press & Hold for 5 seconds]
\nForce mode allow the charger to manually begin charging when the connected battery’s voltage is too low to be detected. If battery voltage is too low for the charger to detect, press and hold the mode button for 5 seconds to activate Force Mode, then select the appropriate mode. All available modes will flash. Once a charge mode is selected, the Charge Mode LED and Charge LED will alternate between each other, indicating Force Mode is active. After five (5) minutes the charger will return to the normal charge operation and low voltage detection will be reactivated.

 CAUTION. USE THIS MODE WITH EXTREME CARE. FORCE MODE DISABLES SAFETY FEATURES AND LIVE POWER IS PRESENT AT THE CONNECTORS. ENSURE ALL CONNECTIONS ARE MADE PRIOR TO ENTERING FORCE MODE, AND DO NOT TOUCH CONNECTIONS TOGETHER. RISK OF SPARKS, FIRE, EXPLOSION, PROPERTY DAMAGE, INJURY, AND DEATH.

The entire quote, notably the all-caps portion, was 100% original, by the way, not “enhanced” in any way by editing from yours truly (explaining, among other things, the “creative” grammar in spots). Reminds you of Jason Hemphill’s “hack” that I highlighted back in mid-March, doesn’t it?

Death. I’ll just leave that for you to ponder as you wish. Memento Mori, my friends. And with that pleasant thought Embedded systems and online entertainment platforms certainly share more design principles than many might expect. From real-time processing to user experience, both fields rely on efficiency, reliability and responsive interaction.

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Modern digital experiences are very much built on foundations that extend far beyond the screen. Embedded systems, found in everyday devices, operate on sound principles of precision, timing and efficiency. Interestingly, these same principles are increasingly visible in lots of online entertainment platforms. As interactive digital environments continue to really evolve, the overlap between engineering disciplines and entertainment design becomes much more apparent, particularly in very fast-growing sectors such as online casino gaming and sports engagement platforms.

How Real-Time Processing Shapes Both Hardware and Gaming Platforms

Real-time processing is very much a cornerstone of embedded systems engineering. Devices must respond instantly to inputs, often within strict timing constraints, to function correctly. This same expectation of immediacy is now absolutely central to digital entertainment platforms.

In environments such as online casino zambia, users expect very smooth, uninterrupted gameplay where actions are reflected instantly on screen. Whether interacting with games or navigating platform features, responsiveness is essential for maintaining engagement.

The ability to process inputs quickly and deliver immediate feedback ensures a seamless experience. Just as embedded systems rely on precise timing to function, modern entertainment platforms depend on low-latency performance to keep users engaged and satisfied. 

The Role of Efficiency in Embedded Systems and Online Entertainment Design

Efficiency is certainly a defining characteristic of embedded systems, where limited resources must be managed very carefully to achieve optimal performance. This principle has clear parallels in digital entertainment platforms, where speed and resource optimization are key to delivering high-quality user experiences.

Platforms such as online casino zambia demonstrate how efficient system design enhances gameplay. By streamlining processes and minimizing unnecessary delays, these platforms ensure that lots of users can access games quickly and consistently.

Efficiency also extends to user interface design, where clarity and simplicity reduce users’ cognitive load. In both embedded systems and online entertainment, efficient design leads to smoother operation and improved overall satisfaction.

User Interaction Principles Shared Across Engineering and Digital Gaming

User interaction is a critical consideration in both embedded systems and online entertainment platforms. In engineering, devices must respond predictably to user inputs, ensuring reliability and ease of use. Similarly, digital gaming platforms must provide intuitive and responsive interfaces.

In the context of online casino zambia, user interaction design plays a central role in shaping the overall experience. Clear controls, logical navigation and responsive feedback help create an environment where users feel in control and engaged.

This shared emphasis on interaction design highlights the importance of understanding user behavior. Whether designing a microcontroller interface or a gaming platform, the goal remains the same: to create systems that are easy to use and highly responsive.

Reliability and Performance as Core Design Priorities in Both Fields

Reliability is essential in embedded systems, where even minor failures can have significant consequences. These systems are often required to operate continuously and consistently over long periods. This same expectation of reliability is increasingly important in online entertainment platforms.

For platforms like online casino zambia, consistent performance is crucial for maintaining user trust and engagement. Players expect games to function smoothly without interruptions or delays. Reliable system architecture ensures that this expectation is met.

Performance also plays a key role in user satisfaction. Fast response times, stable connections and consistent gameplay contribute to a positive experience. In both embedded systems and digital entertainment, reliability and performance are closely linked and equally important.

Translating System-Level Thinking into Seamless Online Experiences

System-level thinking involves understanding how individual components interact within a larger system. In embedded engineering, this approach ensures that hardware and software work together efficiently. In online entertainment, a similar perspective is used to design cohesive user experiences.

Platforms such as online casino zambia benefit from this approach by integrating different elements, such as game logic, user interfaces and backend processes, into a unified system. This integration ensures that users experience smooth transitions and consistent performance across the platform.

By applying system-level thinking, developers can identify potential bottlenecks and optimize overall functionality. This leads to more stable and enjoyable experiences for users.

Shared Foundations Driving Digital Innovation

The overlap between embedded systems and online entertainment highlights a broader trend in digital innovation. Both fields rely on precision, efficiency and responsiveness to deliver effective experiences.

In the case of online casino zambia, these principles translate into platforms that are fast, reliable and engaging. Users benefit from systems designed with the same discipline and attention to detail as those used in engineering applications. User expectations will only continue to grow in this space. 

As digital platforms continue to evolve, the influence of embedded systems thinking will remain evident. The focus on performance, interaction and reliability ensures that both industries continue to advance in parallel, shaping the future of interactive technology and entertainment.

Doing business across borders feels risky and confusing. Different tax rules, new cultures, and strict reporting can drain your time and money. You might worry about missing a rule, facing a penalty, or paying more tax than you should. That fear is common. A Scottsdale certified public accountant can guide you through international business and taxation with clear steps. You gain someone who understands foreign tax rules, treaties, and reporting demands.

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You also gain support that protects you from costly errors. This blog shows how CPAs advise on structure, pricing, reporting, and risk. It explains how to set up operations, move money, and stay compliant with both U.S. and foreign laws. It also shows when to ask for help and what questions to ask. You can take calm, informed steps instead of guessing.

Why you need help with cross border taxes

International business brings three hard problems. You face different tax laws in each country. You must track where you earn income. You must report that income to each tax office on time.

Tax rules change often. So do trade rules and reporting systems. You may not see the change until you receive a notice or a bill. That shock hits your bank account and your peace of mind.

A CPA trained in international work keeps track of these shifts. You gain early warning. You also gain clear options instead of panic.

How CPAs help you choose the right structure

The way you set up your business affects how much tax you pay and where you pay it. It also affects your risk if something goes wrong.

Common choices include:

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• Branch office in a foreign country
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• Subsidiary company owned by a U.S. parent
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• Joint venture with a local partner
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A CPA compares these paths using simple numbers. You see how each choice affects income tax, sales tax, payroll, and reporting. You also see how each choice affects your family if you own the business.

Key topics CPAs review with international clients

You can expect a CPA to walk through three core topics.

1. Where your income is taxed

First, you must know where your income is sourced. Some countries tax income earned inside their borders. Others tax worldwide income for residents and citizens. The U.S. taxes citizens and residents on worldwide income. It also offers credits and treaty relief.

The IRS explains basic rules for U.S. persons with foreign income at the Foreign Tax Credit page on IRS.gov. A CPA uses these rules to reduce double tax while keeping you compliant.

2. How tax treaties protect you

Many countries sign tax treaties with the U.S. These treaties can lower withholding tax on interest, dividends, and royalties. They can also help decide which country taxes certain income first.

A CPA reads treaty rules and translates them into clear steps. You learn when you can claim a lower rate and what forms you must give to customers or banks.

3. How to meet foreign reporting rules

International business often triggers special reports. These can include reports of foreign bank accounts, foreign companies you own, and payments to foreign partners.

U.S. persons with foreign financial accounts often must file an FBAR through the Financial Crimes Enforcement Network. A CPA helps you track which reports apply to you and when they are due.

Common issues CPAs watch for

International work often leads to the same painful mistakes. A CPA tries to stop these before they hit you.

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• Registering for tax in the wrong country
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• Missing foreign payroll duties for local staff
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• Using prices between related companies that tax offices may question
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• Leaving profit in high tax locations instead of planning ahead
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• Forgetting that currency swings change real profit
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A CPA sets up a simple calendar for returns and payments. You then build tax steps into your daily work instead of rushing at the last minute.

Sample comparison of cross border choices

The table below shows a simple example. It compares three ways a U.S. owner might sell to customers in another country. The numbers are sample ranges, not advice. Actual rates differ by country and by treaty.

A CPA walks through a table like this with your own numbers. You then choose a path with clear eyes.

Questions to ask your CPA

You gain more value when you ask direct questions. Useful questions include:

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• Which countries do you see as high risk for small U.S. businesses
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• How do tax treaties affect my sales or services
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• Which foreign reports could apply to me this year
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• What records should I keep for each country
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• How should I pay myself from foreign profit
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Each answer should lead to a short written plan. You can then share that plan with your spouse, partner, or staff.

How to work with a CPA as your business grows

Your first step may be simple. You might start with one foreign customer or one small contract. You still gain from an early talk with a CPA.

As you grow, you can schedule three types of help.

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• Planning before you sign new foreign contracts
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• Checkups during the year when rules change
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• Year-end reviews for all countries where you file
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Each stage keeps you ahead of trouble. You spend less time with tax offices and more time with your customers and your family.

Taking your next step with confidence

International business does not need to feel like a maze. You can use expert help to cut through noise and fear. A CPA who understands cross-border rules turns vague stress into clear tasks.

You protect your savings. You protect your staff. You also protect your sleep. With steady guidance and honest planning, you can grow across borders without losing control of your tax life.

AI video generation may be impressive on a technical level, but typing out a prompt doesn’t exactly feel like creative work. Interaction designer Hun Han wondered how he could make that more of a collaborative experience and that led him to develop something pretty incredible: the Hush toy box.

Hush is a small, enclosed lightbox for photography. Users pose inanimate objects — action figures, clay models, plants, and whatever else they can think of — inside the box, then close the lid. After that, the magic happens: Hush snaps a photo of the scene inside the box and feeds it as a prompt to a video generation AI.

The result is often fantastic, as AI models are now at a point where they do a very good job of generating and rendering realistic video. And in this case, that realistic video incorporates the real-world items in the box. Imagine your LEGO minifigs battling a clay dragon that you sculpted. That is exactly the kind of video Hush can produce and you get to be part of the creative process by deciding what to put in the box and how to pose those things within the scene. You also get control over day versus night and the simulated weather in the scene.

Kling v2.5 Turbo does the heavy lifting of video generation and a PC connects to that via the Replicate AI. The physical controls, including the weather selection dial and the Hall sensor that detects lid closure, connect to the PC through an Arduino. That board also controls the LED strips that illuminate Hush’s interior. The PC snaps a photo of the scene through OpenCV and a webcam. Finally, the rendered video results display on a repurposed iPhone 6, which is visible through a peep hole on the top of the box. 

When it comes to whimsy and entertainment, this might just be the best use of AI that we’ve come across.

The post This toy box does something incredible with AI-generated video appeared first on Arduino Blog.

Most embedded projects don’t stay simple for long. You start with a microcontroller (MCU), reading sensors and controlling outputs. Then you add connectivity, maybe a user interface, maybe even AI. At that point, a single MCU starts to feel limiting. So you introduce a Linux-based system. Now you have flexibility – but also a new layer of complexity: two processors, two toolchains, and a growing amount of glue code just to keep everything in sync.

You want the flexibility of Linux. You need the precision of real-time control. The Arduino^® UNO Q board is designed to bring these two worlds together and make this friction a thing of the past.

A dual-brain architecture gives you the best of two worlds

UNO Q combines two distinct processing environments on a single board.

A Linux-capable microprocessor (MPU) handles high-level workloads such as networking, AI inference, and application logic. Alongside it, a microcontroller manages real-time I/O, deterministic timing, and direct hardware interaction. This separation is intentional.

The MPU runs tasks that benefit from an operating system: multitasking, connectivity stacks, and model execution. The MCU handles tasks where timing and reliability are critical: reading sensors, generating signals, and controlling actuators.

Instead of forcing one processor to do everything, each side does what it’s best at – and the magic happens when the two “talk” to each other through the UNO Q bridge mechanism. 

In practice, this means your Python code can interact directly with hardware-level events handled by the microcontroller (such as a button press, change in temperature, movement, etc.), and your MCU can react to high-level decisions made on the Linux side (e.g. updating a web interface, logging data, or triggering an AI-driven response). Without complex setup, you’re working within a single, coordinated architecture.

Arduino^® App Lab offers a unified application model

The dual-brain architecture enables a different coding experience – so the real shift is not just in the hardware, but in how you develop for it.

With Arduino App Lab, the MPU and MCU are exposed as parts of a single application. 

Arduino App Lab provides developers with a unified, single-console environment. This centralized environment eliminates the need to switch between separate terminals or tools to monitor the two distinct environments. Within this consolidated interface, developers can monitor the logging output from both the primary application processor and the real-time microcontroller in parallel, offering a complete, time-correlated view of the entire system’s execution flow.

From a developer perspective, this removes the need to manually manage communication or synchronization between two separate systems.

The best part? If you want to see how Arduino App Lab is working behind the scenes, the Github repo contains all the source code, no secrets here! If you’re curious, just check it out here.

Arduino App Lab AI workflows bridge data insight and real-world action

Edge AI often becomes complex at the integration stage. Running a model is one thing, but connecting it to real-world signals, managing timing, and triggering actions reliably is where things usually break down.

This is exactly where the dual-brain architecture of the UNO Q changes the game. By combining an MPU running Linux with an MCU handling real-time control, you can naturally split AI workflows: the MPU takes care of model execution, orchestration, and the MCU takes the role of the king of deterministic land. 

It’s not just about running AI, it’s about making it fit and work reliably inside a real system.

Arduino App Lab acts as the bridge between these two worlds, enabling seamless data exchange and coordinated execution across the MPU and MCU. With the integration of Edge Impulse, the path from model training to deployment becomes much more direct. You can move from data collection to inference without reworking your entire stack.

Now you can build and deploy custom models in a unified flow: start from the Arduino App Lab “Train New Model,” move to Edge Impulse for training and validation, and deploy back to Arduino App Lab – ready to run across the dual-brain system, from insight to action.

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You can even switch between different models with a simple click of the mouse!

If you want to explore the full workflow step by step, you can dive deeper into the dedicated article on training and deploying AI models in App Lab, as well as the overview of the expanding UNO Q ecosystem.

From architecture to applications

This dual-brain approach is not just theoretical – you can already see it in action across different types of projects.

From installing widely available tools like Node-RED to vision-based inspection systems, image processing can run on the Linux side while the microcontroller handles precise triggering and control. This allows you to process complex visual data without sacrificing timing accuracy. You can even process images and short videos with text prompts to generate descriptions or answers, like in this project where local LLMs and VLMs run on UNO Q.

In energy monitoring and smart sensing applications – like this accident response system that leverages physical AI – the MCU continuously samples real-world signals, while the MPU aggregates data, runs analytics, and exposes results through services or dashboards.

Three reasons, one simpler way to build

When you put it all together, UNO Q makes building complex systems simpler for three clear reasons.

First, a single, coordinated setup makes your builds more straightforward and efficient. You have two different brains, each one doing what it’s best at.

Second, the unified application model with Arduino App Lab turns two processors into one coherent development experience. You write, monitor, and debug everything from a single environment – no more switching between terminals, no different hardware for different tasks, no more glue code just to keep the two sides talking.

Third, AI workflows actually fit the system. With Edge Impulse, Qualcomm^® AI hub, Hugging Face that can be integrated into the flow, you can go from data collection to a deployed model without rebuilding your stack along the way. The microprocessor runs the inference, the microcontroller handles the signals, and Arduino App Lab keeps them all together using code and Bricks – so edge AI stops being an integration headache and starts being just another part of your application.

Flexibility of Linux, precision of real-time control, and a development ecosystem that is able to handle every side of your next project without you having to jump around between platforms: it’s all in a single board, designed to make building simpler from day one.

Qualcomm branded products are products of Qualcomm Technologies, Inc. and/or its subsidiaries. Arduino and UNO are trademarks or registered trademarks of Arduino S.r.l.

The post One board, two brains? Three ways a dual architecture board makes building simpler appeared first on Arduino Blog.

We’re bringing the maker community behind the scenes with a new live format: Built with Arduino, a candid conversation between our own Andrea Richetta (Senior Product Manager) from Arduino (for Qualcomm Europe) and Rafik from Kamitronix, the creator behind a smart mirror project built entirely on the Arduino^® UNO Q board.

No polished demos, no scripted walkthrough. Just an honest, back-and-forth discussion about what it’s actually like to prototype with the UNO Q ecosystem: Bricks, Modulino, App Lab, and all.

Over 40 minutes, we’ll dig into the real architectural choices every UNO Q developer faces: what belongs on the Linux side, what belongs in the real-time MCU, and how the latest updates from Arduino^® App Lab reduce the friction in between. The final 20 minutes will be open for audience questions.

Three live quizzes will keep the session interactive. Come ready to participate: May 13th @ 4PM CET.

Arduino and UNO and the Arduino logo are trademarks or registered trademarks of Arduino S.r.l.

The post Real talk: building with Arduino UNO Q appeared first on Arduino Blog.

After-school workshops run by curious, driven students is where some of the most exciting engineering happens in the Arduino community! One of the most compelling examples of this is FermiLabs, the innovation hub at secondary school IIS “E. Fermi – R. Guttuso” in Giarre, Sicily, offering students afternoon lab sessions in robotics, automation, and experimental physics. The results speak for themselves: FermiLabs teams have earned multiple podium positions at RoboCupJunior Europe, one of the most demanding student robotics competitions in the world.

RoboCupJunior Rescue, in particular, challenges teams to design, build, and program fully autonomous robots capable of navigating disaster scenarios – from following lines across obstacle-laden terrain to exploring multi-level mazes and assisting simulated victims. For the 2026 season, two FermiLabs teams are pushing the limits of what student-built robots can do, with Arduino at the core of both machines.

Team Tachyons: solving the maze with Arduino GIGA R1 WiFi

The RoboCupJunior Rescue Maze requires a robot to autonomously explore a complex, multi-level labyrinth, identify victims, and deploy rescue kits with precision. The 2026 rulebook raised the bar significantly with the introduction of “cognitive targets” – five concentric colored circles that robots must decode in real-time to classify victim types. This shift from simple colored squares to dense visual patterns demands a substantial leap in processing power and sensor integration.

Team Tachyons – who showcased their work during Arduino Days 2026 and are led by YouTuber and TEDx speaker Etto Fins – met that challenge by centering their robot on the Arduino GIGA R1 WiFi, leveraging the board’s ability to handle complex, multi-threaded tasks with the reliability and low latency that competitive robotics demands.

The robot’s intelligence lives in a custom-designed Arduino shield that acts as its central nervous system. Four dedicated stepper motor drivers deliver sub-millimeter positioning accuracy, while a six-axis IMU (Inertial Measurement Unit), fused with data from six ToF (Time-of-Flight) distance sensors, feeds a PID control loop that keeps the robot precisely centered within each tile – even on ramps and uneven terrain. On top of all this, the software builds a live 3D matrix to map the labyrinth in real-time, allowing the robot to backtrack and optimize its path autonomously.

The mechanical design is equally thoughtful. Custom silicone wheels, molded in-house with an airless structure, maximize traction while minimizing weight and absorbing shocks. The rescue kit deployment mechanism uses a compliant mechanism and twin springs to fire rescue cubelets at high velocity – and the kits themselves are engineered with the lowest possible coefficient of restitution, so they drop dead in place when they reach a victim rather than bouncing away.

After a successful showing at the regional selections in Catania, Team Tachyons placed second in the Italian Nationals with a new and improved model based on UNO Q 4GB boards… winning the chance to fly to Incheon, South Korea to compete with the best 3,000 robotics students in the world.

Team Yellow Radiators: vision-first line following with Arduino UNO Q

The Rescue Line challenge tasks a fully autonomous robot with following a black line across a modular arena of tiles, overcoming obstacles, debris, and varying terrain – ultimately locating and rescuing simulated victims before navigating to an extraction zone. Speed, reliability, and real-time visual processing are everything.

Team Yellow Radiators chose to abandon traditional line-following sensors entirely in favor of a vision-first architecture built around Arduino UNO Q. Rather than running high-level logic and low-level motor control on separate boards, this allowed them to unify both on a single platform. 

A Python layer running OpenCV processes real-time camera data to identify the line and read intersection markers, while the Arduino side simultaneously handles the high-frequency motor control loop and sensor integration. A custom communication bridge between the Python vision layer and the Arduino language hardware layer makes this seamless two-brain operation possible.

For the competition, the team built a custom web control panel that transforms how the robot is calibrated on-site. Via a local Wi-Fi network, team members can view live camera buffers, toggle between different image masks to debug line detection in real-time, and adjust color calibration or sensor thresholds wirelessly using on-screen sliders – no code re-upload required. The dashboard even allows direct remote function calls to the Arduino core, so specific subsystems like the rescue kit grabber can be tested manually. In the variable lighting conditions of a competition arena, this kind of live debugging capability is a genuine competitive advantage.

On the AI side, the team deployed a custom-trained YOLO object detection model using the NCNN runtime, optimized for the UNO Q Arm-based Qualcomm Technologies’ SoC. Their next milestone: enabling GPU passthrough to leverage Vulkan acceleration on the onboard Qualcomm Adreno GPU, further reducing inference latency. Development has been eased significantly by the full Debian OS running on the board, letting the team work directly from VS Code via Remote Development – a proper professional workflow on a compact edge device.

From Sicily to the world championship

Both projects illustrate something FermiLabs has made a habit of demonstrating: that with the right tools, a secondary school team can engineer solutions that rival professional-grade systems. Arduino’s role in both robots isn’t incidental – it’s the platform that makes rapid iteration, hardware control, and connectivity available to students who want to build things that actually work under pressure. 

After multiple successes at the national level in Catania in April, FermiLabs is now gearing up to take two teams to the RoboCupJunior European Championships in Vienna, and two more to the RoboCup Federation Junior World Championships in South Korea. Follow fermilabs.it on LinkedIn to see their progress, or check out their call for partners to find out how you can support them.

Qualcomm branded products are products of Qualcomm Technologies, Inc. and/or its subsidiaries. Arduino, GIGA R1, and UNO are trademarks or registered trademarks of Arduino S.r.l.

The post How FermiLabs builds championship-level robots with Arduino appeared first on Arduino Blog.

Have you ever met a person with an exceptionally neat, tidy, and well-decorated office? Everything is intentional, from the furniture finishes to the potted plants. Even the trash can needs to fit the aesthetic. That’s why Akashdeep Singh of The Wrench YouTube channel designed this fancy 3D-printed dustbin for his new workshop that features a very cool motion-activated iris mechanism. 

This is a small dustbin perfect for putting on a desk. Not only does it look awesome with cassette futurist aesthetics, but it is also functional. Wave your hand over the top and the camera aperture-like iris mechanism will open up for a moment, so you can toss your garbage in. A few seconds later, it will close, keeping smells contained and unsightly refuse out of view. Finally, the body of the dustbin attaches to the base with magnets, so getting access to empty the bin is quick and easy.

That iris magic happens thanks to a pretty simple gear ring mechanism actuated by a small hobby servo motor. That servo motor operates under the control of an Arduino Nano board, which tells the servo to spin when it sees motion through an ultrasonic sensor. To avoid external wires, power comes from an 18650 lithium battery with a voltage booster to get clean 5V to the Arduino and servo motor. A custom PCB designed by Singh ties those components together in a compact package.

All of the mechanical parts to build this dustbin are 3D-printable. If you want to do that yourself, you can find the necessary 3D files and Arduino sketch over on Cults3D.

The post This futuristic-looking dustbin features a motion-activated iris mechanism appeared first on Arduino Blog.

Vishay has released 16 single and dual FRED Pt ultrafast rectifiers in low-profile DFN6546A packages with wettable flanks. The 200-V devices occupy a 6.5×4.6-mm footprint with a typical height of 0.88 mm. Rated from 6 A to 15 A, they offer a 10% lower profile and 50% higher current than comparable 200-V SMPC (TO-227A) devices.

The rectifiers are designed for high-frequency power conversion and protection in automotive, industrial, and consumer systems, including EV powertrains, ADAS, industrial automation, and telecom equipment. Automotive variants are AEC-Q101 qualified.

For these applications, the rectifiers feature low reverse leakage current and operate over a wide temperature range from −55 °C to +175 °C. A low forward voltage drop of 0.75 V, combined with fast reverse recovery time and low reverse recovery charge, reduces power losses and improves efficiency.

The DFN6546A package’s wettable flanks enable automatic optical inspection (AOI), eliminating the need for X-ray inspection and supporting automated assembly. The devices are MSL 1 qualified per J-STD-020, with a maximum peak reflow temperature of 260 °C.

Samples and production quantities of the single and dual FRED Pt ultrafast rectifiers are available now, with lead times of eight weeks.

Vishay Intertechnology 

The post Rectifiers combine low profile and high current appeared first on EDN.

Rohm’s ML7670/ML7671 wireless charging chipset provides NFC charging for compact wearables such as smart rings and fitness trackers. Operating in the 13.56-MHz band, NFC charging enables antenna miniaturization for ultra-compact devices. Following the 1-W ML7660/ML7661 chipset, the ML7670/ML7671 is optimized for even smaller wearable designs.

The chipset comprises the ML7670 receiver and ML7671 transmitter and supports wireless power transfer up to 250 mW. Peripheral components, including switching MOSFETs used to power the charging IC, are integrated. ROHM states that the 2.28×2.56×0.48-mm receiver IC reaches 45% power-transfer efficiency at 250 mW output, where it is optimized for compact wearable designs.

Rohm says the 45% power-transfer efficiency is enabled by tailored coil matching, rectifier circuitry, and reduced switching losses. Firmware for wireless power delivery is embedded in the IC, eliminating the need for a host MCU and reducing board space.

The NFC Forum WLC 2.0-compliant chipset is in mass production and is used in the Soxai Ring 2.

ML7670 product page 

ML7671 product page

Rohm Semiconductor

The post Rohm shrinks NFC charging for wearables appeared first on EDN.

ADI’s ADAA245x series of A²B 2.0 Automotive Audio Bus transceivers delivers 4× higher bus bandwidth (98.3 Mbps full-duplex) than A²B 1.0 devices. Now in production, the transceivers handle up to 119 upstream and downstream audio channels for advanced automotive audio systems, enabling high-definition audio transport across ECU networks.

The ADAA2457 supports Ethernet data tunneling via an Open Alliance SPI (OASPI) interface. All ADAA245x devices are compatible with existing A²B 1.0 cable and connector infrastructure and enable A²B 1.0 branching via device-specific I²S, I²C, and SPI interfaces. The ADAA2455 operates as a sub-node transceiver, while the ADAA2456 and ADAA2457 can be configured as main or sub-nodes.

According to ADI, the transceivers achieve up to 30% system cost reduction through increased functional integration and reduced external circuitry and component count. They also provide low, deterministic latency of 62 µs and are built for straightforward integration.

Learn more about A²B 2.0 and individual transceivers here.

Analog Devices

The post Transceivers boost in-vehicle audio bandwidth appeared first on EDN.

Portable power units have both instantaneous-output and run-time limits, of course, but this situation seems a bit ridiculous. Or, then again, maybe not. But how to tell?

Last December, a few hours after the “kickoff” of our high wind-induced multi-day power outage “adventure”, I had the bright (if I do say so myself) idea to try hooking up our portable power stations (plus extended batteries in two of the three cases):

to the refrigerator-plus-freezer combo in the kitchen, along with both its combo fridge-plus-freezer companion and a standalone chest freezer out in the garage. The weather outside, therefore also the temperature in the garage, was chilly, so I wasn’t terribly worried about anything spoiling in either of those latter two units. Then again, I didn’t know how long the outage would last, and I had three supplemental power solutions at my disposal, so…

Part 1 of this mini-series about PCIe 7.0 fundamentals explained ordering rules and the distinction between relaxed ordering and ID-based ordering. Part 2 elaborates why PCIe 7.0 bandwidth alone isn’t enough and how UIO addresses legacy ordering limitations in this version of high-speed serial interface specification.

As noted earlier, PCIe 7.0 doubles raw link bandwidth compared to PCIe 6.0, increasing full‑duplex throughput from 256 GB/s to 512 GB/s on an x16 link by raising the signaling rate to 128 GT/s in flit mode. However, raw bandwidth does not directly translate into sustained throughput in AI factories.

Large‑scale training and inference systems generate traffic patterns such as GPU collective operations, sharded parameter broadcasts, gradient reductions, and streaming access to disaggregated accelerator and memory resources. These patterns include many independent data streams that cross the PCIe fabric concurrently and continuously.

The legacy ordering model inherited from earlier PCIe generations, including strict ordering, relaxed ordering, and ID‑based ordering, was designed around a producer-consumer abstraction in which ordering conveys semantic meaning to software. Relaxed ordering and ID-based ordering loosen this model selectively.

Relaxed ordering allows certain transactions to bypass global ordering constraints, while still participating in fabric‑enforced ordering rules. ID-based ordering further scopes ordering guarantees to a requester or execution context, preserving program order within that scope. In both cases, the PCIe fabric requires tracking and enforcement of ordering relationships to ensure correctness.

However, fabric‑enforced ordering introduces head‑of‑the-line blocking, increases buffering pressure, and restricts the ability of switches and endpoints to exploit parallel paths. This is particularly the case for multi‑path and non‑tree topologies common in modern AI systems. These effects reduce effective link utilization even though physical bandwidth is available, making it difficult for highly parallel AI workloads to keep PCIe 7.0 links continuously busy.

Addressing legacy ordering limitations with UIO

The unordered I/O (UIO) engineering change notice (ECN) was introduced in the PCIe 6.1 specification and included in PCIe 7.0 to address the specific limitation noted above. UIO introduces a wire-level semantic that shifts producer-consumer ordering responsibility from the fabric to the endpoints. The UIO ECN declares that ordering may be irrelevant for certain traffic classes.

For AI factory workloads, where operations such as reductions, parameter streaming, and telemetry are independent or statistically aggregated and never consumed in program order, enforcing any form of ordering (even per‑ID ordering) adds overhead. UIO removes fabric‑enforced ordering, enabling true multi‑path parallelism and reducing buffering requirements.

This allows PCIe fabrics to sustain higher utilization for concurrent AI traffic. Since UIO enables independent transactions from different request originators to bypass one another safely, AI systems can optimize PCIe 7.0’s increased bandwidth to support rapidly growing model sizes and highly parallel GPU workloads.

UIO is especially effective at reducing read latency because multiple UIO read completions for a single UIO read request may be returned in any address order. This same flexibility applies to UIO write completions, with the additional capability that write completions for the same transaction ID may be coalesced. Since every UIO request has a corresponding completion, the request originator maintains the ordering of its own transactions. This allows the PCIe fabric to forward traffic along multiple paths without violating semantic correctness.

With its low latency, UIO transforms PCIe fabrics into high-throughput, highly parallel forwarding planes capable of accommodating modern AI workloads. Instead of relying on the fabric to manage per-flow sequencing, UIO shifts ordering control back to the source device that initiates the requests.

How UIO reduces latency and unlocks concurrency in AI applications

UIO’s command set and wire semantics reduce latency and boost performance for AI training and inference in several ways.

First, UIO mandates completions for all UIO requests. This gives GPU endpoints precise end-to-end flow control and prevents posted-write “fire and forget” bursts from clogging switch queues. It also cuts head-of-the-line blocking and shortens tail latency, speeding up requests by allowing different types of requests to bypass each other without applying any ordering rules within the PCIe fabric.

One of the classic head-of-the-line blocking examples in the baseline strict ordering rule is that current read requests are not permitted to bypass previous write requests. UIO eliminates this rule, allowing read and write requests to be processed in parallel and completed in any order, as shown in Figure 1.

Figure 1 UIO read and write requests are processed in parallel at the application layer. Source: Cadence Design Systems

In addition, UIO read requests reduce latency and buffering by allowing a completer to return read completions out of order. This enables data to be delivered as it becomes available, rather than delaying responses to preserve requests or address ordering. This improves overall efficiency by giving the device greater freedom to exploit internal data availability and minimizing completion queueing and reassembly overhead.

For example, Figure 2 and Figure 3 show the completion patterns for a single 512 MB MRD request for non-UIO (in-order) and UIO (out-of-order) cases, respectively.

Figure 2 Non-UIO completion responses must be in order for the same MRD request. Source: Cadence Design Systems

For non-UIO, Figure 2 illustrates that completions must arrive in order, starting at byte 0 and ending at byte 511. However, with UIO, the completion order can be random, as shown in Figure 3. The first two completions carry the last two chunks of MRD requests (256-383B and 384-511B) because they are already available in the local cache. After that, the application reads the remaining completion data from its local memory and sends the remaining two completions (0B-127B and 128B-255B).

Figure 3 UIO read and out-of-order completion responses are processed for the same request. Source: Cadence Design Systems

Second, because ordering is enforced at the source rather than at every intermediate hop, packets from unrelated GPU streams can be load-balanced across multiple parallel paths through the PCIe fabric without being serialized by switch-level producer-consumer rules. This increases effective throughput at a given link rate and stabilizes latency underload. In multi-path topologies, system architects often use a non-transparent bridge (NTB) to connect separate systems, enabling cross-system traffic within a larger fabric.

Third, UIO is available only in flit mode. Operating in fixed-size flits with UIO-specific VC3VC4 (via the streamlined virtual channel capability) isolates UIO traffic from legacy flows, minimizes delays, and improves switch buffer utilization.

Figure 4 The above diagram displays a multi-path application example. Source: Cadence Design Systems

Figure 4 shows two interconnected PCIe systems (System 0 and System 1), each with GPUs and local PCIe switches connected via multiple NTB links. The upper NTB link can operate with either UIO-enabled or non-UIO-enabled traffic, while the three diagonal and lower links operate with UIO-enabled NTB.

As a result, independent transactions can flow concurrently across switches SW0–SW3. This topology shows how UIO-based NTB paths improve GPU communication by enabling multipath routing, reducing latency, and increasing bandwidth in large-scale AI systems.

PCIe ordering: A traffic light analogy

A helpful way to think about PCIe ordering is traffic control in a city. Strict ordering is like running the entire city with a single traffic light, and every vehicle must wait its turn and proceed in sequence. While there is no ambiguity, congestion can quickly build up. Relaxed ordering allows certain vehicles to pass through intersections in specific emergency situations, provided it is safe to do so.

While this removes unnecessary traffic jams, it still assumes the traffic system is centrally managed. ID-based ordering further refines this model by assigning each neighborhood its own traffic lights. While cars within the same neighborhood must obey local ordering rules, traffic from different neighborhoods can flow independently. This improves parallelism without sacrificing local correctness.

UIO bypasses traffic light rules entirely. It is akin to routing traffic onto a freeway, where there are no intersections or signals at all, and vehicles move continuously as capacity allows. On a freeway, the infrastructure does not impose sequencing. Instead, the responsibility for safe merging and interpreting arrival order shifts to drivers.

Similarly, with UIO, the PCIe fabric no longer enforces producer‑consumer ordering or completion sequencing. The requester explicitly declares that ordering carries no semantic meaning, allowing the fabric and devices to deliver and complete transactions opportunistically. This maximizes parallelism while minimizing buffering and latency.

These four ordering schemes are a progression rather than a set of alternatives. Strict ordering prioritizes safety and simplicity, while relaxed ordering removes unnecessary global barriers. ID-based ordering preserves correctness within a context while enabling scale, and UIO explicitly abandons ordering when it has no value. This layered model allows PCIe to remain compatible with legacy software while scaling efficiently for modern accelerators, multi‑queue devices, and highly parallel workloads.

Turning PCIe bandwidth into system-level performance

Fully utilizing PCIe 7.0’s 128 GT/s link in today’s AI factories requires more than higher signaling rates. In an environment where thousands of GPUs, accelerators, and memory expanders operate as a single, distributed system, an ordering model that can scale with extreme parallelism is necessary.

Legacy relaxed ordering and ID-based ordering schemes retain implicit ordering constraints that limit their efficiency at PCIe 7.0 speeds, making them increasingly inadequate for AI factories operating at hyperscale.

UIO relaxes fabric‑enforced ordering and enables AI workloads to more effectively utilize multi‑path PCIe fabrics. By shifting ordering decisions to endpoints that already manage synchronization at the runtime and application levels, UIO reduces ordering-related head-of-the-line blocking issues.

Not only does this improve latency under bursty collective traffic, it also supports higher sustained link utilization across dense training and inference clusters. The result: Under AI workloads, PCIe 7.0 can be used more efficiently as a data plane, rather than simply serving as a peak‑bandwidth interconnect.

Vanessa Do is a senior product marketing manager for PCIe IP at Cadence with over 20 years of experience in PCIe design, system validation, and customer engagement. Her background spans PCIe protocol development, FPGA-based customer support, and leading cross‑functional teams to debug complex PCIe issues at the system level.

Editor’s Note

This is Part 2 of the article series about PCIe 7.0 fundamentals. Part 1 explained PCIe’s ordering rules and the distinction between relaxed ordering and ID-based ordering.

The post PCIe 7.0: Addressing legacy ordering limitations with UIO appeared first on EDN.

What if your virtual pet wasn’t just pixels on a screen, but something you could actually reach out and touch? A team at Reality Hack @ MIT 2026 made that idea real with Power Pet – a hybrid VR and physical companion that bridges the digital and tactile worlds using Arduino® UNO Q, hand tracking on Meta Quest 3, and a responsive robotic arm.

The project tackles something many of us can relate to: staying focused and emotionally regulated in an increasingly overwhelming world. But instead of adding more notifications or productivity pressure, Power Pet offers a calming presence that responds to you in both virtual reality and the real world. Pat the virtual pet on the head? The physical one tilts toward you. Step closer? Both versions respond with expressive eye contact and gentle animations.

How virtual becomes tangible

The team built the entire system using UNO Q at its core, taking advantage of the board’s hybrid MPU and MCU architecture: the Linux side handles networking via Python® and WebSockets, while the microcontroller manages real-time motor control for the stepper motors and servos. This division of labor – networking on one processor, time-critical hardware control on the other – allowed them to synchronize VR state and physical movement reliably without jitter.

Designed for focus, not stress

The inspiration behind Power Pet came from lived experience with neurodivergence and working directly with autistic individuals, where the team saw how sensory regulation and emotional support can dramatically affect focus and comfort. They were inspired by research showing that companion animals reduce stress and increase productivity – but without the barriers of cost, care requirements, and unpredictability.

What’s next: meditation, LLMs, and scent cues

The team has a lot of ideas of how Power Pet could be expanded in the future. They envision adding guided meditation to help users ground themselves, LLM-powered chat for when users feel stuck, and a shop system where progress unlocks skins and accessories for customization. Further exploration could involve additional sensory channels, like scent cues (aroma) and integrating real-world context using Arduino® Modulino sensors to detect stress proxies like temperature changes or fidgeting – and trigger calming behaviors in response.

When hardware meets heart

Power Pet is a beautiful example of what happens when technology serves human needs rather than the other way around: the team created something that’s both technically impressive and genuinely comforting.You can explore the project in detail, including code and documentation, on the Power Pet Devpost page. Check it out to find out more about the technical implementation, the research behind emotional regulation, or just curious about the future of tangible XR companions!

The post Power Pet: a VR companion at your side appeared first on Arduino Blog.

Remember at Arduino Days when we teased something that would fundamentally change how you build with App Lab? That moment is here. Arduino App Lab 0.7 introduces Custom Bricks and with it, the power to extend the apps for your Arduino^® UNO Q board and enjoy more creative freedom. Alongside this release, we are also introducing a new documentation experience designed to make learning App Lab feel more natural and intuitive from the very first step.

What are Custom Bricks?

Bricks are modular software components that add ready-to-use functionalities to your projects. If you’re new to Arduino App Lab, it helps to think about them as building blocks for complex features – without the complexity.

Until now, you’ve been working with the built-in Bricks we provide such as AI Audio and Computer Vision, or Web User Interface. Now you can build your own.

Custom Bricks transform App Lab from a powerful tool into an extensible platform. Build something once, package it as a Brick, and reuse it across every app you create. Connect to databases and integrate AI models. If you can code it in Python, you can make a Brick out of it.

Two flavors of custom

Custom Bricks come in two varieties, suited to different levels of complexity:

1. Python-only Bricks

The simplest approach. Create a Python library that exposes an API to your main program. Perfect for utility functions, data processing, or custom algorithms you want to reuse across projects.

2. Python + Container Bricks

Add Docker containers to your Brick for more powerful capabilities. Run specialized tools, APIs, or services alongside your app.

See Custom Bricks in action: OCR in minutes

During Arduino Days, our colleague Davide demonstrated Custom Bricks by building an OCR (Optical Character Recognition) Brick from scratch, live on stage. He took an object detection example, created a custom Brick, added a Docker container running Tesseract OCR, wrote the Python interface, and had working text recognition in a matter of minutes.

The result? A reusable OCR Brick that any app can import and use with a single function call. Upload an image, get back the text. Simple, powerful, and now part of his development toolkit forever.

^{Watch Davide’s full Custom Brick demo from Arduino Days 2026}

How to create your first Custom Brick
Getting started is straightforward — just follow these easy steps:

1. Create or open an app in App Lab.
2. Select “Add Brick.”
3. At the bottom of your screen, select “Create Custom Brick.”
4. Give it a name and let the system work its magic.

^{Create Custom Brick is available at the bottom bar inside a Brick}

App Lab automatically generates a folder structure with everything you need:

\n
• brick_config: Your Brick’s identity and configuration – ID, name, variables, etc.
\n\n\n\n
• brick_compose: A Docker Compose file for any containers
\n\n\n\n
• __init__.py: Your Python code, where you define the functions and classes that make your Brick useful
\n

Each Custom Brick lives locally in your app, fully under your control. Define a function like hello_arduino() in your Brick’s __init__.py, then import and call it from main.py. 

^{A folder structure is automatically added on the left hand side upon the creation of your Custom Brick}

^{Brick_config lets you define your Custom Brick’s identity and setup}

What will you build with a Custom Brick?

^{A Custom Brick in App Lab 0.7}

Custom Bricks unlock new possibilities, new freedom: 

\n
• Connect to any database (PostgreSQL, MongoDB, MariaDB – you name it)
\n\n\n\n
• Integrate custom ML models trained for your specific use case
\n\n\n\n
• Add containerized IoT services such as MQTT brokers, dashboard managers or your own middleware
\n\n\n\n
• Interface with audio/video processing tools
\n\n\n\n
• Build domain-specific libraries for your industry or research
\n\n\n\n
• Package complex workflows into simple, sharable components
\n

The OCR demo is just the beginning. We can’t wait to see what the Arduino community creates.

What else is new in 0.7?

In this release, in addition to Custom Bricks, we’ve made Arduino App Lab smoother and more intuitive across the board:

\n
• Console panel redesign: The console (including logs and serial monitor) is no longer a separate tab – it’s now integrated directly into the editor page.
\n

^{Enhanced App Lab editor with the integrated console panel at the bottom}

\n
• Drag-and-drop file management: Your file tree now supports drag-and-drop organization. Plus, you can also rename and delete folders directly. And much more: Bug fixes, performance improvements, and quality-of-life updates throughout. 
\n

^{Drag-and-drop file management is now possible in Arduino App Lab 0.7 version}

New App Lab documentation experience

Over time, Arduino App Lab has grown in capabilities, and with it, the documentation has naturally expanded as well. What we noticed is that users often wanted a quicker way to find the right information for their specific goal, without needing to scan through longer pages or figure out where to start. 

That’s why App Lab content is now organized by user journey and feature, with clear sections for getting started, setup, Bricks, and apps. A guided flow on the homepage helps you quickly reach the most relevant information (see below).

We also added new setup guides for each configuration, a dedicated Bridge API reference, and full Arduino App CLI command documentation to support more advanced use cases.

So it feels less like searching through a manual and more like being guided through a workspace where everything is ready when you need it.

^{A guided flow on the documentation homepage helps you quickly reach the most relevant information} 

Get started today

Arduino App Lab 0.7 is available now. Update through the app or download from this page. And check-out our refreshed App Lab documentation site. 

Did you build something cool with Custom Bricks? Share it with the community on Arduino Project Hub – we’re excited to see what you do with this cool new update.

Arduino and UNO are trademarks or registered trademarks of Arduino S.r.l.

The post Arduino® App Lab 0.7: Custom Bricks are here! appeared first on Arduino Blog.

The earliest commercial robots, like those used in factories for assembly, weren’t intelligent at all — they simply moved motors in sequence according to pre-programmed commands. But today we can build sophisticated robots that respond to their environment and even people. More importantly, that is possible on a modest budget with off-the-shelf parts. Luca Di Lorenzo (AKA LucaDilo) proved that by using an Arduino® UNO Q to create a robot arm that detects faces and acts accordingly.

In this case, the robot arm reacts to seeing a person’s face by picking up a pen and handing it to them. That is only moderately useful, but it is really just a demonstration of the hardware and capability. It shows that the robot can see what is around it and act accordingly. 

LucaDilo was able to achieve that with very affordable and accessible hardware, starting with an UNO Q. Not only does that direct the robot arm’s Feetech serial servo motors with its microcontroller, but it also performs facial recognition on the Linux side with a USB webcam. An optional Modulino LED Matrix provides status, feedback, and a dash of charm.

The structure and mechanical parts of the robot arm are all 3D-printable, even including the gripper mechanism.

LucaDilo programmed the arm so that upon startup, it enters into a setup mode. In that mode, the user can physically move the arm to a desired home position and up to nine different pen slot positions. After that, the robot will know where to move to pick up a pen when it sees a face.

The total build cost for this robot should be under $100/€85, which is pretty incredible when you consider how much computational power goes into just recognizing a face.

The post A robot arm that recognizes your face appeared first on Arduino Blog.

As industrial environments rapidly evolve with the integration of operational technology (OT) and information technology (IT), the demand for seamless connectivity and reliable power delivery has never been higher. The proliferation of smart devices, such as sensors, controllers, cameras and robotic arms, has made data indispensable to modern factories and process industries.

To meet the increased demand, more industrial IoT (IIoT) device manufacturers are turning to Power over Ethernet (PoE) as a preferred solution, leveraging its unique ability to deliver both power and data over a single cable. This convergence is enabling smarter, more flexible and efficient industrial operations, while simplifying deployment and maintenance for end users.

Figure 1 Industrial environments are increasingly integrating operational and information technologies. Source: Microchip

What’s Power over Ethernet (PoE)?

Power over Ethernet (PoE) is a technology that allows electrical power and data to be transmitted simultaneously over standard Ethernet cabling. It was first introduced by PowerDsine in 1998; the company was later acquired by Microchip Technology. The Institute of Electrical and Electronic Engineers (IEEE) introduced the first IEEE 802.3af standard in 2003.

PoE was initially developed to power devices like IP phones and wireless access points without the need for separate power supplies. Since then, PoE standards have evolved to include IEEE 802.3 af/at/bt supporting higher power levels and a broader range of devices, making it a cornerstone technology for modern networking encompassing industrial automation and IIoT deployments.

Why IIoT manufacturers are turning to PoE

For IIoT device manufacturers, PoE offers a host of compelling benefits. PoE simplifies deployment by combining power and data in a single cable, eliminating the need for separate electrical wiring and reducing installation complexity and cost. It enables flexible placement of devices, allowing installation in remote, hard-to-reach, or hazardous locations where traditional power sources may be unavailable or cost-prohibitive.

PoE also supports unified network architecture, streamlining network design and making it easier to scale and adapt to changing operational needs. Reliability and compliance are enhanced, as standards-based PoE delivers safe, low-voltage DC power, supporting regulatory compliance and minimizing electrical hazards.

Additionally, offering PoE-powered devices can provide manufacturers with a competitive advantage in a crowded market by delivering a more convenient, integrated solution to customers.

Overcoming PoE deployment challenges in industrial settings

Despite its advantages, deploying PoE in industrial environments is not without challenges. One of the primary obstacles is the limited availability of PoE-enabled network infrastructure. Many existing industrial networks lack PoE switches, and even when available, these switches may not provide sufficient power on every port to support all connected devices.

The cost and complexity of upgrading network infrastructure can be prohibitive, especially in legacy facilities. Other challenges include limited access to power, as not all areas of a factory or plant have easy access to network cabling or power outlets, making device placement difficult. The high cost of power delivery can also be a concern, as retrofitting facilities to support PoE can be expensive and disruptive.

Compatibility concerns must be addressed to ensure that PoE-powered devices work seamlessly with existing network equipment, avoiding downtime and support issues. Finally, scalability is a challenge, as the number of connected devices grows, so does the demand for reliable, scalable power solutions.

Introducing PoE midspans: Supplementing network power

To address the challenge of limited PoE-enabled infrastructure, many industrial facilities are turning to PoE midspans, also known as injectors, to supplement network power where it does not exist. A PoE injector is a device that sits between an Ethernet port that is not supplying PoE and the powered device, injecting power into the Ethernet cable so that both data and power are delivered to the endpoint.

This approach allows manufacturers and customers to deploy PoE-powered IIoT devices without the need to replace existing switches or overhaul network architecture, making it a cost-effective and scalable solution for expanding PoE coverage in industrial environments.

Figure 2 PoE midspans inject power into the Ethernet cable. Source: Microchip

PoE industrial injectors vs. standard indoor injectors

While standard indoor PoE injectors are suitable for office or commercial settings, industrial environments demand more robust solutions. PoE industrial injectors are specifically designed to withstand the harsh conditions often found in factories, processing plants, and outdoor installations.

These injectors feature ruggedized construction, enabling reliable operation in environments with extreme temperatures, humidity, dust, and vibration. They support an extended temperature range, ensuring consistent performance in both hot and cold conditions.

Enhanced safety and compliance are also critical, as industrial injectors meet stringent safety and regulatory standards, providing low-voltage, standards-compliant DC power that minimizes electrical hazards. Industrial PoE injectors support higher power levels—such as IEEE 802.3bt up to 90 W—to accommodate demanding devices and are designed with robust surge protection, which is essential in industrial environments where electrical surges from machinery or harsh conditions are more common.

Flexible mounting options, such as DIN rail, wall, or rack installations, accommodate diverse deployment scenarios. Reliability and longevity are ensured through components and enclosures designed for continuous operation, providing long-term durability and minimal maintenance. These features are essential for maintaining uptime, safety, and performance in industrial settings, where environmental challenges and operational demands are far greater than in typical office environments.

Figure 3 Here is a visual comparison between standard indoor midspan (above) and industrial midspan (below). Source: Microchip

What to look for in a PoE solution provider

For IIoT device manufacturers and customers deploying PoE-powered devices, selecting the right PoE solution provider is critical. Proven compatibility is essential; the provider’s injectors should be tested and validated for seamless operation with a wide range of industrial devices, reducing the risk of downtime and support issues.

Flexible power options are important, with support for various power levels and device types to meet diverse application needs. Reliability and compliance should be prioritized, ensuring solutions meet industry standards for safety and performance, supporting regulatory requirements and minimizing risk.

Ease of installation is also key, with plug-and-play solutions that leverage existing Ethernet cabling to simplify deployment and reduce installation time. Rugged design is necessary for industrial-grade injectors, offering robust construction and extended temperature ranges for reliable operation in challenging environments.

Finally, strong technical support and post-sale service from the provider can help resolve compatibility issues and ensure long-term satisfaction. By prioritizing these features, manufacturers and customers can ensure successful, scalable, and reliable PoE deployments in industrial environments, unlocking the full potential of smart IIoT devices.

Alan Jay Zwiren is senior marketing manager of Microchip Technology’s Networking and Connectivity Business Unit.

Special Section: Smart Factory

\n
• Rethinking machine vision in industrial automation
\n

The post Smart factory: The rise of PoE in industrial environments appeared first on EDN.

Obtain tighter stop band impedance variance via the techniques detailed in this tutorial.

Input impedances presented by lowpass and highpass filters in their respective stop bands are usually not controlled and can vary quite widely. Sometimes though, we’d like to have a little better control of them.

For example, tee-configuration low-pass filters and high-pass filters exhibit input impedances and frequency responses which are typified in the following sketches:

\nFigure 1 A typical tee-configuration low-pass filter delivers non-ideal results.

\nFigure 2 A typical tee-configuration high-pass filter also delivers non-ideal results.

For tee-configuration filters, the presented input impedance in the passband tends toward the load resistance value, but in the stopband, the presented input impedance rises without limit. That essentially uncontrolled and rising impedance can create stability problems for some kinds of driving devices delivering input signals to such filters.

There is at least a partial remedy for this impedance issue possible, as follows:

\nFigure 3 A tee-configuration filter pair provides at least a partial remedy.

Using both a low-pass and high-pass filter, with each feeding its respective load, the input impedance becomes controllable both in the passband and the stopband of whichever filter you decide is the intended signal path. Input impedance and frequency responses would take on the following forms:

\nFigure 4 Controlled impedance filtering can improve stability.

The corner frequency impedance null doesn’t go away, but the input impedance both above and below that corner frequency tends to the load resistance values, chosen here as fifty ohms, which may help make a driving amplifier more stable.

John Dunn is an electronics consultant and a graduate of The Polytechnic Institute of Brooklyn (BSEE) and of New York University (MSEE).

Related Content

\n
• Toward better behaved Sallen-Key low pass filters
\n
• Simple state variable active filter
\n
• A digital filter system (DFS), Part 1
\n
• A digital filter system (DFS), Part 2
\n

The post Filter impedance control appeared first on EDN.

Deepak Shankar, founder of Mirabilis Design and developer of VisualSim Architect platform for chip and system designs, has created this cartoon for electronics design engineers.

The post The system architect’s sketchbook: The buildout frenzy appeared first on EDN.

In modern engineering, precision fluid control is vital across industries ranging from electronics manufacturing to medical device design. Peristaltic pumps, with their distinctive squeeze-and-release mechanism, deliver exceptional reliability, cleanliness, and accuracy in fluid transfer. By preventing direct contact between the pump and the fluid, they ensure contamination-free operation while reducing maintenance demands.

This post explores the fundamentals of peristaltic pumping and how electric-drive systems help engineers achieve the perfect flow in today’s most demanding applications.

Peristaltic pump vs. electric peristaltic pump

A peristaltic pump refers to the general pumping principle: fluid is moved through flexible tubing by a rotating squeeze-and-release motion. This design ensures accurate flow and prevents contamination since the fluid never touches the pump components.

An electric peristaltic pump, however, is a specific implementation powered by an electric motor. The motor provides consistent speed, programmable control, and higher precision, making it ideal for industrial automation, laboratory dosing, and electronics manufacturing processes. While the term “peristaltic pump” covers the entire category, “electric peristaltic pump” highlights the modern, motor-driven versions that engineers rely on for efficiency and repeatability.

Figure 1 A sample of today’s compact electric peristaltic pump—this battery-operable low-voltage DC motor version demonstrates modern design efficiency. Source: Author

Peristaltic pumps vs. dosing pumps

A dosing pump is a broader category of pumps designed to deliver exact volumes of fluid at controlled intervals. Peristaltic pumps can serve as dosing pumps when paired with electric drives and programmable controls, but other pump types—such as diaphragm or piston pumps—are also used for dosing applications.

In short, all electric peristaltic pumps can function as dosing pumps, but not all dosing pumps are peristaltic. Understanding this distinction helps engineers select the right solution depending on whether the priority is contamination-free transfer, chemical compatibility, or ultra-precise dosing.

As a quick aside, it’s worth noting the distinction between DC-motor-driven and stepper-motor-driven peristaltic pumps. DC motors provide continuous rotation with simple speed control, making them cost-effective and compact for general fluid transfer.

Stepper motors, on the other hand, deliver precise incremental motion, enabling highly accurate dosing and repeatability. The choice between the two depends on application requirements: DC motors excel in straightforward pumping tasks, while stepper motors are favored in laboratory and industrial settings where precision is paramount.

Figure 2 A stepper-motor peristaltic pump delivers responsive start-stop and reverse operation, offers a wide speed range, and ensures reliability, thus meeting the accurate and dependable flow control demanded by precision instruments. Source: Author

The inner workings of peristaltic pumps

At the heart of a peristaltic pump is a simple but ingenious principle: fluid is transported by compressing flexible tubing in a controlled sequence. As rollers mounted on a rotating rotor travel along the tubing, they push the fluid forward in discrete segments, creating a smooth, continuous flow. Because the fluid remains fully enclosed within the tubing, there is no risk of contamination or contact with mechanical components, making this design particularly valuable in sensitive applications such as pharmaceuticals.

The internal structure of a peristaltic pump reflects this principle with elegant simplicity. A rotor fitted with rollers or shoes provides the pressure needed to move the fluid, while the tubing’s elasticity ensures it returns to its original shape after each cycle. The pump housing supports and guides the mechanism, ensuring consistent operation.

This combination of mechanical precision and material resilience allows peristaltic pumps to deliver accurate dosing, reliable performance, and easy maintenance—qualities that make them indispensable in modern engineering systems.

Figure 3 Drawing simply depicts the mechanisms of single-roller and multi-roller peristaltic pumps. Source: Author

As a closely related note, industrial peristaltic pumps differ from those used in general and medical applications. Industrial designs often employ shoe mechanisms to achieve higher pressures and rugged performance, making them suitable for chemical transfer, mining, and other heavy-duty environments where durability is paramount.

By contrast, general-purpose and medical pumps typically rely on roller mechanisms, which minimize friction, reduce energy consumption, and extend tubing life—qualities essential for precision dosing, sterility, and reliable operation in laboratory and healthcare settings.

And when powered by an electric motor, the same mechanism gains programmable control, variable speed adjustment, and enhanced precision. Electric peristaltic pumps transform the fundamental design into a highly versatile dosing system, capable of delivering exact volumes with repeatability. This evolution from a simple mechanical concept to an automated solution makes them indispensable in neoteric engineering environments where accuracy, efficiency, and reliability are non-negotiable.

Pulsed flow: Quick pointers for makers and engineers

Now to a few compact cues and practical insights to keep your designs flowing with precision. First off take note that motor choice sets the tone for performance: DC drives are cost-effective for simple transfer tasks like irrigation or fluid circulation, while stepper motors deliver the precision required for accurate dosing.

Roller mechanisms are especially suitable for medical and laboratory applications, since they minimize friction, extend tubing life, and provide gentle, contamination-free fluid handling. They also make an excellent choice for hobbyist projects, offering simplicity, reliability, and low maintenance for makers experimenting with fluid transfer.

By contrast, shoe mechanisms are designed for rugged industrial environments where higher pressures are needed, though they accelerate tubing wear. Tubing selection is equally critical; silicone ensures biocompatibility, PVC covers general transfer needs, and specialized elastomers withstand aggressive chemicals.

Now recall that roller pumps themselves come in single-roller and multi-roller designs. Single-roller pumps are mechanically simpler, lower-cost, and easier to maintain, making them suitable for basic transfer or hobbyist projects where flow smoothness is less critical.

Multi-roller pumps, by contrast, provide smoother, more continuous flow with reduced pulsation, which is essential in medical and laboratory applications where dosing accuracy and patient safety matter. While multi-roller designs increase complexity and cost, they extend tubing life and deliver higher precision, making them the preferred choice in food and beverage industries as well.

Also, electric drives add programmable control and variable speed, enabling integration with MCUs or PLCs for automation, while compact low-voltage battery-operated designs balance efficiency with portability in point-of-care devices. Notably, to mitigate the risk of power outages, contemporary electric peristaltic pumps for medical applications are frequently equipped with hand cranks for manual fluid delivery.

In today’s market, DC drive versions are available with more than just a regular DC motor—many include extra leads for speed control inputs (often via pulse width modulation), tachometer outputs, and other control/feedback signals. These additions give designers greater flexibility in monitoring, closed-loop control, and seamless integration with modern embedded systems, making even basic DC drives far more versatile than before.

Figure 4 Datasheet snippet highlighting a brushless peristaltic pump that delivers multiple features, including speed and direction control. Source: Binaca Pumps

Maker tip: PPM-controlled “digital” peristaltic pumps simplify automation by emulating the behavior of standard RC servo motors. Because the motor driver is integrated directly into the pump, you can skip the complex external circuitry usually needed to manage speed or direction. This lets you control the pump directly from a microcontroller’s digital pin using standard libraries—saving you both space and setup time (here is a practical example).

Frankly, when it comes to real-world control challenges, few are as nuanced as those involving peristaltic pumps. The core difficulty stems from two inherent characteristics of their operation. First, these pumps often run at very low speeds, sometimes down to a complete standstill depending on the application. Second, the motor experiences highly variable loads as the rollers engage and disengage with the flexible tube.

For most of the rotation cycle, the rollers move smoothly along the tube with minimal changes in torque or fluid pressure. However, at the points of disengagement and re-engagement, the system encounters sharp pulses in both torque and pressure.

That is, the combination of low-speed operation (which challenges velocity controllers) and cyclic load fluctuations (which creates non-linear disturbances) is exactly what makes these pumps “fussy” to control. Addressing these dynamics requires specialized motion control strategies—but that is a topic for another discussion.

Closing note: Peristalsis in engineering form

I have more to share but let me close with the fundamentals at this time.

Peristaltic pumps are a class of positive displacement pumps inspired directly by biology. Just as peristalsis in the digestive tract moves food through rhythmic muscle contractions, these pumps transport fluids by progressively deforming flexible tubing with rollers or shoes. The motion sweeps fluid forward, but because the swept length is always less than the tubing circumference, each rotation introduces a brief pause, resulting in the characteristic pulsed flow.

Designs vary between fixed and variable occlusion systems: fixed occlusion maintains a constant compression force, while variable occlusion allows adjustment via springs to fine-tune performance. Accuracy is further influenced by the slip factor, a correction term that accounts for incomplete tubing recovery and backflow, which can cause measured dispense rates to differ from theoretical values.

In peristaltic pump engineering, slip refers specifically to tubing recovery and backflow losses, which differs from the slip factor used in turbomachinery but serves the same purpose of correcting theoretical versus actual flow.

In essence, peristaltic pumps mirror a biological process with engineering precision—balancing simplicity, safety, and adaptability across a broad range of applications. In healthcare, they provide sterile infusion for IV therapy, dialysis, and precise drug delivery. In laboratories, they handle chemical dosing, reagent transfer, and bioprocessing where purity is paramount. Industrially, they manage viscous fluids, corrosive chemicals, and food-grade materials without risk of cross-contamination.

In the food and beverage sector, they support hygienic transfer of juices, dairy, and brewing ingredients. For hobbyists, they simplify aquarium maintenance, hydroponics, and small-scale brewing. In agriculture, they excel at nutrient dosing in irrigation and supplement delivery in animal farming. Their gentle, pulsed flow and hygienic design make them a versatile solution wherever controlled, reliable fluid handling is required.

As you explore these designs in your own projects, consider how roller choice, hose selection, occlusion type, and modern drive features can shape performance, and share your insights to keep the conversation on precision fluid handling moving forward.

T. K. Hareendran is a self-taught electronics enthusiast with a strong passion for innovative circuit design and hands-on technology. He develops both experimental and practical electronic projects, documenting and sharing his work to support fellow tinkerers and learners. Beyond the workbench, he dedicates time to technical writing and hardware evaluations to contribute meaningfully to the maker community.

Related Content

\n
• Designing Motor Control: Key Aspects
\n
• Designer’s guide: Motor control and drivers
\n
• Mastering motor control: motor control 101
\n
• Optimizing motor control for energy efficiency
\n
• A primer on industrial motors and motor control
\n

The post Engineering the perfect flow with peristaltic pumps appeared first on EDN.

Increasing power demands in data centers demand high-efficiency, high-density power-conversion solutions.

Figure 1 shows a block diagram of power distribution inside an IT tray. A 48V bus bar goes down the back of the rack to distribute power to the IT trays. Inside each tray is hot-swap or e-fuse circuitry to limit inrush current during tray plug-in and to protect the upstream rack during tray failures. Intermediate bus converters (IBCs) convert 48V to the second-stage voltage, usually 12V or 6V. Final-stage multiphase buck voltage regulators complete power delivery by converting the second-stage voltage to the loads, with the majority of power going to sub-1V, high-current processors. In this edition of Power Tips, I will focus on the 48V IBC, covering design considerations, comparing topologies, and discussing system trade-offs of various approaches.

\nFigure 1 48V IT tray power distribution. Source: Texas Instruments

The IBC power distribution network offers a wide range of power-conversion approaches inside an IT tray (Reference 1). As the system architect, you have three main design choices:

\n
• A modular or discrete solution (also known as chip-down design).
\n
• Regulated, unregulated (also known as fixed ratio) or semiregulated IBC operation.
\n
• The second-stage bus voltage to maximize system performance.
\n

When selecting a modular or chip-down design power converter, your main trade-off will be power density vs. board design flexibility. Power modules, as shown in Figure 2a, are highly optimized solutions built on high-layer-count printed circuit boards (PCBs) (usually more than 16), offering prequalification and the highest power density. The drawbacks of power modules are a lack of flexibility, with fixed footprints and set features, as well as a higher cost per watt.

Chip-down designs, as shown in Figure 2b, are highly flexible solutions that offer footprint and feature freedom, with a lower cost per watt in high-volume production. Their drawbacks include longer upfront time and greater cost investments to qualify the design.

(a)	(b)

Figure 2 48V IBC design examples of modular (a) and chip-down design (b) approaches. Source: Texas Instruments

When considering the output regulation of the IBC, your choice depends on two main factors: the load being powered and the operating range of the IBC’s input bus voltage. When the IBC directly drives 12V loads such as cooling fans, hard drives and Peripheral Component Interconnect Express cards, only a fully regulated output voltage (Reference 1) will ensure component safety. In modern data centers, the tray voltage has a more stable, narrow range, typically 40V to 60V. This narrow input range gives you the option to use higher-efficiency and higher-power-density fixed-ratio or semiregulated IBCs. The regulated second-stage voltage regulators following the IBC stage can absorb fixed-ratio IBC output voltage fluctuations.

Your third design choice is the second-stage voltage delivered by the IBC. Equation 1 determines system efficiency (η_system):

η_system = η_IBC x η_PDN x η_VR

For a given power load, decreasing the second-stage bus voltage will lower the IBC efficiency (η_IBC), because it must deliver more current at a lower voltage to provide the same output power. Similarly, for the motherboard power distribution network (PDN), which distributes current from the first-stage IBC to the second-stage voltage regulator, the PDN efficiency (η_PDN) will also decrease because of increased I² x R ohmic losses. The benefit of a lower second-stage bus voltage is apparent when using final-stage, high-frequency, high-current voltage regulators with significantly reduced voltage-related switching losses. This results in higher second-stage efficiency (η_VR) and a potentially smaller size of the second stage.

Unlike a buck converter-dominated second-stage voltage regulator, a first-stage IBC has a wide range of power delivery approaches and thus a wider variety of power-conversion topologies available. In most modern IT applications, isolation for safety purposes is not required, so your power topology options increase further when you can consider transformerless options. Figure 3 shows four popular options for IBC module and chip-down designs.

The full-bridge converter shown in Figure 3a is a simple buck converter-derived transformer-isolated topology. The full-bridge converter’s strengths are ease of regulation and the ability to easily scale the intended output voltage by adjusting the transformer turns ratio for your chosen second-stage bus voltage. One drawback of the full-bridge converter is that transformer design is key to its performance, requiring a high-layer-count PCB that limits the topology to module-based designs. Another drawback of the full-bridge converter is that the primary devices are hard-switched, limiting power density and efficiency.

The transformer-isolated inductor-inductor-capacitor (LLC) converter shown in Figure 3b looks very similar to the full-bridge converter but uses an additional capacitor and two inductors to eliminate switching-related losses in the primary devices, enabling high efficiency and high power density (Reference 2). The LLC converter has the same transformer-related strength (an easily scalable output voltage) and weakness (it’s limited to module-based designs) as the full-bridge converter. The LLC converter operates with the highest efficiency at the resonant frequency set by the additional passive components (CR and LR), with efficiency decreasing as you move away from the resonant frequency to regulate the output voltage. For this reason, the LLC converter’s most common application in IBCs is fixed-ratio designs, always operating at the resonant frequency, ensuring the highest efficiency.

Two other popular topologies, the hybrid switched-capacitor (HSC) converter (Reference 3) shown in Figure 3c and the basic buck converter shown in Figure 3d, both offer benefits for chip-down designs because of their lack of AC-dependent power transformers. The HSC converter has a natural step-down ratio of 4-to-1, making it a strong candidate for high-efficiency 48V to 12V IBCs. The addition of flying capacitors limits the power density and hinders this converter’s operation in boost mode, making it a good fit for semiregulation, as regulating only occurs in step-down buck converter mode.

Because the HSC converter has a natural step-down ratio of 4-to-1, scaling the output voltage down further to an 8-to-1 6V_OUT design (for example) is more challenging than it would be for the full-bridge and LLC converter options because the HSC converter must rely instead on a longer freewheeling period, requiring a larger output filter inductor, decreasing power density and efficiency.

The buck converter is the most common topology in power electronics, used exclusively in the second-stage voltage regulator, so it is natural to want to apply this simple and well-known approach to the IBC stage as well. The challenge with using a buck converter in the higher-voltage IBC application is that the power devices experience the highest voltage and current stresses when compared to the other topologies, limiting efficiency and power density.

Figure 3 Popular IBC topologies: full-bridge converter (a); LLC converter (b); HSC converter (c); and buck converter (d). Source: Texas Instruments

Table 1 compares the different topologies and trade-offs.

Table 1 Comparing IBC topology characteristics.

 With the maturation of gallium nitride (GaN) power devices (Reference 4), which have much lower switching-related charges compared to traditional silicon metal-oxide semiconductor field-effect transistors (MOSFETs), simpler topologies like the buck converter topology become more attractive and viable options for higher-voltage applications like IBCs. See Table 2.

Table 2 Comparison of 100V GaN and silicon-based IBC semiconductor options.

The IBC power distribution network offers the widest range of power-conversion approaches of the systems inside an IT tray for good reason. As power requirements and architectures rapidly evolve, the best way to optimize performance for 48V IBCs changes. And as additional variables such as highly improved GaN semiconductors get thrown into the equation, it becomes even more important to understand design considerations, topology comparisons and trade-offs.

References

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1. Hsu, C., L. Olariu, S. Zou, et al. “48V Onboard Power Solution Requirements.” Open Compute Project, Version 1.0.0, Nov. 15, 2024.
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2. McDonald, Brent. “Overview of a planar transformer used in a 1kW high-density LLC power module.” Texas Instruments technical article, 2025.
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3. Li, C., and J.A. Cobos. “A Switched Capacitor and Autotransformer Hybrid Converter With DC Current in the Windings,” in IEEE Transactions on Power Electronics 37 (2), February 2022, pp. 1870-1884.
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4. Gallium nitride (GaN) power stages, Texas Instruments.
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David Reusch is a systems engineer on the data center team at Texas Instruments, specializing in power electronics. David has more than 20 years of experience in power electronics, ranging from cutting-edge gallium nitride (GaN) technology to high-reliability space-grade DC-DC converters. He received his B.S., M.S. and Ph.D. in electrical engineering from Virginia Tech.

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• Power Tips #151: Improving efficiency in 48V-input multiphase buck converters with GaN
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• Power Tips #127: Using advanced control methods to increase the power density of GaN-based PFC
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The post Power Tips #152: Design considerations and topology comparisons for 48V intermediate bus converters appeared first on EDN.

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Nobody enjoys doing inspections, but they’re a fact of life across many different industries. If you rent out moving trucks, for example, you need to do inspections before and after each rental, so you know if a customer damages something that needs to be addressed. But the logistics of those inspections are tricky and often expensive. That’s why Alejandro Vazquez developed “Brick.”

Brick is an open-source embedded device designed specifically for performing and logging inspections. It is a handheld and compact unit that inspectors can carry in a glovebox, wear on a belt, or stuff in a pocket. When it is time for an inspection, they can use Brick to snap relevant photos according to a predefined routine, flag anomalies, and upload inspection reports.

Most importantly, it doesn’t cost a lot of money to build a Brick and it won’t require any proprietary (read: expensive) systems or software.

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That’s possible because Brick relies on accessible off-the-shelf hardware. That includes an Arduino GIGA R1 WiFi board and GIGA Display Shield, an ArduCam Mini, an RFID reader, a real-time clock module with battery backup, and a NiMH-based rechargeable battery.

Vazquez built the interface GUI on LVGL and took advantage of available libraries when possible, but the functionality is custom. It is also secure, thanks to HTTPS communication, which could be critical for some businesses. 

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On top of the Brick device itself, Vazquez even created a cloud backend and a web interface to access that. After building one or more Brick devices, a business could deploy the rest of the system in an afternoon — all without purchasing licenses or subscriptions.

The post Brick streamlines inspections on a budget appeared first on Arduino Blog.

Aliasing is thankfully becoming a less frequent problem due to improved instrument designs. Users should still be aware of it to prevent time- and money-costly errors.

Aliasing is an ever-present potential problem in sampled data acquisition systems. It occurs when input signals are sampled at a sample rate that is too low. If you haven’t been bamboozled by an aliased signal, you are extremely lucky.

Sampled data instruments, such as digitizers and digital oscilloscopes, must sample their input signals at a rate greater than twice the highest frequency component present in the input signal. If this criterion is not met, then aliasing can occur. Figure 1 shows an example of aliasing.

\nFigure 1 In this example of aliasing, a 50MHz sine wave was acquired at sampling rates of 1 Giga samples per second (GS/s) and 55 Mega samples per second (MS/s). The 55 MS/s acquisition is aliased and displayed as a 5 MHz waveform.
\nSource: Art Pini

A 50 MHz sine wave was acquired at both 1 GS/s and 55 MS/s. The waveform acquired at 1 GS/s has the correct frequency of 50 MHz as shown in the frequency parameter P1. The waveform acquired at 55 MS/s is aliased and has a frequency of 5 MHz as reported in parameter readout P2. The alias waveform will appear as having a different frequency than the correctly sampled waveform. This can be a significant problem that can be costly if not addressed carefully.

Let’s look into aliasing and learn how to deal with it. Sampling is a mixing process. When you apply an input signal to a sampler, the resulting output from the sampler contains the original waveforms, the sampling waveform, and the sum and difference frequencies, including the harmonics of the sampling signal. This is illustrated in Figure 2.

\nFigure 2 Sampling is a mixing or multiplicative process. The baseband frequency spectrum of the acquired signal appears as the upper and lower sidebands about the sampling frequency and all its harmonics.
\nSource: Art Pini

A correctly sampled waveform will have more than two samples per cycle at the bandwidth limit. In the sampler output, the baseband frequency spectrum of the input signal will appear as upper and lower sidebands about the sampling frequency and its harmonics. The right-hand graphs show the output spectrum of the sampler for the correct sampling rate (upper) and the undersampled case (lower). As the sampling frequency is decreased below twice the input signal bandwidth, the lower sideband of the sampling frequency interferes with the baseband signal, resulting in aliasing.

In the time-domain view (left-hand graphs), the aliased signal lacks sufficient time resolution to track the input waveform. Returning to the example in Figure 1, the 50 MHz input sampled at 55 MS/s will result in sum and difference image frequencies that are above and below the 55 MS/s sampling frequency. The lower sideband image falls into the baseband region of the spectrum and is the source of the 5 MHz alias signal.

Current digital instrument designs generally use sampling rates much higher than the instrument’s analog bandwidth. Some instruments may use sharp-cutoff anti-aliasing low-pass filters to limit the input bandwidth and control the instrument’s frequency response. These techniques, combined with long acquisition memories, also minimize this classic problem.  Still, users should be aware of aliasing.

Recognizing Aliasing

It is good practice to determine the frequency of the measured signal and verify that it has not been aliased. If the characteristics of the input signal are unknown, it is good practice to view the signal at the highest available sample rate, then decrease the sampling rate as needed. If aliasing occurs, you will see the signal’s frequency change as you select a lower sampling rate.

Another hint that a signal is an alias is that it will appear to have an unstable trigger and will jump erratically in time. This occurs because the instrument is triggered by the signal, and the alias, with fewer samples, may not display the trigger point. The instrument displays the nearest sample, which varies from one acquisition to the next, causing instability.

Aliasing can also be recognized by observing the effect on the input signal’s frequency-domain spectrum as the signal’s frequency is varied. A spectral component that shows a decrease in frequency when the input signal’s frequency is increased, a reversal of direction, is an alias. As the frequency of a sine wave increases, the spectral line corresponding to that sine wave will move to the right until it hits the Nyquist frequency of one-half the sample rate.

As the frequency increases above Nyquist, an aliased image from the lower sideband about the sampling frequency will fold back into the baseband spectrum, moving downward in frequency. The lower-sideband images for each harmonic of the sampling frequency show this reversal. Upper sideband images will move in the correct direction. This phenomenon is called spectral folding.

A helpful technique to view an aliased signal

If the signal is a relatively simple periodic waveform, such as the example sine wave, then enabling infinite display persistence will show the underlying waveform, as shown in Figure 3.

\nFigure 3 The aliased signal (upper trace) and the same signal displayed with infinite persistence turned on (lower trace). The persistence display accumulates all the sample values showing the original 50 MHz waveform.
\nSource: Art Pini

All sample points in the aliased waveform are real. If infinite persistence is enabled, all samples are accumulated on the persistence display, and the original unaliased waveform is eventually recovered. This technique won’t work for complex signals such as non-return-to-zero (NRZ) data or broadband signals.

Using aliased waveforms

Given that aliased signals are made up of real samples, an aliased signal can be used in measurements, as long as the signal’s frequency is not being measured. Consider measuring the output of a remote keyless entry transmitter. This device outputs a pulse-modulated RF signal with a carrier frequency of 433MHz. This signal has a relatively narrow bandwidth about the carrier frequency. The information being transmitted is encoded in a 400 ms pulse pattern.

Two measurement scenarios are needed. The first is to characterize the RF signal. Parameters like frequency. Also, the shape of the RF envelope affects the purity of the transmitted signal. The second measurement would involve decoding the information content. Using an oscilloscope with a 20 Mega sample (MS) memory at a horizontal scale setting of 100 ms per division (1 second acquisition time), the sampling rate would be 20 MS/s. Figure 4 shows the two measurement processes for both the RF and Data decoding measurements.

\nFigure 4 Measurements on a remote keyless entry transmitter use an aliased signal to decode digital data.
\nSource: Art Pini

The traces on the left side of the screen show the RF measurements. The signal is acquired at 20 GS/s, and its leading edge is captured. The oscilloscope measures the RF carrier frequency at 433.9 MHz. The envelope of the RF carrier is extracted by applying the absolute value function, followed by a low-pass filter to create a peak detector. Trace F1 (bottom) shows the envelope. A copy (Trace F3) of the Envelope is also overlaid on a horizontally expanded zoom view (Trace Z1) of the leading edge of the signal. The envelope can be used to measure the envelope’s rise time.

The right side of the display shows the data decoding process. The entire data packet is acquired on a 100-ms-per-division horizontal scale. The sampling rate is 20 MS/s. The RF carrier is aliased down to 6.13 MHz as measured in parameter P2. The aliased frequency of the carrier is the result of mixing the twenty-second harmonic of the sampling rate with the 433.9 MHz carrier. The same envelope detection technique is applied to the entire packet, rendering the data content as an NRZ signal. Aliasing has enabled the acquisition of the entire signal data packet.

Conclusion

Aliasing in digital instruments is a digitizer characteristic that is becoming less frequent a problem due to improved instrument designs, including anti-aliasing filters, oversampling, and very long acquisition memories. Users should still be aware of aliasing to prevent errors that cost time and money.

Arthur Pini is a technical support specialist and electrical engineer with over 50 years of experience in electronics test and measurement.

Related Content

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• Sampling and aliasing
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• Using oscilloscope filters for better measurements
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• Combating noise and interference in oscilloscopes and digitizers
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• Building a low-cost, precision digital oscilloscope—Part 1
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• Building a low-cost, precision digital oscilloscope – Part 2
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The post Aliasing, the bane of sampled data systems appeared first on EDN.

Automated test equipment (ATE) supplier Teradyne is bolstering its test solutions for semiconductor design by acquiring TestInsight, a provider of test program creation, pattern conversion, and pre-silicon validation tools used across ATE platforms and semiconductor design environments.

By acquiring a supplier of semiconductor test development, validation, and conversion software, Teradyne aims to scale its next generation of pre-silicon validation and automated pattern generation technologies. That strengthens Teradyne’s ability to support semiconductor design-in activities to accelerate time-to-market in the emerging AI and data center markets.

Here is how pattern conversion across multiple cores and CPUs accelerates the test program. Source: TestInsight

Greg Smith, president and CEO of Teradyne, calls TestInsight’s tools foundational to modern test program development. “By integrating the TestInsight team into Teradyne, we enhance our ability to help customers achieve silicon readiness faster and with greater confidence.”

The acquisition will allow Teradyne to combine its ATE platforms with TestInsight’s tightly integrated design-to-test workflow, thereby reducing debug cycles, improving coverage, and enabling earlier test program readiness. In short, the acquisition of a design-to-test software firm will help Teradyne close the gap between design and test in semiconductor design environments.

TestInsight announced that it will continue to support its existing customers across all ATE platforms.

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The post Teradyne snaps up TestInsight to boost ATE for semiconductors appeared first on EDN.

Ketone detection may sound like the domain of biochemistry, but at its core, it’s also an electronics challenge: how do we translate a chemical presence into a measurable electrical signal?

The key lies in the ability of circuits to convert molecular interactions into quantifiable outputs. Through principles like signal conversion, amplification, and conditioning, electronics transform invisible chemical activity into reliable data, making ketone monitoring practical and accurate while underscoring how deeply electronics shape modern health technologies.

Ketones: Small molecules, big impact

Ketone detection is crucial because these molecules act as direct indicators of how the body manages its energy balance. Moderate levels can reflect healthy states such as fasting, exercise, or adherence to ketogenic diets, while dangerously high concentrations may signal conditions like diabetic ketoacidosis that require urgent medical attention.

By providing timely and accurate measurements, ketone monitoring empowers individuals to optimize nutrition and performance and gives clinicians essential data to prevent and manage metabolic complications. In both everyday wellness and clinical care, reliable ketone tracking plays a decisive role in safeguarding health.

Overview of ketone detection sensors

Nowadays ketone detection has moved well beyond the lab bench and into lifestyle and wearable electronics. Compact analyzers are being built into fitness trackers, smartwatches, and portable health devices, giving users real-time insights into metabolism and diet. This evolution is powered by the fundamentals of electronics—miniaturization, low-power design, and signal processing—that make complex biochemical measurements practical in everyday life, turning health monitoring into a seamless part of daily routines.

While electronics provide the backbone for translating chemistry into measurable signals, the choice of sensor defines how ketones are detected. Electrochemical sensors generate currents via redox reactions, optical sensors capture variations in light absorption or fluorescence, and chemiresistive sensors—including semiconductor gas sensors—exploit surface-level conductivity shifts. Each technology offers a unique pathway from molecular interaction to electrical output, setting the stage for circuits to amplify, filter, and interpret the data with precision.

Ketone sensing: The gold standard and beyond

In practice, blood testing is the clinical gold standard, using the enzyme β-hydroxybutyrate dehydrogenase (HBDH) to generate a precise electrical signal from β-hydroxybutyrate (BHB). Keep note that a blood ketone meter functions as a miniaturized potentiostat; it maintains a fixed voltage across the biosensor to measure the current produced by this reaction, providing the data needed to distinguish safe ketosis from metabolic crisis.

Figure 1 Today’s multifunction blood meter kits provide a fast and reliable method for measuring β-ketone, blood glucose, and other parameters from fresh whole blood samples in just a few simple steps. Source: eLinkCare

However, the field is evolving beyond the invasive finger-prick. Researchers are now optimizing alternative biomarkers and delivery methods to bridge the gap between clinical accuracy and user convenience.

Exhaled breath analysis targets acetone—a volatile byproduct of fat metabolism. Current technologies, such as chemiresistive metal-oxide sensors, offer a high-frequency, non-invasive “proxy” for ketosis. While breath analysis currently lacks the clinical precision required for acute emergencies like diabetic ketoacidosis (DKA), it provides a sustainable, pain-free alternative for routine wellness tracking.

In a nutshell, ketone breath analyzers typically employ semiconductor-based, chemiresistive sensors to detect acetone—a byproduct of fat metabolism—in exhaled breath. These sensors function by measuring changes in electrical resistance triggered by volatile organic compounds (VOCs), which serves as a proxy for blood ketone concentration. High-end models often integrate CMOS technology to enhance both sensitivity and measurement precision.

Figure 2 Ketone breath analyzers and subcutaneous sensors deliver real-time feedback on ketosis levels. Source: Author

Continuous ketone monitoring (CKM) is an emerging technology that utilizes a small subcutaneous sensor—similar to a continuous glucose monitor (CGM)—to measure BHB levels in the interstitial fluid. By providing real-time data and automated alerts, these devices aim to detect rising ketone levels before they escalate into metabolic emergencies, effectively transitioning patient care from ‘spot-check’ diagnostics to continuous, proactive health management.

Note that a subcutaneous sensor is a tiny, flexible filament inserted into the fatty tissue just beneath the skin. By monitoring the interstitial fluid in this layer, the sensor uses enzymes to measure specific chemical markers—like glucose or ketones—and converts those readings into a continuous digital stream. Because it stays in place for several days and does not require venous access, it offers a painless, real-time alternative to repeated finger-prick testing.

Electronic biosensing for makers

To wrap this up, remember that while the medical industry uses highly proprietary, pre-calibrated systems, the underlying principle is a fantastic playground for makers.

Whether you are working with a glucose oxidase strip for blood sugar or a β-hydroxybutyrate strip for ketone levels, the principle is the same: enzyme-mediated reactions generate electrons that must be measured against a stable reference potential.

Once you master the transimpedance amplifier (TIA), you have essentially built the core of a professional-grade diagnostic instrument. In fact, most commercial biosensors integrate the TIA and supporting circuitry into an analog front end (AFE), which delivers low-noise performance and simplifies design, an approach that makers can emulate at smaller scale when experimenting.

On a related note, amperometry is the electrochemical technique at the heart of most biosensor strips. It involves applying a fixed potential to an electrode and measuring the resulting current, which is directly proportional to the concentration of the analyte.

In glucose oxidase strips, the enzymatic reaction produces hydrogen peroxide that is oxidized at the electrode, while in β-hydroxybutyrate strips, NADH transfers electrons through a mediator. In both cases, the transimpedance amplifier converts this tiny current into a usable voltage signal, enabling accurate, low-noise measurement.

Figure 3 Quick view shows a closeup of a standard ketone blood tester strip. Source: Author

For those curious about non-chemical ketone monitoring, it’s worth noting that hobbyists have also experimented with MQ13x series gas sensors such as MQ138 to approximate acetone levels in breath.

These gas sensors are not medical-grade and require careful calibration against known standards, but they can respond to volatile organic compounds in exhaled breath. Pairing one with a microcontroller, a stable heater supply and signal conditioning circuitry give you a rough, experimental ketone breath analyzer. It’s a fun proof-of-concept project—ideal for learning sensor physics and electronics.

Figure 4 MQ138 sensor module helps detect acetone in exhaled breath, enabling experimental DIY ketone analysis. Source: Author

Just keep in mind that for any real-world health tracking, these DIY setups should be for educational exploration only. Medical-grade devices undergo extensive clinical validation to handle variables like hematocrit levels, temperature, and signal interference—factors that a prototype might miss.

Finally, do not let the complexity of biomedical electronics intimidate you. Every expert once started as a novice tinkering with circuits and sensors. Dive in, experiment boldly, and let curiosity be your guide—the frontier of electronic biosensing is wide open for makers willing to explore.

T. K. Hareendran is a self-taught electronics enthusiast with a strong passion for innovative circuit design and hands-on technology. He develops both experimental and practical electronic projects, documenting and sharing his work to support fellow tinkerers and learners. Beyond the workbench, he dedicates time to technical writing and hardware evaluations to contribute meaningfully to the maker community.

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The post Electronic biosensing: A quick take on ketone detection appeared first on EDN.

Three smart home hubs, from two different companies. All supporting both 2.4 GHz Wi-Fi and proprietary 900 MHz wireless links. How do they differ, and are similar? Let’s find out.

Last month, I told you about TP-Link’s Tapo Hubs and their functional similarity to Blink’s Sync Modules. And last week, I took apart Blink’s second-generation hub, comparing it to its premiere predecessor which’d gone “under the knife” nearly a decade earlier. Today, I’ll be dissecting the entry-level Tapo H100 hub I conceptually covered in late March.

How comparable (or not) is its design to those of its Blink competitors? Let’s dive in and see.

Smart hub brothers from different mothers?

I shared a full set of outer box shots last month; so to avoid redundancy, this time I’ll show only the perspective that’s different, since last month’s device remains in ongoing use while this one (with a different serial number) is intended (initially, at least) solely for dissection.

As usual, it’s accompanied by a 0.75″ (19.1 mm) diameter U.S. penny for size comparison purposes. Also note that, per the common “US/1.26” notation on the sticker found on the bottom of both boxes, this device and last month’s H100 are presumably based on the same hardware version.

Opening up the packaging, you’ll find a sliver of literature inside, with our patient below it.

The only constant is change

On the product support page I initially referenced earlier, you’ll also discover that there have been four hardware versions to date: v1.0, v1.2, my v1.26, and the subsequent (I’m assuming) v1.8. Attempts to mix-and-match divergent hardware, as I’ve noted before, can be problematic. That said, most households will contain only a single hub device (versus multiple sensors and other “smart” peripherals), minimizing the potential-problem set size in this particular case.

Before continuing, let’s revisit the backside of the device, this time zooming on the markings.

Notice what looks like a label stuck on top of part of the original info? That’s exactly what it is.

As it turns out, the FCC ID found on the backside markings (2AXJ4H100) was also later updated; it’s now 2BH7FH100. Are the two changes related? Dunno.

Time to dive inside, a task that, compared to TP-Link smart switches of (recent) past, was thankfully fairly straightforward this time around.

Inside the front half of the enclosure, you’ll find a speaker (used, for example, to implement the sound emitted when the hub is paired with, and activated by, a “smart” doorbell).

And the mechanical assembly for the pairing-and-reset switch is shown on one side, as seen earlier.

Categorizing the guts

Here, however, is the view that most of you are most interested in, I guess.

The bottom half of the PCB disconnected itself from the back half of the enclosure while I was prying apart the two halves.

Further bending back the PCB reveals how the AC “prongs” connect to it.

As well as the PCB backside itself.

The small five-lead IC in the middle, PCB-labeled U4, is marked:

TACeY1

Its identity is unknown to me (readers?). Below it, in a larger seven-lead package, is On-Bright Electronics’ OB2512NJP offline primary-side-regulation (PSR) power switch. Below that is a M7 high voltage rectifier diode. And to its left is another (bridge and three-lead, this time) rectifier, Galaxy Microelectronics’ MBF10M.

Back to the PCB front side, after “un-popping” the PCB (putting it back in its normal place within the enclosure, which is upside down in both the prior-version and the following photo versus its normal orientation).

Note first the two antennae, one embedded and along the lower edge, the other discrete and along the right side. I assume one’s for 2.4 GHz Wi-Fi while the other supports TP-Link’s proprietary 900 MHz ISM band “ultra-low power wireless protocol”. Reader suggestions as to which is what are greatly appreciated in the comments.

In the upper right (again, lower left in normal operating orientation) is the status LED, which ends up shining out the device front cover. The pairing-and-reset switch is along the left side. The top half of the PCB, perhaps obviously given the sizeable transformer, houses the AC/DC conversion circuitry (the fact that the AC prongs are directly behind it at the rear of the device is another functional tipoff).

And, last but not least, the various ICs. In the lower right corner of the transformer is an Eon Silicon Solution EN56Q64-104HIP 64 Mbit serial flash memory, which we’ve seen before in both higher and lower capacities. I assume it houses the code for Realtek’s RTL8710CM SoC below and to its left, also found in the first two of the three TP-Link smart switches I’ve dissected so far. At the bottom, in the middle, is WayTronic’s WT588F02B audio DSP with an integrated DAC, which “can directly drive 8R 0.5W speakers”, an unsurprising function given the speaker connection directly to the left of it. Above and to the right of the audio DSP is another IC I can’t ID:

35UT
\n53C1

And above and to the left of the mono speaker connector is one final mystery:

300A
\nS992
\n515

Reader insights into any of the chips I was unable to identify, as well as broader thoughts on anything I’ve discussed here, are always welcome in the comments.

Brian Dipert is the associate editor, as well as a contributing editor, at EDN.

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The post TP-Link’s Tapo H100: Smart sensing unencumbered appeared first on EDN.

A single microcontroller can interface with many other components and handle several different tasks — that’s kind of the whole point. But microcontrollers do have limits and sometimes it makes sense to divvy up tasks to get a logical system architecture. That led Michael Rigsby to put a whopping 11 different Arduino boards into his trash-handling robot.

This robot, called Zeno, responds to voice commands and can “see” its environment, all to accomplish the goal of collecting trash and depositing that trash into a specified receptacle. The user simply wakes Zeno with a voice command, then they can tell Zeno to follow them or grab trash from their hand.

Zeno’s two DFRobot HuskyLens AI cameras enable it to recognize people and marked trash bins, while five VS53L0X ToF distance sensors help it avoid obstacles. It has two driven wheels actuated by geared DC motors, plus a pair of serial-controlled servo motors for the gripper. That gripper mounts on an arm that rotates on another servo and extends with a 10” linear actuator.

That is a lot of hardware to control, but it could still be done with just a couple of Arduino UNO boards or maybe even a single Arduino Mega 2560 — if you were trying to optimize for efficiency/cost and made use of all of the available pins. Rigsby, however, chose to structure things differently. He dedicated an UNO Rev3 to each subsystem, with a Mega 2560 acting as a central controller. Each HuskyLens, for example, has its own UNO Rev3 that doesn’t do anything else.

When space and cost aren’t an issue, this kind of architecture can be sensible. It let Rigsby keep the subsystems self-contained, so each Arduino’s sketch and wiring is simple and manageable. But when all of the Arduino boards work together, they can accomplish the complex behavior we see from Zeno.

The post This trash-handling robot contains a whopping 11 Arduino boards appeared first on Arduino Blog.

Many Bluetooth Low Energy (LE) applications depend on reliable, high‑throughput data transfer between connected devices. Typical use cases include over‑the‑air (OTA) firmware updates, sensor data streaming, and bulk data transport between embedded systems. Although the Bluetooth LE specification defines clear upper bounds on achievable data rate, measured throughput in real systems often falls well below these limits.

This discrepancy is not caused by a single factor. Instead, it arises from the interaction of connection‑event timing, controller scheduling behavior, protocol stack implementation, and radio‑frequency conditions.

While modern Bluetooth LE devices commonly support Data Length Extension (DLE), the 2-Mbps Physical Layer (PHY), and large Attribute Protocol (ATT) Maximum Transmission Unit (MTU) sizes, these features alone do not determine achievable throughput.

This article focuses on the practical constraints that shape Bluetooth LE Generic Attribute Profile (GATT) write throughput in deployed systems and explains why throughput behavior is frequently non‑linear and platform‑dependent.

Assumptions and test context

To isolate timing and scheduling effects from feature limitations, the analysis presented here assumes a contemporary Bluetooth LE configuration with the following capabilities:

\n
• Support for DLE on both Central and Peripheral
\n
• Use of the 2-Mbps PHY
\n
• A negotiated ATT MTU of 251 bytes
\n
• Transmit‑side buffering sufficient to queue multiple packets
\n
• Use of GATT Write Without Response operations
\n
• A receiver capable of sustaining the incoming data rate without application‑level back‑pressure
\n

GATT Write Without Response is used to minimize protocol overhead and eliminate application‑layer acknowledgments that would otherwise consume airtime and delay buffer reuse. Although this write type omits an explicit GATT‑layer acknowledgment, delivery to the receiver’s Link Layer remains guaranteed by the Bluetooth LE protocol.

Under these assumptions, throughput might be expected to scale directly with the number of packets transmitted per connection interval. In practice, this assumption does not hold.

Theoretical throughput

With Data Length Extension enabled, a single Bluetooth LE Link Layer packet can carry up to 251 bytes of payload. After accounting for Logical Link Control and Adaptation Protocol (L2CAP) and Attribute Protocol (ATT) headers, 244 bytes remain available for application data.

Using the 2-Mbps PHY, the on‑air time for a maximum‑length data packet followed by its acknowledgment is approximately 1.4 ms. If a connection interval could be filled entirely with such packet exchanges, without additional Link Layer procedures or timing gaps, the resulting application‑layer throughput would be approximately 170 KBps.

This value represents an upper bound that is rarely approached in practice.

Connection events and packet scheduling

Bluetooth LE communication occurs within periodic connection events scheduled at intervals defined by the connection interval parameter. During each event, the Central and Peripheral exchange packets until one side terminates the event or the available time expires.

Most controllers support transmitting multiple packets within a single connection event, but the maximum number of packets allowed per event is not specified by the Bluetooth standard and is instead determined by the controller and stack implementation. As a result, packet scheduling behavior can vary significantly across platforms.

This difference is illustrated in Figure 1. In the left‑hand chart, a wireless MCU acting as the Central can pack 20 packets into a 30‑ms connection interval, using most of the available airtime before entering a short end‑of‑event dead time. In contrast, the right‑hand chart shows a smartphone operating as the Central, where the connection‑event length is capped at five packets, even though additional airtime remains available within the same interval.

Figure 1 Packet scheduling within a Bluetooth LE connection interval varies by platform. A wireless MCU Central fills most of a 30‑ms interval with data packets, while a smartphone Central limits the number of packets per connection event, leaving unused airtime. Source: Microchip

Such limits are particularly common on mobile platforms, where power management and radio coexistence requirements constrain connection‑event length. When the number of packets per event is capped, increasing the connection interval does not necessarily increase throughput, because the additional airtime cannot be used for data transmission.

Residual time and end‑of‑event dead time

Two timing effects significantly reduce usable airtime within each connection interval:

\n
• Residual time, which occurs when the remaining interval is too short to accommodate another full packet exchange.
\n
• End‑of‑event dead time, during which the controller prepares for the next scheduled event and does not permit further transmissions.
\n

The impact of these effects is illustrated in Figure 2. The figure shows that a maximum‑length data packet followed by its acknowledgment occupies approximately 1.4 ms of on‑air time. When the remaining portion of a connection interval is shorter than this duration, the controller cannot schedule another packet exchange, even though some airtime remains available.

Figure 2 Residual airtime and end‑of‑event dead time limit packet scheduling at short connection intervals. A maximum‑size packet and its acknowledgment require approximately 1.4 ms, preventing additional transmissions when insufficient time remains. Source: Microchip

The duration of end‑of‑event dead time varies widely between controller implementations and is not explicitly defined by the Bluetooth specification. In many systems, this behavior can only be identified and quantified through direct measurement.

At short connection intervals, residual and dead time consume a relatively large fraction of each interval, limiting the number of packets that can be transmitted. At longer intervals, this overhead can be amortized across additional packets, improving average throughput if packet scheduling is not otherwise constrained.

Non‑linear throughput behavior

Because residual and end‑of‑event dead time depend on internal scheduling thresholds, Bluetooth LE throughput as a function of connection interval is often non‑linear. Small changes in the connection interval can result in unexpected increases or decreases in throughput, depending on how the interval aligns with controller‑specific timing constraints.

These effects are illustrated in Figure 3, which compares measured throughput across a range of connection intervals under different environmental and platform conditions. In the left‑hand graph, an off‑the‑shelf wireless system‑on‑chip (SoC) is evaluated as both Central and Peripheral. Measurements taken in a shielded environment (orange) show consistently higher throughput than those collected in an open office (blue), indicating the impact of ambient interference on achievable performance.

Figure 3 Measured throughput versus connection interval illustrates non‑linear behavior and environmental sensitivity. Results from both a wireless SoC platform and a Zephyr GATT throughput test show higher throughput in low‑interference conditions and increased variability at longer intervals. Source: Microchip

The right‑hand graph, derived from a Zephyr GATT throughput test, reinforces this behavior while also highlighting the non‑linear relationship between connection interval and throughput. As the interval increases, throughput does not scale monotonically; instead, it exhibits discontinuities and increased variance, particularly at longer intervals where residual and dead time are amortized over more packets.

These results emphasize that throughput cannot be predicted solely from the Bluetooth LE specification. Instead, it’s strongly influenced by platform‑specific scheduling behavior and the prevailing radio‑frequency environment.

Impact of interference

Longer connection intervals typically improve throughput in clean radio‑frequency environments by amortizing residual airtime across additional packets. However, they also increase sensitivity to interference. During long connection events, many packets may be transmitted back‑to‑back; if packet loss or repeated cyclic redundancy check errors occur early in the event, some controllers terminate the event prematurely.

When this occurs, a substantial portion of the connection interval may remain unused, resulting in a sharp reduction in throughput. Shorter connection intervals limit the amount of airtime lost when errors occur and often produce more consistent throughput in noisy environments, albeit with a lower theoretical maximum.

While parameters such as PHY speed, MTU size, DLE, and GATT characteristic length are largely fixed in modern Bluetooth LE systems, connection‑event timing and controller behavior ultimately determine achievable throughput.

The connection interval remains the primary tuning parameter, but its effect is non‑linear and highly dependent on implementation details. For systems that limit packet count per connection event, selecting an interval that closely matches the allowed packet budget is critical. When longer events are supported, throughput gains must be weighed against increased sensitivity to interference.

For design engineers, optimizing Bluetooth LE throughput requires empirical evaluation and platform‑specific characterization rather than reliance on specification‑level performance limits. At a practical level, this places increased importance on controller implementations and protocol stacks that offer fine‑grained configurability on both the Central and Peripheral sides, enabling precise control over connection parameters, event length, and buffering behavior.

Wireless MCU platforms, such as Microchip’s PIC32‑BZ6 multiprotocol wireless MCU family, are representative of designs that emphasize this level of stack configurability and visibility. By allowing engineers to tune behavior symmetrically on both ends of the link and observe the resulting timing effects, such platforms can simplify the process of analyzing throughput bottlenecks and optimizing data transfer performance under real‑world operating conditions.

The ability to measure connection‑event timing, packet scheduling, and error behavior at the controller and stack levels enables more repeatable, data‑driven throughput characterization during development.

Patrick Fitzpatrick is senior technical staff engineer for software at Microchip’s Wireless Business Unit.

Related Content

\n
• Bluetooth low energy (BLE) explained
\n
• The basics of Bluetooth Low Energy (BLE)
\n
• Bluetooth 5 variations complicate PHY testing
\n
• Why Industrial Operations are Turning to Bluetooth Technology
\n
• Secure Bluetooth LE adoption on rise in automotive applications
\n

The post Bluetooth LE throughput: Why real‑world performance falls short of specs appeared first on EDN.

Part of Diodes’ RobustISO family, the API782x series of dual-channel digital isolators delivers 5.7-kV_RMS isolation for 1 minute per UL 1577. The devices offer reliable protection for digital control and communication signals in solar inverters, motor control, industrial automation, and data center equipment.

The API782x series meets reinforced and basic isolation requirements across multiple standards, including VDE, UL, and CQC. The devices are rated for an 8-kV peak isolation voltage per DIN VDE 0884-17 and a 12.8-kV peak surge isolation voltage for transient events. Based on Diodes’ reliability calculations for the capacitive isolation barrier, the components offer a predicted operational lifetime exceeding 40 years.

The isolators support data rates up to 100 Mbps and provide a minimum CMTI of 150 kV/µs. The API7820 features both channels in the same direction, while the API7821 provides both channels in the opposite direction with either a high or low default output state. They operate from a 2.5-V to 5.5-V supply voltage and typically consume 2.1 mA per channel at 1 Mbps.

API782x isolators in SO-16WW packages are available through Diodes’ authorized distributors.

API782x product page 

Diodes

The post Digital isolators strengthen industrial systems appeared first on EDN.

The Vishay WLKN-000 two-way Wilkinson power divider/combiner operates from 15 GHz to 20 GHz, centered at 18 GHz. By integrating a resistor with the transmission lines, the compact surface-mount device simplifies system design and saves space in aerospace, defense, and 5G/6G connectivity applications.

Low insertion loss of <0.5 dB below 19 GHz—said to be one of the industry’s lowest­—and return loss of 10 dB to 15 dB enhance system efficiency by reducing power dissipation throughout the signal path. Unlike narrowband or resistive splitters, the WLKN-000 offers high output-to-output isolation of <20 dB at the center frequency. This limits crosstalk, protects downstream amplifiers during combining, and maintains stable performance across parallel RF paths.

The thin-film device operates over a temperature range of −55°C to +155°C, supporting reliable performance in challenging environments. Applications include automotive ADAS, radio transceivers, LEO satellites, base station terminals, drones, weapons guidance systems, and phased-array radar systems.

Samples of the WLKN-000 in 1817 SMD packages are available now; production quantities have a lead time of 20 weeks.

WLKN-000 product page 

Vishay Intertechnology 

The post Wilkinson divider/combiner reduces insertion loss appeared first on EDN.

Littelfuse’s TDB series of miniature DIP switches uses a 1.27-mm half-pitch, surface-mount design to reduce PCB footprint. The compact devices support high-density layouts where space, reliability, and manufacturability matter.

The switches are available in 2-, 4-, 6-, 8-, and 10-position SPST configurations, with body lengths ranging from 3.67 mm to 13.83 mm depending on position count. Contact ratings of up to 50 VDC, 100 mA (steady state) and 24 VDC, 25 mA (switching) make them suitable for low-power industrial control, as well as consumer IoT and smart home devices. Contact resistance is 100 mΩ maximum, and insulation resistance is 100 MΩ minimum at 100 VDC.

Compatible with automated SMT assembly, the switches feature gold-plated bifurcated contacts and top tape sealing for post-reflow washable processing. They offer a mechanical and electrical life of 1000 cycles and operate over a temperature range of –40°C to +85°C.

The TDB series switches are available in tube or tape-and-reel packaging for high-volume production. Samples can be obtained through authorized Littelfuse distributors.

TDB series product page 

Littelfuse

The post SMT DIP switches fit space-constrained PCBs appeared first on EDN.

With Keysight Assembly simulation software, automotive manufacturers can virtually test shop-floor processes to identify issues early in development. Late-stage assembly failures drive delays, rework, and recalls. By delivering early insight and integrating with existing ecosystems, the software improves body-in-white assembly workflows.

Developed with automotive OEM partners, Keysight Assembly enables engineers to replicate processes such as part positioning, clamping, and spot welding through guided workflows and templates—without requiring finite element modeling (FEM) expertise. It also provides early visibility into distortion and dimensional risks, shortening production timelines and improving build accuracy.

Keysight Assembly integrates with Keysight’s stamping simulation software, allowing engineers to carry stamped-part data across the process—from forming through assembly—and validate outcomes against pre-production scan data. It also integrates with CAD, product lifecycle management (PLM), Excel, and existing digital workflows without disrupting established practices.

Learn more about Keysight Assembly and related webinars here.

Keysight Technologies  

The post Simulation tool tests assembly processes upfront appeared first on EDN.

Deepak Shankar, founder of Mirabilis Design and developer of VisualSim Architect platform for chip and system designs, has created this cartoon for electronics design engineers.

The post The system architect’s sketchbook: The coherency wall appeared first on EDN.

Deepak Shankar, founder of Mirabilis Design and developer of VisualSim Architect platform for chip and system designs, has created this cartoon for electronics design engineers.

The post The system architect’s sketchbook: The AI hiring frenzy appeared first on EDN.

Four cameras, from two companies. Similar at first glance. Quite different once you zoom in and ponder the picture a while. Which approach is superior? Share your opinions in the comments!

The way this is going, and to remain honest both with myself and all of you, I’m at least for now going to need to start referring to myself as a “camera collector” versus a photographer. I keep accumulating particularly noteworthy (therefore also rare) gear when I come across lightly used, but still reasonably priced, examples on eBay and elsewhere. But I can’t seem to find any spare time to actually use anything in my steadily expanding hardware inventory…at least not yet.

Will I ever be able to retire?

First World problem. I know. My latest examples of acquisition excess fall into the “pocketable” camera category. First off are two Pentax devices. As regular readers may recall from my past writeups, I’m nearing a half-century as a “Pentaxian”, a term originating on a t-shirt I snagged at the company’s CES booth a “few” years ago, prior to the brand’s acquisition by Ricoh. The new-to-me cameras are both members of the company’s “Q” product series: a first-generation Q:

and the successor Q7, skipping (at least so far) the in-between Q10 as well as the Q-S1 concluding iteration. I’d long known about the Q family, which originated a decade-and-a-half back, but enthusiastic reviews from folks such as Micro Four Nerds (the prior blog link is supplemented by the following video) tipped me over the acquisition edge:

Key differences between my two Pentax Q-series cameras include:

\n
• Sensor size: 1/2.3″ on the Q, 1/1.7″ on the Q7, albeit both delivering 12 Mpixel resolution. By the way, the origin of this particular sensor dimension terminology is a story in and of itself, which I’ll save for another day; for now, see here.
\n
• Body construction: Magnesium alloy on the Q, (still-rugged) plastic on the Q7
\n

Note too, for comparison-to-come purposes, that neither model embeds an electronic viewfinder (EVF), although they both include both a pop-up flash and a hot shoe tailored for an optional external flash unit (which can operate in tandem with the pop-up) or a transmitter.

Potato, potahto (or tomato?)

Then I came across Chris Niccolls’ extensive writeup, “The Panasonic Lumix GM-5 Is the Greatest Digital Camera Ever Made”, along with an associated video, at PetaPixel:

Insert hook and reel me in. Regular readers may also recall I’ve been slowly-but-steadily collecting Micro Four Thirds (M43) gear in recent years, now spanning a “few” cameras from two suppliers (Olympus-now-OM System and Panasonic; the Blackmagic Design video cameras I own are both higher-end Canon EF mount-based models), one of which ended up as a gift for my wife. Well, my stable is now even fuller; I bought both a Panasonic Lumix DMC-GM1:

and the successor DMC-GM5:

both of which are also more than a decade old at this point. Here’s another Micro Four Nerds review writeup-plus-video combo, this time focused (bad pun intended) on the GM1:

along with a coverage content tandem on the GM5 (to be clear, I have no affiliation with Micro Four Nerds or any other “influencer” showcased here; I’m just a fan):

Notable differences between the two models include the following:

\n
• Supplemental illumination: pop-up built-in flash on the GM1 (but no hot shoe), hot shoe (but no integrated flash) on the GM5, and
\n
• Viewfinder: backside LCD only on the GM1, added EVF (electronic viewfinder, space-supplanting the predecessor’s pop-up flash) on the GM5
\n

Sensor inconsistencies

Although the four cameras, from two manufacturers’ model lines, are conceptually similar (“pocketable”), their respective implementations are quite different. The inherent tradeoffs leading to each development team’s decisions and resultant product capabilities and limitations are interesting (IMHO at least) to ponder. Note that I have no company-representative insight, either quotable or off-the-record; what follows are just my educated guesses.

As already mentioned, my two Pentax Q variants’ image sensors are both 12 Mpixel in resolution, albeit with differing dimensions; the ~60% larger-area of the Q7’s sensor translates into improved low-light performance and wider dynamic range thanks to expanded pixel pitch and other factors. Conversely, the Panasonic GM1 and GM5’s image sensors are, as far as I can tell, identical, with 16 Mpixel resolutions. That said, M43 image sensors have roughly 9x the surface area of the 1/2.3″ sensor in the Pentax Q, and are still approximately 4x larger (again, surface area, not necessarily active image capture area) of the 1/1.7″ sensor in the Pentax Q7.

Stabilization tradeoffs

All four (total, including my two) Pentax Q family members also supported in-body image stabilization (IBIS), in and of itself a curious choice given the lightweight bodies and accompanying lenses, all of which would seemingly diminish the need for mechanical stabilization of any sort. To wit, neither Panasonic camera mentioned here implements IBIS, nor did any Panasonic-branded M43 lenses support optical image stabilization (OIS), at least at the time that the GM1 and GM5 were in production.

That said, M43 partner then-Olympus did have OIS-inclusive optics in its “glass” portfolio at the time, which could as-needed be used on Panasonic bodies given the two manufacturers’ lens mount compatibility. OIS is, generally speaking, inferior to IBIS, although as I’ve previously noted, it’s particularly effective with telephoto lenses. But it’s arguably better than nothing at all, or to interpolation-based digital image stabilization, for that matter.

Here are a couple of example videos discussing the similarities and differences between IBIS and OIS along with concept examples of both IS forms in action, as well as how they can collaborate:

This one from Canon has a Japanese audio track albeit with English subtitles:

Keep in mind, too, that given the Panasonic cameras’ larger-sized image sensors versus the Pentax alternatives, therefore larger pitch pixels despite the 33.3% higher resolutions, image stabilization was inherently less necessary in the M43 case given that improved light-gathering capability translated into the ability to operate them at blur-suppressing higher shutter speeds.

Space constraints

The added stabilization hardware surrounding the image sensor in the Pentax Q-family bodies, coupled with the desire to maintain their compact weight and dimensions, also compelled the company to dispense with a mechanical shutter, at least in the bodies themselves. Instead, a subset of the then-available eight-lens suite embedded mechanical leaf shutters in the lenses. More broadly, an “electronic shutter” implemented in the image sensor was available in all body-plus-lens cases, albeit with “rolling shutter” and other tradeoffs.

A hollow victory?

Ironically, in spite of these likely-difficult tradeoff decisions made by its development team, Pentax still ended up with Q-series camera bodies that were (slightly) larger than that of the Panasonic DC-GM1, as Robin Wong, another well-known photo enthusiast “personality”, notes in his Pentax- and Panasonic-themed blog posts and videos:

I’ve got more to say about the two companies’ contrasting approaches to the “pocketable” camera market, including the tradeoffs between multi-supplier standard and sole-sourced proprietary lens mounts …but I’ll save that for another day and writeup (or few). For now, I’ll wrap up my writeup and hand the keyboard to you for your so-far thoughts in the comments!

—Brian Dipert is the associate editor, as well as a contributing editor, at EDN Magazine.

Related Content

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• The Godox V1 camera flash: Well-“rounded” with multiple-identity panache
\n
• Scrutinizing a camera flash transmitter
\n
• Multi-source vs proprietary: photography case studies
\n
• SD card speeds: question your assumptions
\n
• Tamron’s TAP-in Console: A nexus for camera lens update and control
\n

The post Engineering tradeoffs: a camera case study appeared first on EDN.

Managing IoT devices at scale is hard, but we believe finding the right resources at the right time shouldn’t feel like searching through a haystack! That’s why we built Smart Folders in Arduino Cloud – saved searches that stay alive and update automatically in real-time. This builds on recent improvements announced in Arduino Cloud, including a dark theme and a new Thing page.

What are Smart Folders?

Smart Folders bring dynamic, rule-based organization to Arduino Cloud, an all-in-one platform to bring your IoT projects to life quickly. If you’ve used Smart Folders in macOS or Google Drive, the concept will feel familiar – but we’ve tailored it specifically for IoT fleet management.

Instead of manually organizing resources into static folders that get outdated immediately, you create folders based on criteria that matter to your workflow: device status, location, connection type, or custom keywords. Arduino Cloud automatically populates these folders and keeps them updated as your fleet evolves.

Where you can create Smart Folders

Smart Folders are available across all major IoT listing pages:

\n
• Things
\n\n\n\n
• Devices
\n\n\n\n
• Dashboards
\n\n\n\n
• Triggers
\n

This universal availability means consistent organization across your entire Arduino Cloud workspace.

How to create a Smart Folder

Creating a Smart Folder is straightforward: here’s a quick step-by-step guide.

1. Define your criteria

Use search and filter controls to narrow down your resources. You can combine multiple filter types:

\n
• Keywords: Multiple search strings as individual criteria (press Enter after each)
\n\n\n\n
• Status filters: Device status
\n\n\n\n
• Technical filters: Device type, connection type, timezone
\n\n\n\n
• Metadata filters: Creation date, tags, and attributes
\n

^{Select multiple active filters such as keywords, status, device or connection type}

2. Save as a Smart Folder

Save your filters with a descriptive name. Arduino Cloud immediately creates a folder that automatically includes all matching resources.

^{Arduino Cloud instantly generates a folder containing all matching resources}

3. Manage and refine

Here are the key actions you can take to keep your Smart Folders always functional.

\n
• Duplicate: Create variations quickly
\n\n\n\n
• Edit filters: Adjust criteria when requirements change
\n\n\n\n
• Delete: Remove unused folders
\n

^{The Smart Folder management options menu}

Why Smart Folders matter in Arduino Cloud

^{Your Smart Folders appear at the top}

Traditional folders become stale immediately and require constant manual maintenance. Smart Folders stay current automatically. Add a new device matching existing criteria? It appears in the right folders instantly. Change a device’s status? It moves between folders automatically. Update tags? Your organization adapts in real time.

Watch Marta Barbero, our Lead Product Manager, explain what you can do with Smart Folders in Arduino Cloud.

Getting started 

Smart Folders are available now. Here’s how to start:

1. Log in to Arduino Cloud.
2. Navigate into your IoT builder side bar: Things, Devices, Dashboards, or Triggers.
3. Select the Smart Folder folder icon.

4. Apply filters using search and filter controls.
5. Save as Smart Folder with a descriptive name.
6. Pin important folders to your sidebar for quick access.

Start simple with one or two folders for your most common searches, such as “My Active Projects” or “Offline Devices,” and see how instant filtered views change your workflow!

Try Smart Folders today in Arduino Cloud, as well as our AI Assistant. Share your feedback in the Arduino community forums or reach out to our support team.

Arduino is a trademark or registered trademark of Arduino S.r.l.

The post Organize your IoT fleet in Arduino® Cloud with Smart Folders appeared first on Arduino Blog.

In the automotive industry, “drive-by-wire” means that a traditionally mechanical linkage, like a throttle cable, has been replaced by an electronic actuator. That can eliminate design constraints and even save money. SciFientist was able to apply those same drive-by-wire principles to this 3D-printed micro milling machine.

Machine tools, including vertical mills, are usually either CNC, manual, or power-assisted. In that last scenario, there is usually a simple motor that rotates a lead screw, so the user doesn’t have to crank the handle a bunch of times to traverse long distances. The motor can feed more consistently than a person can as well.

But this 3D-printed micro mill is different, because it entirely replaces the traditional manual cranks with motors and can only be controlled electronically — just like a drive-by-wire car.

Each axis has a lead screw turned by a stepper motor, controlled by an Arduino UNO Rev3 with a CNC Shield. The Arduino moves the motors in response to user input through a joystick and buttons. But in this incarnation, there isn’t any provision for true CNC operation — though SciFientist has plans for a second version with that capability.

What also stands out about this micro mill is its 3D-printed frame. That isn’t rigid at all by machine tool standards, but it should be good enough for the PCB milling that SciFientist plans to tackle with the machine.

While this is just the first step on the way to more conventional CNC milling, the drive-by-wire control is interesting. With linear position feedback on each axis — essentially a DRO— and fine motor movement, it would allow for many of the benefits of manual milling, but in a compact and affordable package that ignores the design constraints of manual mills.

The post A 3D-printed “drive-by-wire” micro mill for your desktop appeared first on Arduino Blog.

Tracking down rodentia (or otherwise)-caused cable cuts, and differentiating them from normal open circuits, is critical. Evolving the circuit design for expanded functionality makes it even more valuable.

It’s just part of the job.  Every design engineer learns early (if not so happily) about the inevitable necessity of detecting, confronting, and swatting “bugs” in circuitry.

Wow the engineering world with your unique design: Design Ideas Submission Guide

In a recent Design Idea, frequent contributor Jayapal Ramalingam extends this art of circuit defect detection and deletion from dealing with mere insects to coping with something much more formidable: rats!

With so many rodents and creatures around the plant, a cable cut can happen at any time

The cables being subjected to those toothy threats transport signals from field contacts monitoring pressure, temperature, valve position, limit switches, manual operator inputs, etc., to process control systems. The possible consequences of mistaking an undetected cable break for an open contact range from the merely inconvenient to the catastrophic. An example of the latter might be a critical valve that’s actually open but erroneously read as closed—viz., Three Mile Island?

Mr. Ramalingam’s clever solution to the problem of undetected cable cuts is a current transmitter design that adds a third current level to the two that are inherent to an ON/OFF contact.  Thusly.

20mA = contact closed, cable intact
\n4mA = contact open, cable intact
\n0mA = cable cut, contact state unknown

It therefore explicitly verifies cable continuity, preventing the mistaking of an open circuit for an open contact. See his article for details.

Mr. Ramalingam’s circuit works, is proven, and has nothing significantly wrong with it.  Its utility, however, is limited to that single function.  It might be significantly more convenient and thrifty if its role could be combined with another in a multipurpose design, provided, of course, that said design would be of no greater cost or complexity than the single-purpose transmitter.  Figure 1 and Figure 2 show such a circuit adapted from an earlier article.

\nFigure 1  0/20mA to 4/20mA current loop converter.

\nFigure 2 Field contact OFF/ON to 4/20mA current loop converter.

Note that the circuits are identical, so that only one design needs to be fabricated, documented, and stocked.

Calibration in this new role is quick and simple and completed in a single pass:

\n
1. Open contact.
\n
2. Tweak 4mA adj for 4mA output.
\n
3. Close contact.
\n
4. Tweak 20mA adj for 20mA output.
\n

Stephen Woodward‘s relationship with EDN’s DI column goes back quite a long way. Over 200 submissions have been accepted since his first contribution back in 1974.  They have included best Design Idea of the year in 1974 and 2001.

Related Content 

\n
• Is your PLC/DCS reading the field contacts reliably?
\n
• Silly simple precision 0/20mA to 4/20mA converter
\n

The post Double-duty current loop transmitter appeared first on EDN.

The Wireless Broadband Alliance (WBA) has released guidelines to strengthen security, privacy, and trust across Wi-Fi networks. These guidelines help organizations reduce exposure to common Wi-Fi threats, improve user trust, and simplify interoperability across networks and partners.

The guidelines also address the growing need for carrier-grade security that aligns with user expectations.

\n
1. Prevent connections to rogue and fake networks
\n

Wi-Fi devices must validate network certificates before sharing credentials by using 802.1X and Extensible Authentication Protocol (EAP). That ensures users connect only to legitimate networks, significantly reducing the risk of evil-twin and rogue access point (AP) attacks.

\n
1. Protect data over the air
\n

Data traffic confidentiality and integrity can be ensured by enforcing WPA2/WPA3-Enterprise with Advanced Encryption Standard (AES) and Protected Management Frames (PMF). That prevents passive sniffing, de-authentication attacks, and many man-in-the-middle techniques, bringing Wi-Fi security closer to cellular-grade protection.

\n
1. Preserve user identity privacy without breaking compliance
\n

Balance privacy and traceability by using anonymous identities, encrypted inner identities, pseudonyms, and chargeable-user-identity (CUI). That protects personally identifiable information during authentication while still enabling lawful intercept, billing, and incident handling when required.

\n
1. Secure credentials end-to-end
\n

Credentials are protected throughout their lifecycle, from device to network to backend systems. Secure OS key stores on devices and hardened credential storage in identity provider systems. So, tamper-resistant SIMs and USIMs for mobile credentials reduce the risk of large-scale credential theft.

\n
1. Harden the entire access network
\n

Security extends beyond the radio link. Physical security of access points and controllers, encrypted AP-to-controller links, secure backhaul design, and local breakout architectures ensure that data traffic remains protected across the full network path.

\n
1. Secure AAA and roaming signaling
\n

This guideline recognizes that the control plane is often overlooked; so, it strongly recommends RADIUS over TLS or DTLS for all AAA and roaming exchanges. That protects authentication and accounting traffic from interception or manipulation, aligning with OpenRoaming and WRIX requirements.

\n
1. Add layer-2 protections against lateral attacks
\n

Layer-2 traffic inspection, client isolation, proxy ARP, and multicast and broadcast controls are employed to limit damage even if a malicious device connects and thus reduce client-to-client attacks such as ARP spoofing and broadcast abuse.

\n
1. Enforce security through federation and governance
\n

Security is reinforced not only technically but operationally through OpenRoaming and the WRIX legal framework. As a result, security requirements, responsibilities, and privacy obligations can be consistently enforced across operators, identity providers, and hubs.

Related Content

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• Securing a wireless network–The basics
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• How to achieve better IoT security in Wi-Fi modules
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• How to make 802.11 systems combine security with affordability
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• 10 things to consider when securing an embedded 802.11 Wi-Fi device
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The post 8 Wi-Fi security guidelines issued by Wireless Broadband Alliance appeared first on EDN.

Multicore processing boosts performance and energy efficiency in many coding situations. Bare-metal algorithms further enhance these benefits.

Many embedded firmware engineers have seemingly not yet tried multicore processing. Using processors with more than one core can actually make your architecture and coding easier. And the part you may find surprising is that setting up and using multicores processors is very easy to do.

Wow the engineering world with your unique design: Design Ideas Submission Guide

Typically, multicore programs are used in systems with an OS, but if you’re like me, my projects are typically bare-metal. I have long used multicore under an RTOS but have historically avoided multicore on bare-metal systems. But ever since I discovered how easy it was to use multicore on bare-metal, it has become part of my go-to design architecture.

Let’s look at how this is accomplished. The examples and discussions that follow are based on using an RP2040 two-core microcontroller with code developed on an Arduino IDE. RP2040 development boards can be found for around $5 USD. Also, although I will discuss a two-core setup, expanding to larger core count processors will use the same concepts.

So why didn’t I use multicore designs sooner? I had some concerns that there were difficulties that I wasn’t ready to take on. Some of these were:

\n
• How to keep each core’s code separate
\n
• How to start multiple cores
\n
• How the cores talk to each other (i.e., how to transfer data among cores)
\n
• What peripherals each core can use; do they need to be checked out or registered, for example
\n

It turns out that all these issues are actually very easy to deal with. Let’s look at them one at a time.

First, how do you separate the code for each core? In a single-core Arduino C program there are two major sections: the setup section (which begins like this: void setup()) and the loop section (which begins like this: void loop()). If you are using two cores, the first core, core 0, will use these sections just as used in a single-core design.

The code for the second core, core 1, will have a function defining its main loop. Let’s name it core1_main. Then in the core 0’s setup section, enter the line multicore_launch_core1(core1_main);. That line will start the function, called core1_main, running on the second core. (Note: I find it much cleaner to put the core 1 code in a separate tab in the Arduino IDE.) Unlike the main loop in an Arduino C program, you will need to wrap the code in core 1 in a while(1); loop. Another item to include is the line #include \"pico/multicore.h\" at the top of the code.

Be aware that there are other approaches for setting up code in the second core. They include methods that allow core 1 to use its own setup function. Use your favorite AI or other research tool to discover other methods of setting up code and executing code on the second core.

Here’s a very simple example having each core blinking its own LED:

#include \r\n#include \"pico/multicore.h\"\r\n\r\n// -----------------------------\r\n// Core 1 code\r\n// -----------------------------\r\nvoid core1_main() {\r\n    pinMode(14, OUTPUT);\r\n\r\n    while (1) {\r\n        digitalWrite(14, HIGH);\r\n        delay(500);\r\n        digitalWrite(14, LOW);\r\n        delay(500);\r\n    }\r\n}\r\n\r\n// -----------------------------\r\n// Core 0 code\r\n// -----------------------------\r\nvoid setup() {\r\n    pinMode(15, OUTPUT);\r\n\r\n    // Start core 1\r\n    multicore_launch_core1(core1_main);\r\n}\r\n\r\nvoid loop() {\r\n    digitalWrite(15, HIGH);\r\n    delay(300);\r\n    digitalWrite(15, LOW);\r\n    delay(300);\r\n}

This example gives you an idea of how to get the two cores executing their own tasks. Typically, though, you would want to have some sort of communication between the cores. This can be achieved very simply by using a variable that each core can see and modify. It turns out that the entire memory space of the microcontroller can be seen and modified by either core. So, if you define a global variable at the top of the code (just below the #include statements), it can be used to transfer data between cores.

Make sure that the variable is tagged as volatile as it can change at any time. Also remember that the RP2040 is a 32-bit microcontroller and reading and writing 64-bit values is not atomic, so care must be taken to not read a transferred 64-bit value before both halves have been transferred. A simple flag can help here. This simple method of using shared memory to transfer data is easy but can be dangerous if you’re not careful—similar to global variables—but bare-metal developers typically like this tight control over resources.

This method of transferring data is good for simple tasks, but you may want to use FIFOs to handle more data and to remove some syncing issues. These are not difficult to write, and you’ll also find pre-written packages online. For more sophisticated programs, you can investigate mailboxes, semaphores, flags, etc. from various sources…but now we’re getting into RTOS functions.

Now let’s look at sharing peripherals between cores. In our bare-metal architecture, the best explanation is that any core can use any peripheral at any time. This situation is both good and bad. Good because there are no flags to set, no checkouts that need to happen, and no negotiations to be made: just use the peripheral. Bad in the sense that without some form of coordination the two cores can attempt to set up the same peripheral at the same time, in different configurations.

What I have found useful in my designs is that I have typically separated the code in the two cores such that each core always uses peripherals that are not used by the other core. If that not the case in your designs, you may want to implement a resource lock method using flags. Related is the interesting fact that both cores can use the serial port (only configured by one core) without any necessary handshaking or flags. Do note, though, that the serial communications will be interleaved. That said, I find this very handy since I can Serial.print() from either core during debugging.

Let’s answer one last question: why do I want to use more than one core? The first reason is the obvious one: you get more computing power. But more than that, by separating tasks from each other you may find coding easier and cleaner. That’s because there are no concerns about the multiple tasks fighting for cycles, especially for time-sensitive tasks. Also, if you are using multiple interrupts, separating these tasks between cores can remove the complexity of interrupts occurring at the same time and thereby holding off one or the other. Another benefit is that you may have faster response to events happening as you can essentially monitor and respond to twice as many events.

Here’s another code example using some of the concepts discussed earlier. This code uses core 1 to monitor the serial port looking for a G or an R. If it sees a G, it sets the shared variable led_color to 1. Core 0 continuously monitors led_color and turns on the green LED if the led_color is 1. Similarly, if core 1 sees a R it changes led_color to 0 and core 0 then then turns on the red LED:

#include \r\n#include \"pico/multicore.h\"\r\n\r\n// ----------------------------\r\n// LED pin assignments\r\n// ----------------------------\r\n#define RED_LED_PIN    14\r\n#define GREEN_LED_PIN  15\r\n\r\n// ----------------------------\r\n// Shared variable between cores\r\n// 0 = RED, 1 = GREEN\r\n// ----------------------------\r\nvolatile int led_color = 0;\r\n\r\n// ======================================================\r\n// Core 1: Serial monitor\r\n// ======================================================\r\nvoid core1_entry() {\r\n    while (!Serial) { delay(10); }\r\n\r\n    while (1) {\r\n        if (Serial.available() > 0) {\r\n            char c = Serial.read();\r\n\r\n            if (c == 'G' || c == 'g') {\r\n                led_color = 1;\r\n                Serial.println(\"Set LED = GREEN\");\r\n            }\r\n            else if (c == 'R' || c == 'r') {\r\n                led_color = 0;\r\n                Serial.println(\"Set LED = RED\");\r\n            }\r\n        }\r\n        delay(2);\r\n    }\r\n}\r\n\r\n// ======================================================\r\n// Core 0 setup\r\n// ======================================================\r\nvoid setup() {\r\n    Serial.begin(115200);\r\n\r\n    pinMode(RED_LED_PIN, OUTPUT);\r\n    pinMode(GREEN_LED_PIN, OUTPUT);\r\n\r\n    // Launch Core 1\r\n    multicore_launch_core1(core1_entry);\r\n}\r\n\r\n// ======================================================\r\n// Core 0 loop — LED logic now lives here\r\n// ======================================================\r\nvoid loop() {\r\n    if (led_color == 1) {\r\n        digitalWrite(GREEN_LED_PIN, HIGH);\r\n        digitalWrite(RED_LED_PIN, LOW);\r\n    } \r\n    else {\r\n        digitalWrite(RED_LED_PIN, HIGH);\r\n        digitalWrite(GREEN_LED_PIN, LOW);\r\n    }\r\n    delay(5);\r\n}

It may now be becoming clearer to you where the benefits lie in using more than one core. Think of something more complex, say, a program that monitors the serial port for modifications to settings, along with a high-speed ADC being read with a tight tolerance on jitter. Having the serial port code running on one core and the ADC code in another core would make this combination much easier to get working cleanly.

Give multicore code design a try! It’s easy, I think you’ll find lots of uses for it, and you’ll also find it makes coding easier and more organized.

p.s. Both pieces of code shown in this article were initially written by CoPilot per author instructions. The author subsequently only made minor modifications.

Damian Bonicatto is a consulting engineer with decades of experience in embedded hardware, firmware, and system design. He holds over 30 patents.

Phoenix Bonicatto is a freelance writer.

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• Multicore architectures, Part 1 – Key drivers
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• Multicore architectures, Part 3 – Communications and memory
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• Multicore architectures, Part 4 – Application specificity
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The post Give bare-metal multicore processing a try appeared first on EDN.

The technology treadmill never stops, and so it goes with Blink’s second-generation hub device versus its predecessor.

Last month, I compared the conceptually similar (and thankfully, concurrent-use RF-compatible) hub-and-spokes approaches used by Blink and TP-Link for their respective battery-operated device ecosystems. Blink’s particular hub implementation, the first-generation Sync Module still in active use at my residence to this very day, doesn’t support local recording storage, only to the cloud, a service which fortunately is free for me (albeit in a somewhat limited-duration fashion) as a legacy customer.

(it’s more recently been moved from my office to the laundry room, and as regular readers know from other recent writeups, that Belkin Wemo smart switch above it is also now DOA)

Gratis capacity for non-geriatrics

But when I saw an inexpensive “for parts only” second-generation Sync Module available for sale on eBay, I still jumped on the opportunity, driven by curiosity. Primary differences between the two generations include, for the more recent model:

\n
• A functionally active embedded USB-A connector, for mating with a flash stick or other mass storage device for local recording storage
\n
• More robust, therefore more responsive, integrated processing, and
\n
• Claimed wider-range Wi-Fi coverage
\n

Turns out the device itself works fine, at least to the degree I’ve tested it so far; I was able to factory-reset it, and the Blink app can now “see” it (although I haven’t yet set it up). The only thing missing was the originally included AC/DC adapter with a micro-USB output, but I’ve got plenty of spares of those already, along with the one currently fueling its same-dimensions precursor in case I ever decide to upgrade in situ. So, let’s dive inside and see what we can learn, both in an absolute sense and relative to the first-gen Sync Module that I took apart…yikes….nearly seven years ago. Shall we?

Here’s today’s patient, as usual accompanied by a 0.75″ (19.1 mm) diameter U.S. penny for size comparison purposes:

All-important FCC ID (2AF77-H2121520):

Micro-USB power input:

and now-functional USB-A data port:

Open sesame

I wish everything I tore down was this easy to open up:

At this point…

Let’s pause a moment for some interesting (at least to me) background info. In re-reading my archaic first-gen teardown verbiage, I noted that I’d written (among other things) the following:

Today’s teardown candidate is that very same Sync Module. The one currently in use with my Blink XT cameras matches their black color; this particular one was purchased standalone off Ebay specifically for teardown purposes and is white (and previously used). Color scheme deviations aside, the two models are functionally identical.

I was right with my “identical” claim, at least with respect to the functional angle. And I’d already noted the color deviation. But further (and more recent) research has enlightened me that there were other (non-functional) hardware differences between my in-use device and the one I took apart, too. Blink actually brought to production multiple main variations of the first-generation Blink Sync Module (including a low-volume initial “launch” iteration), along with region-specific tweaks of each variant reflective of differing RF spectrum regulations:

There have been 5 main revisions of sync modules:

Version 0 which was white and has a (non-functional) ethernet port and (non-functional) USB and BLE (non-functional) available. This was the ‘launch’ era.

 Version 1a which is white and has a (non-functional) ethernet port and (non-functional) USB.

Version 1b which is white or black and has a (non-functional) USB.

Version 1c which can be white or black and has no ports.

These were all the general ‘XT’ era modules.

Version 2 (the current one) which has a functional USB port.

All the modules are currently compatible with each other, but Modules 0, 1a,b,c have support ‘no longer guaranteed’.

However, this isn’t the end of the story, as the boards inside all come in combinations of EU and US and Intl flavors (due to regulatory / radio differences) too!

I’m guessing that the version I tore down back in mid-2019 was a “Version 1a”. I suppose it also could have been a “Version 0”, although I didn’t come across any Bluetooth Low Energy circuitry inside it. The one still in use here is a “Version 1b”.

Intra-generational variation

When the Redditor who wrote the above shared his thoughts four years ago, there may have been only one (initial) version of the Sync Module 2 we’re looking at today. Fast forward to the present, however, there now have been (at least) two. The initial hardware was based on Atheros silicon for both the processor and Wi-Fi module; Blink subsequently switched to NXP-sourced ICs for both the processor and wireless subsystems, the latter this time supporting not only Wi-Fi but also both Bluetooth and BLE.

Onward. Remove two screws:

And the PCB pops right out:

You’ve already gotten a glimpse of the PCB frontside, so in fairness to its backside counterpart, let’s start there with the detailed analysis:

Admittedly, there’s not much of note, unless you’re into passives and embedded traces, that is. At lower left is the reset-and-pairing switch. And to its right is a Winbond W25Q256JV 256 Mbit serial NOR flash memory, presumably for system code storage. For comparisons sake, here’s the comparatively sparse backside of the first-gen Sync Module PCB:

Now flipping the PCB back over…

I didn’t bother expending much effort at peeling the initially stubborn sticker off the processor; I already know from the NXP logo visibly atop the chip in its upper right corner in conjunction with the helpful Wiki reference page I’d found that it’s the second iteration of the second-gen design, employing NXP’s MCIMX6Z0DVM09AB application processor with the following specs:

\n
• ARM Cortex-A7 running Linux
\n
• 900MHz
\n
• SRAM: 128kB
\n
• SPI/UART/I2C
\n
• 96KB bootrom, 128KB internal RAM
\n
• Has Arm TrustZone
\n

That other NXP chip I previously noted is the 88W8987-NYE2 wireless “solution”. Below the processor is an ISSI IS43TR16640BL 1 Gbit DDR2 SDRAM. And at the top center of the PCB is one more notable (albeit tiny) IC. Labeled as follows:

455A
\nCQRX
\n220

It’s Silicon Labs’ Si4455 sub-GHz wireless transceiver, which (as the name) implies implements the proprietary long-range 900 MHz channel that Blink refers to as the LFR (low-frequency radio) beacon.

In closing, here’s the first-generation Sync Module PCB topside for comparisons sake:

And with that, I’ll turn it over to you for your thoughts in the comments!

—Brian Dipert is the associate editor, as well as a contributing editor, at EDN Magazine.

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• Blink: Security camera system installation and impressions
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The post The Blink Sync Module 2: Faster response and local storage, too appeared first on EDN.

Following the introduction of Industry 4.0, power electronics are becoming more significant in both digital and industrial infrastructures. Factories, energy systems, and data centers are getting smarter and more connected. This requires efficient power solutions that offer high power density and can scale with them.

Semiconductors are expected to deliver performance beyond the limits of conventional silicon-based power devices. Wide-bandgap (WBG) materials such as silicon carbide (SiC) and gallium nitride (GaN), as well as novel approaches to designing, packaging, and controlling power devices, are helping achieve the main goals of Industry 4.0: efficiency, flexibility, scalability, and intelligence.

800-VDC power architecture

One of the most significant changes introduced in the power system is the move of data centers to 800-VDC distribution, as detailed in an Nvidia white paper. Traditional systems that use AC and low-voltage DC can’t keep up with the speed and growth needs of AI-based workloads. High-performance computing clusters, especially those that support generative AI and machine learning, demand more power and should use it as efficiently as possible.

By raising the distribution voltage to 800 VDC, operators can reduce the current for a given power level. This approach offers the benefits of reduced I²R losses and the ability to use thinner wires. Overall, efficiency can thus be increased, and more power can be integrated in the same area or volume. The design also becomes less complicated because there are fewer steps in the conversion process.

This new architecture directly affects semiconductor requirements. Power devices need to perform well at higher voltages with minimum loss and support fast switching. Chipmakers and manufacturers are developing power solutions to support Nvidia’s 800-VDC power architecture reference design for next-generation AI factories to improve efficiency and reduce power losses.

To support gigawatt-scale AI factories based on an 800-VDC power architecture, Flex, for example, introduced a new reference design (Figure 1) that integrates power, liquid cooling, and compute capabilities into a modular assembly. This prefabricated solution streamlines the implementation of 800-VDC architectures and, according to the company, enables 30% faster deployment than conventional systems.

SiC semiconductor advances

Due to its physical properties, such as high breakdown voltage, low switching losses, and high thermal conductivity, SiC can operate efficiently and provide high reliability in high-voltage and high-power environments.

At the high-voltage end, SiC devices are going into the multi-kilovolt range. More devices are gaining ratings above 1,200 V, making SiC more common in places where silicon-based power devices used to be the norm.

Navitas Semiconductor recently announced the availability of samples for its 2,300-V and 3,300-V high-voltage SiC products, specifically designed to increase efficiency in AI data centers, power grids, and renewable energy infrastructure. The devices, available in discrete, module, and known-good-die formats, are based on the company’s Trench-Assisted Planar architecture.

This semiconductor structure optimizes electric-field management, significantly reducing voltage stress and improving avalanche robustness compared with traditional trench- or planar-MOSFET designs. It also achieves lower R_DS(on) at high temperatures and better current spreading.

As power devices improve, their packaging becomes increasingly crucial to the overall performance of the system. Newer packages are designed to reduce parasitic inductance, improve thermal management, and handle larger current densities.

These advancements in packaging technology enable higher performance and efficiency gains. Texas Instruments (TI), for example, recently unveiled two isolated power modules for applications from data centers to electric vehicles that require improvements in power density, efficiency, and safety. The UCC34141-Q1 and UCC33420 isolated power modules leverage TI’s IsoShield technology, which copackages a high-performance planar transformer and an isolated power stage, providing functional, basic, and reinforced isolation capabilities.

TI’s proprietary multichip packaging solution claims up to 3× higher power density than discrete solutions in isolated power designs and shrinks the solution size by as much as 70% by packing more power into smaller spaces. Applications range from factory automation PLC modules and EV and powertrain systems to grid infrastructure and rack and server power.

Wolfspeed Inc. has revealed that its 300-mm SiC platform, leveraging patent-pending innovations, is set to become a key material component for AI and high-performance computing (HPC) packaging by the late 2020s. Figure 2 shows a conceptual demonstration of an interposer substrate built on the company’s 300-mm SiC wafer. According to Wolfspeed, the SiC substrate helps to improve the thermal, mechanical, and electrical performance of next-generation packaging structures required by AI and HPC systems.

GaN advances

While SiC excels at high voltages, GaN is suited for low- and medium-voltage applications, especially below 650 V. This semiconductor can switch at high frequencies, up to the megahertz range, with very low power loss, making power converters more efficient and smaller and requiring less cooling.

One important trend in GaN’s growth is integration. For example, Schottky diodes could be incorporated into GaN transistors to reduce losses from reverse conduction and make it easier to build power stages. Following this concept, Infineon Technologies AG has introduced the industry’s first industrial-grade GaN power transistors featuring an integrated Schottky diode.

Traditionally, GaN devices in hard-switching applications suffer from higher power losses due to their large body-diode voltage drop. This issue gets worse during the “deadtime” of a power controller. Engineers previously solved this by adding an external Schottky diode or complex controller tuning, both of which increase design time and costs. The new CoolGaN transistor G5 family solves this by integrating the diode directly into the transistor, reducing deadtime losses and boosting overall system efficiency.

Another important trend is bidirectional switching, where new GaN devices can block current and voltage in both directions. This simplifies converter topologies and requires fewer components. This capability is especially crucial for applications such as energy storage systems, EV chargers, and power-factor-correction circuits.

Renesas Electronics Corp. has introduced the industry’s first bidirectional switch (TP65B110HRU) based on depletion-mode (d-mode) GaN technology (Figure 3). Most current high-power conversion systems rely on unidirectional silicon or SiC switches that block current in only one direction. This limitation forces engineers to design multi-stage circuits or use “back-to-back” switch configurations, which significantly increases component count and reduces overall efficiency.

By integrating bidirectional blocking into one GaN product, this technology enables “single-stage” power conversion. The high switching speed and low stored charge of GaN also enable higher power density and switching frequencies. According to the company, this architecture has demonstrated over 97.5% power efficiency, providing a solution well-suited for AI data centers, on-board EV chargers, and renewable energy applications.

Solid-state transformers

Solid-state transformers (SSTs) are a huge change in how power is transferred and controlled. SSTs are not like ordinary transformers, as they use power electronic converters to modify, split, and control the voltage.

Using this technology, more advanced features become available. These include two-way power flow, real-time voltage management, and the capacity to operate with renewable energy sources. Smart grids, microgrids, and Industry 4.0 all need SSTs that can change rapidly and easily. For SSTs to grow, WBG semiconductors are particularly significant.

For example, Infineon and DG Matrix, a company specializing in SSTs, have partnered to integrate SiC semiconductors into the Interport multiport SST platform. This collaboration aims to modernize the connection between the public grid and energy-intensive applications such as AI data centers, EV charging, and industrial microgrids.

Unlike traditional copper- and iron-based transformers, SSTs are semiconductor-based devices. They are smaller and lighter, accelerating deployment and providing higher power density. Adopting Infineon’s SiC technology, these SST systems achieve improved efficiency and reliability.

The technology enables direct power conversion from medium-voltage grid levels to the low-voltage requirements of modern digital infrastructure. DG Matrix plans to scale toward higher-voltage platforms to support the global rollout of high-performance power infrastructure.

The post Power electronics evolve to maximize efficiency appeared first on EDN.

Electric motors are everywhere—from the cars we drive to the appliances in our homes—but most rely on rare earth magnets that come with high costs and environmental challenges. A new wave of innovation is changing that story. Magnet-free electric motors are proving that smart engineering can deliver powerful performance without depending on scarce materials.

By removing rare earths from the equation, these designs promise cleaner supply chains, more sustainable production, and fresh opportunities for industries ranging from electric vehicles to renewable energy. It’s a shift that could redefine how we think about powering the future.

Why rare earths matter

Rare earth magnets, especially neodymium and dysprosium, have been the secret ingredient behind the compact, high-torque motors that power everything from electric vehicles to wind turbines. Their ability to deliver strong magnetic fields in small packages has made them indispensable in modern motor design.

But there is a catch: mining and processing rare earths is energy-intensive, environmentally challenging, and geographically concentrated in just a few regions of the world. This creates supply chain risks, price volatility, and sustainability concerns that ripple across industries.

By understanding why rare earths became so central to electric motors, we can better appreciate the significance of moving beyond them—and why magnet-free designs are more than just an engineering curiosity. They represent a strategic shift toward resilience, affordability, and cleaner technology.

How do you pull without a magnet

So how do you build a motor without magnets? The answer lies in clever engineering that takes advantage of the natural properties of materials and the geometry of the motor itself. Instead of relying on powerful magnets to create motion, magnet-free designs use principles like reluctance torque—where the rotor naturally aligns with the path of least magnetic resistance—or induction, where currents in the rotor generate the force needed to spin.

These approaches may sound technical, but the idea is simple: by rethinking the fundamentals, engineers can coax motors into delivering the same performance we expect, without the rare earth magnets. The result is a motor that can be lighter, more affordable, and easier to manufacture at scale. And because these designs lean on widely available materials, they sidestep the supply chain bottlenecks that have long plagued magnet-based motors.

Why it matters

Magnet-free motors are not just an engineering breakthrough; they are a practical step toward cleaner, more resilient technology. By removing rare earths, manufacturers can cut costs, ease supply chain pressures, and reduce environmental impact.

The benefits ripple across industries: in electric vehicles, they promise more affordable and sustainable mobility; in renewable energy, they support wind turbines and other systems without relying on scarce materials; and in industrial machinery, they offer reliable performance with simpler, more scalable production.

In short, magnet-free motors matter because they combine innovation with real-world impact, helping power a future that is smarter, greener, and less dependent on limited resources.

Figure 1 Today’s magnet-free electric motors deliver high efficiencies for heavy-duty and commercial vehicle applications. Source: Advanced Electric Machines

Working principles of magnet-free motors

For learners, makers, and anyone with a curious engineering mind, the real excitement lies in how magnet-free motors actually work. Instead of relying on rare earth magnets to generate motion, these designs tap into fundamental physics—using reluctance torque, induction, or clever rotor geometry to produce rotation.

Think of it as guiding the motor to “want” to align itself with paths of least resistance, or harnessing currents induced in the rotor to drive movement. The beauty is that these principles are elegant, scalable, and rooted in concepts every engineer encounters early in their studies. By revisiting the basics with fresh eyes, magnet-free motors show how fundamental science can be reimagined to solve modern challenges.

At their core, magnet-free motors rely on clever ways to generate motion without permanent magnets, using principles that every curious engineer can appreciate.

That is, reluctance motors exploit the tendency of a rotor to align with the path of least magnetic resistance, producing torque through geometry rather than magnets. Induction motors create rotation by inducing currents in the rotor with alternating fields, a design that is simple yet powerful. Synchronous reluctance motors combine aspects of both, offering efficiency and control that rival traditional designs.

Each approach shows how fundamental physics—magnetic fields, current flow, and mechanical alignment—can be harnessed in different ways to achieve the same goal: reliable rotation. For learners, makers, and innovators, these principles are a reminder that rethinking the basics can unlock new possibilities for sustainable engineering.

Figure 2 A synchronous reluctance motor demonstrates magnet‑free operation with smooth torque characteristics. Source: ABB

It’s important to note that not all reluctance motors are the same. A synchronous reluctance motor (SynRM) runs in step with the supply frequency, using flux barriers in the rotor to align with the path of least magnetic resistance, delivering smooth torque and efficiency. A switched reluctance motor (SRM), by contrast, relies on sequentially energizing stator phases to pull a simple steel rotor around; it’s rugged and powerful but tends to be noisier with more torque ripple.

Sitting between these designs is the permanent magnet assisted SynRM (PMA‑SynRM), which adds small magnets to stabilize the field and boost efficiency while still using far fewer rare earths than traditional permanent magnet motors. Together, these variations show the spectrum of approaches engineers use to balance performance, simplicity, and sustainability.

Unlocking SynRM performance with VFDs

While SynRMs deliver smooth torque and efficiency, they typically need a variable frequency drive (VFD) to start and stay synchronized with the stator’s rotating field. The VFD supplies control frequency and voltage, making these motors flexible but dependent on modern power electronics.

By contrast, older induction motors could start “across the line”—plugged directly into the grid—though at the cost of high inrush currents and less precise control. This reliance on VFDs underscores how magnet-free motor innovation is inseparable from advances in drive technology, reminding designers that motor and electronics progress go hand in hand.

As a worthy side note, VFD is the electronic brain that makes modern motors flexible. By adjusting the frequency and voltage, it lets a motor start gently, avoid the punishing inrush currents of direct grid connection, and run at variable speeds with precision. For SynRMs, the VFD is essential—it keeps the rotor locked in sync with the stator’s rotating field. Older induction motors could start “across the line” without such electronics, but that simplicity came at the cost of efficiency and control.

Figure 3 A compact VFD module suitable for driving 3-phase SynRM motors supports efficient control in both industrial and household applications. Source: Mean Well

From a design standpoint, the dependence on VFDs is both enabling and constraining. On the enabling side, drives unlock efficiency gains, smoother torque, and precise speed control that make SynRMs competitive with permanent-magnet machines.

On the constraining side, they add cost, require integration expertise, and shift part of the reliability burden from the motor to the electronics. For engineers, it means evaluating magnet-free motors is not just about rotor geometry; it’s about the total system, where sustainability benefits must be balanced against drive complexity and lifecycle economics.

Note that modern control strategies such as field-oriented control (FOC) and sensorless vector control extend the capabilities of these VFDs. FOC regulates stator currents to deliver precise torque and flux, while sensorless vector methods estimate rotor position without mechanical sensors, reducing cost and improving reliability. Together, they allow SynRMs—and other magnet-free designs—to match the responsiveness and efficiency of permanent-magnet machines.

Quick FOC take: Field‑oriented control does not have to be daunting. For makers eager to experiment, compact FOC shields/modules provide a straightforward, low‑power entry point. The Arduino SimpleFOC Shield is a practical example, lowering barriers and making hand-on exploration accessible.

Figure 4 SimpleFOC Shield empowers accessible FOC experimentation for Arduino users. Source: Author

Next, getting into design significance, the combination of magnet-free motor design, advanced VFDs, and intelligent control strategies has broad implications. Engineers gain access to motors that are lighter, more affordable, and easier to manufacture at scale, while sidestepping rare-earth supply chain constraints.

In the long run, magnet-free motors not only reduce dependence on scarce materials but also align with global sustainability goals, positioning them as a cornerstone of next-generation electrification across industries spanning from manufacturing to consumer appliances.

Closing thoughts

Magnet-free motors are steadily moving from concept to reality, driven by both maker ingenuity and industry ambition. With BMW and Mahle advancing externally excited synchronous motors to reduce rare-earth dependence, and Tesla having already demonstrated the scalability of induction motors, the message is clear: sustainable propulsion can deliver performance without compromise.

For makers and engineers alike, this is an invitation to experiment boldly and rethink motor design fundamentals, because the next leap in innovation may emerge as much from a personal workbench as from an automotive R&D lab.

T. K. Hareendran is a self-taught electronics enthusiast with a strong passion for innovative circuit design and hands-on technology. He develops both experimental and practical electronic projects, documenting and sharing his work to support fellow tinkerers and learners. Beyond the workbench, he dedicates time to technical writing and hardware evaluations to contribute meaningfully to the maker community.

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The post Magnet-free electric motors: Driving innovation beyond rare earths appeared first on EDN.

Flagship consumer electronic device launches are among the most operationally complex events in modern engineering. They require years of coordination across hardware, silicon, RF, software, operations, supply chain, and manufacturing. Yet, despite mature processes and experienced teams, flagship programs remain vulnerable to schedule volatility.

The root cause is rarely inadequate engineering talent. More often, it’s structural. Manufacturing realities are integrated too late into architectural decision-making. System-level validation, when deployed early and continuously, functions not as a downstream quality checkpoint, but as an organizational mechanism for compressing schedule risk before capital and timeline commitments are locked.

Financial exposure at flagship scale

At flagship scale, schedule slip is not simply an engineering inconvenience. It’s a material financial event.

Apple’s fiscal year 2025 results reported approximately $416 billion in annual revenue, with iPhone revenue representing roughly half of total sales. Samsung’s Mobile Experience division reported approximately $26 billion in quarterly revenue during. For programs operating at this scale, a one-month delay during a peak launch cycle can defer revenue comparable to the annual revenue of many mid-sized technology firms.

Even outside tier-one OEMs, launch timing directly impacts channel readiness, carrier alignment, ecosystem momentum, and competitive positioning. In high-volume hardware, schedule is strategy.

The challenge is that many launch delays are not caused by unforeseen global disruptions, but by late-stage design changes triggered during production ramp. Industry analyses consistently show that a significant portion of late engineering change orders originate from integration and manufacturability issues that were technically detectable earlier in the development cycle.

When these issues surface during ramp, optionality has already collapsed. Tooling is frozen, suppliers are capacity-allocated, and marketing calendars are committed. At that stage, validation confirms risk rather than preventing it.

Why component-level validation fails at scale

Traditional validation strategies are optimized for component correctness. Subsystems are tested against modular specifications, and readiness decisions are based on aggregated subsystem pass rates. This approach ensures that parts function independently; however, it does not guarantee that the system functions reliably under real-world, high-volume conditions.

Many failure modes emerge only during full-system interaction. Digital signal interference, RF coexistence conflicts, thermal coupling between tightly integrated subsystems, and parasitic effects often cannot be fully replicated in isolated bench testing.

For example, a high-speed display flex cable may pass standalone signal integrity validation. During system-level engineering verification testing (EVT) under real RF load, that same cable can radiate broadband noise that desensitizes the primary cellular receiver. The result is a coexistence failure that frequently forces late-stage shielding changes or mechanical redesign.

Similarly, assembly processes introduce stress, tolerance stack-up, and handling variability that are absent in early prototypes. Component-level validation ensures parts are defect-free. It does not predict how those parts behave when integrated and manufactured at scale. The consequence is predictable: issues emerge when yield sensitivity tightens during ramp.

A defect observed in 1 out of 100 early validation units translates into 10,000 defective devices at a one-million-unit scale. At millions of units, small deltas compound rapidly.

The design–manufacturing impedance mismatch

A recurring root cause of late-stage validation failures is misalignment between design optimization and manufacturing constraints. Design teams optimize for performance, power efficiency, compact form factor, and cost targets. Manufacturing teams optimize for yield stability, throughput, repeatability, and process capability. Both are correct within their domains.

Failure occurs when manufacturing sensitivity is not structurally integrated into architectural trade-off decisions. In cross-functional reviews, performance metrics are often presented without quantified yield sensitivity analysis. Design freeze decisions may proceed based on functional validation, while manufacturing risk remains probabilistic rather than modeled. Schedule pressure can incentivize accepting integration risk with the assumption that ramp will resolve residual issues.

System-level validation acts as the translation layer between these domains. When embedded early, it exposes divergence between design intent and production feasibility while design changes remain affordable. The cost-of-change curve, widely cited in engineering economics literature, demonstrates that defects discovered during mass production can cost orders of magnitude more to correct than those identified during early design phases. Whether the multiplier is 10x or 100x depends on context, but the direction is consistent: late discovery amplifies cost and schedule exposure.

System-level validation as risk compression

Reframing system-level validation as a schedule-risk compression mechanism changes how engineering organizations deploy it. Risk compression means reducing the variance between projected and actual ramp performance before high-volume commitments are made. It means narrowing the gap between modeled yield and early ramp yield while architectural flexibility still exists.

Consider a ten-million-unit program targeting 97% yield but only achieving 94% during early ramp. A 3% delta produces 300,000 additional defective units. At a $500 bill-of-materials cost, that equates to $150 million in direct exposure: before accounting for logistics, containment actions, rework, warranty impact, and brand degradation.

When system-level validation is embedded earlier in the development cycle, integration uncertainty is resolved before tooling freeze and capacity allocation. Manufacturing sensitivity becomes an architectural input, not a downstream constraint. Validation shifts from reactive confirmation to proactive risk reduction.

Governance implications for senior managers

For senior engineering and manufacturing managers, the implication is structural. System-level validation must be positioned upstream of design freeze, not solely before ramp. In practice, this requires:

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• Upstream integration: Embedding manufacturing engineering into early architecture discussions.
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• Quantified sensitivity: Requiring quantified yield sensitivity data before design freeze.
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• Strategic alignment: Aligning validation milestones with major financial commitments.
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• Holistic ownership: Elevating system-level risk ownership to program leadership rather than distributing it across siloed subsystem teams.
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Organizations that treat system-level validation as a downstream quality function implicitly accept schedule volatility as a cost of doing business. Organizations that embed it as a bridge between design architecture and manufacturing execution create structural advantage. They stabilize flagship launch timelines, reduce ramp inefficiency, and preserve optionality when trade-offs are still affordable.

Ayokunle Oni is a system engineering program manager at Apple, where he helps coordinate the iPhone hardware design and engineering process across cross-functional teams. He specializes in system integration and validation and has led complex engineering programs from concept through production, working closely with global manufacturing and vendor partners.

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The post How system-level validation compresses schedule risk in device design appeared first on EDN.

Built with low-distortion ferrite material, TDK’s MAF0603GWY series of filters attenuates noise on audio lines in the 5-GHz band. The filters fit in a compact 0.6×0.3×0.3-mm package for use in small consumer devices like smartphones and wearables with Bluetooth and Wi-Fi audio lines.

Electromagnetic noise radiated from audio lines in electronic devices can interfere with the internal antenna and reduce receiver sensitivity. While chip beads are commonly used to suppress noise, they can degrade sound quality.

TDK reports its newly developed ferrite material minimally affects audio-line characteristics while reducing distortion. The filters provide high attenuation at 5 GHz (impedance up to 3220 Ω) to suppress noise. They also limit attenuation of audio signals with lower resistance than conventional products, enabling a wide dynamic range.

Mass production of the MAF0603GWY series is set to begin in April 2026.

TDK

The post Tiny filters curb 5-GHz audio-line noise appeared first on EDN.

Four 100-V GaN power-stage ICs from EPC are optimized for motor drives in humanoid robots, drones, and battery-powered platforms. The EPC23108, EPC23109, EPC23110, and EPC23111 integrate a gate driver, high- and low-side eGaN FETs, and level-shifting circuitry in a half-bridge configuration. They support operation up to 100 V with load currents of 35 A (EPC23108, EPC23109) and 20 A (EPC23110, EPC23111).

The control interface includes an active-low fast-shutdown and standby input with a 65-kΩ pull-up. It meets industrial logic standards, letting designers connect directly to standard controllers. This simplifies designs and ensures consistent operation across platforms. Safety is enhanced through deterministic shutdown. 

The series supports continuous 100% duty-cycle operation, enabling full-torque and uninterrupted conduction in motion control, robotics, and precision regulation systems. The EPC23109 and EPC23111 offer a single-pin PWM input with enable logic and fixed dead time, simplifying multi-axis designs. The EPC23108 and EPC23110 feature dual PWM inputs for adaptive dead-time modulation.

Engineering samples are available for qualified designs. The EPC23108, EPC23109, EPC23110, and EPC23111 can be ordered through EPC’s distributor partners.

Efficient Power Conversion 

The post GaN ICs drive robotics and motion control appeared first on EDN.

We once looked at how conducted emissions testing could be affected by the negative input impedance of a switch-mode power supply. Please see: “Conducted Emissions testing.”

Digital data signals that a client’s electric power company was putting on the power lines were being amplified by the negative input impedance of the power supply being tested, which made it look like the power supply itself was generating conducted emissions, which, in fact, it was not.

I have since been asked by someone, “How can a negative impedance result in amplification?” The sketch below will illustrate how that can come about.

Figure 1 Negative resistance amplification.

Let our “impedance” in question be a resistance. In our sketch, voltages E2 and E4 are derived by voltage dividers from identical “Esig” sources for which standard voltage division equations apply. What is NOT standard here is that we are going to set R4 to negative numerical values.

My SPICE simulator will not let me assign a negative number to any resistance value (I think of that as picky, picky, picky!), but given that as the case, the voltage divider equations can be set up in GWBASIC. Line 150 of that code is where that happens.

With R1 and R3 arbitrarily set to 1K each and held there, we vary R2 and R4 together as shown to look at the effects on outputs E2 and E4, where we find the following.

E2 is always a lesser voltage than Esig. E2 varies versus the choices of value of R2, but it is always smaller than Esig.

On the other hand, E4 is always a greater voltage than Esig. E4 varies versus the negative value of R4, but it is always larger than Esig.

This effect on E4 is the amplification effect referred to in the earlier essay.

John Dunn is an electronics consultant and a graduate of The Polytechnic Institute of Brooklyn (BSEE) and of New York University (MSEE).

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The post Negative resistance amplification appeared first on EDN.

Motor control integrated circuits (ICs) and motor drives are essential elements for implementing smart manufacturing within the framework of Industry 4.0. A common requirement in modern industrial applications is high-efficiency motor solutions. About 50% of global energy consumption is due to electric motors, and therefore, even a moderate improvement in efficiency can provide meaningful economic benefits, helping reduce the carbon footprint.

International efficiency standards for industrial motors, such as IE3 (Premium) and IE4 (Super Premium), have been introduced to reduce energy use. As of July 2023, European regulations mandate that three-phase induction motors between 75 kW and 200 kW adhere to the IE4 efficiency standard.

In addition to being more efficient, modern industrial motor solutions must be smart and connected. “Smart devices” are equipped with sophisticated capabilities. They can identify irregularities such as excessive heat or voltage surges and respond automatically. The introduction of AI technologies, such as machine learning, brings this function to the next level, allowing predictive maintenance and reducing factory downtime.

Connection is another key requirement for motor solutions deployed in the Industry 4.0 sector. This feature allows the devices to exchange data in real time, supporting predictive maintenance, energy efficiency improvements, and remote control. Using the industrial internet of things, electric motors can send operational data to cloud systems. This helps reduce downtime and allows for continuous improvement of production processes. Moreover, technicians can access performance data remotely, decreasing the need for on-site inspections and allowing faster troubleshooting.

Motor driver architecture

Motor driver electronics is the power interface between digital control systems and electromechanical loads. This architecture is based on three components: control logic, gate drivers, and power stages.

Control logic typically resides within microcontrollers (MCUs), digital-signal processors, or dedicated motor control ICs, which are engineered to perform real-time control loops. Subsequently, gate drivers transform these logic-level signals into switching commands, which are then employed to regulate power transistors, encompassing MOSFETs and IGBTs. The power stage, frequently implemented via inverter or H-bridge configurations, supplies the desired current to the motor windings.

Furthermore, in Industry 4.0 contexts, motor drivers incorporate supplementary functionalities, encompassing fault monitoring, thermal sensing, communication interfaces, and energy management capabilities. Motor driver ICs also feature integrated protective measures, such as overcurrent, overvoltage, and thermal shutdown mechanisms. These protections improve system reliability and simplify the design process.

Microchip Technology Inc. recently introduced a lineup of 12 600-V gate drivers. These high-voltage drivers are designed to deliver output currents between 600 mA and 4.5 A. They are also available in a range of configurations, including half-bridge, three-phase driver, and high-side/low-side options.

These gate drivers facilitate rapid switching, thereby promoting efficient performance, and are particularly appropriate for industrial motor control applications. In addition, the logic inputs are compatible with standard TTL and CMOS levels, extending down to 3.3 V, which streamlines integration with conventional MCUs. The safe operation of the output power MOSFETs is ensured by Schmitt triggers on the inputs and an internal deadtime preset.

The MCP8062136, for instance, is a three-phase half-bridge with three high-side drivers operating in bootstrap operation up to 600 V and can provide a 200-mA source and 350-mA sink output current. The gate drivers also include several protection features, including shoot-through protection logic, undervoltage lockout for V_CC, and overcurrent protection.

To drive motor-controlled industrial applications such as sensorless three-phase fans and pumps up to 40 W, Melexis has introduced the MLX81339 motor control IC. The device is also suitable for driving brushless DC (BLDC) and bipolar stepper motor control for accurate positioning in applications such as automated valves, flaps, and small robotic motors.

The MLX81339 supports several types of communication interfaces with a host MCU, including the legacy PWM/FG, as well as the I²C, UART, and SPI interfaces. The motor control IC offers several protection and diagnostics features, including undervoltage, overvoltage, overcurrent, and overtemperature detection and protection, and integrates a programmable flash memory that can be used for application customization and IC configuration.

Connectivity in smart motor control

In Industry 4.0 applications, motor drivers often adopt communication protocols, such as EtherCAT, Profinet, and Ethernet/IP, to exchange real-time data with other drives, sensors, or systems supervising the industrial network. Typical data that can be exchanged includes torque, speed, temperature, and vibration. When processed at the edge or remotely on the cloud, this data allows predictive-maintenance models to provide valuable insights into motor operation, helping to detect potential faults before they occur.

Drive units mounted directly on motors or industrial machines are becoming very common. These devices, which include embedded controllers and communication interfaces, reduce the wiring complexity and allow machines to be reconfigured quickly for different production requirements.

For example, the RA8T2 MCU from Renesas Electronics Corp. is optimized for industrial motor control. Based on a 1-GHz Arm Cortex-M85 processor (with an optional 250-MHz Arm Cortex-M33 processor available in the dual-core version), the RA8T2 is designed for industrial motor control applications that require real-time performance and a high-speed communication interface.

These devices (Figure 2) integrate a 14-channel PWM timer for motor control, different types of memories (including a low-latency and high-speed TCM memory), and analog functions in a single chip. They also provide a dual-channel Gigabit Ethernet MAC with DMA and an optional EtherCAT slave controller that supports synchronous networks in industrial fields.

Wide-bandgap semiconductors

Wide-bandgap materials, such as silicon carbide (SiC) and gallium nitride (GaN), provide higher breakdown voltages, faster switching speeds, and lower on-resistance per unit area than silicon IGBTs and MOSFETs. From a designer’s perspective, this means that lower switching losses, improved thermal management, and higher operating frequencies can be achieved. These characteristics also lead to higher efficiency across the load range and a reduced footprint due to a reduced size of the passive components.

SiC is usually preferred in high-voltage and high-current applications above 600 V, such as high-power industrial drives and inverters. GaN, meanwhile, operates well in the 100- to 650-V range, with switching frequencies up to about 1 MHz. It is well-suited for mid-power motor drives in appliances, HVAC, pumps, small robots, and light industrial equipment.

Through a partnership, Qorvo Inc. and Cambridge GaN Devices (CGD) have developed the 400-W PAC5556AEVK2 and the 800-W PAC5556AEVK3 evaluation kits, suitable for developing motor control solutions in applications such as industrial fans, pumps, compressors, and white goods. The kits combine Qorvo’s PAC5556A mixed-signal system-on-chip with CGD’s ICeGaN HEMTs. The PAC5556A is a programmable 32-bit MCU that integrates a 600-V DC/DC buck controller and 600-V gate drivers.

The PAC5556AEVK2 evaluation kit features CGD’s 240-mΩ ICeGaN power devices, achieving up to 400-W peak performance without requiring a heat sink. The PAC5556AEVK3 integrates CGD’s 55-mΩ ICeGaN switches and provides a peak output power of 800 W, requiring minimal airflow cooling. The usage of GaN transistors improves the overall efficiency due to reduced power loss, reduces heat dissipation, and allows for smaller and more reliable motor control solutions.

Efficient Power Conversion (EPC), a company focused on e-mode GaN solutions, introduced the EPC91202 evaluation board for motor drive applications. It integrates a three-phase BLDC motor drive inverter built on the EPC2361 100-V eGaN FET and can provide an output current up to 70 A peak (50 A_RMS), with a switching frequency up to 150 kHz.

The EPC91202 is designed to handle sensorless and encoder-based motor control, boasting a low-voltage change rate, specifically a dV/dt rate of under 10 V/ns. This low voltage change rate reduces electromagnetic interference and acoustic noise. This board is well-suited for developing motor drive applications in various sectors. These include industrial automation, e-mobility, robotics, drones, and battery-powered devices.

AI and ML integration

Integrating AI/ML in motor control systems offers a valuable solution to investigate the behavior of motors during normal operation, helping to prevent anomalies or possible faults in advance. An example of a hardware and software integrated solution is the STSPIN32G4-ACT reference design and the FP-IND-MCAI1 STM32Cube function pack from STMicroelectronics.

The STSPIN32G4 is an advanced system-in-package that combines an STM32G431 MCU (based on an Arm Cortex-M4 core with CORDIC mathematical accelerator) with a three-phase gate driver. This architecture is specifically designed for controlling BLDC/permanent-magnet synchronous motors and provides the computing power needed to handle field-oriented control (FOC) algorithms, as well as local data analysis tasks (edge AI).

The FP-IND-MCAI1 software provides an implementation example for condition monitoring and predictive maintenance. This package collects data from internal sensors (current and voltage) and from external sensors (vibration and temperature), using it to feed pre-trained ML models.

Using ST’s NanoEdge AI Studio tool, optimized libraries can be generated that run directly on the chip, enabling the drive to “learn” the motor’s normal behavior and detect anomalies (such as mechanical imbalances or bearing failures) in real time.

Software tools

Several vendors offer software toolchains that cover the full development workflow from motor parameter identification through algorithm configuration, real-time debugging, and production code generation.

Infineon Technologies AG recently expanded its ModusToolbox Motor Suite to include a hardware-abstracted motor control core library covering advanced algorithms such as FOC and trapezoidal control, multiple startup methods including rotor alignment and six-pulse injection for initial position detection, and SVPWM modulation schemes. The integrated graphical user interface (GUI) provides a configurator and testbench that auto-detects connected evaluation boards; a digital oscilloscope monitoring up to eight firmware variables simultaneously; a motor profiler for automated extraction of resistance, inductance, and inertia parameters; and a PID tuner for closed-loop optimization.

Power Integrations released its MotorXpert v3.0 last year, a suite developed for its BridgeSwitch motor driver ICs (Figure 3). It adds shuntless and sensorless FOC support, a two-phase modulation scheme that cuts inverter switching losses by 33% in high-temperature environments, and a five-fold improvement to its waveform visualization tool. The codebase is written in MISRA-C and is MCU-agnostic, covering applications from 30 W to 750 W.

Other development tools available from leading semiconductor manufacturers include ST’s STM32 Motor Control SDK (X-CUBE-MCSDK) and Texas Instruments Inc.’s MotorControl SDK.

The post Designer’s guide: Motor control and drivers appeared first on EDN.

Firmware over-the-air (FOTA) updates are essential for improving system quality, adding new features after initial release, fixing bugs and vulnerabilities, improving system performance, and reducing recall and service costs. As new features are added, the size and complexity of the firmware stored in flash memory typically increases, inevitably leading to increased FOTA completion times.

Most of this time is spent on erasing and reprogramming. Beyond optimizing the user experience through faster updates, the irreversible nature of these operations must also be considered.

Another important consideration is that FOTA operations should ideally be performed in a stable environment similar to flash programming in a production environment. However, field update environments are relatively harsh and unstable. To avoid lengthy, risky, or potentially critical FOTA operations, the time required should be minimized.

But field updates are also vulnerable to various security threats, so thorough preparation is essential. These threats can range from third-party attacks to arbitrary modifications attempted by the product owner. This article outlines key considerations for implementing FOTA.

FOTA basics

FOTA is a technology that remotely updates a device’s firmware via wireless networks such as Wi-Fi, 5G, LTE, or Bluetooth without a physical connection. The flash memory used in this process serves as a core hardware resource, either temporarily storing the update package or ultimately writing the new executable code.

Let’s first examine the classification of FOTA based on flash memory configuration. This classification is determined by whether the flash memory is located internally or externally.

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• Dual-bank architecture, internal NOR flash memory method
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The dual-bank flash memory space within the MCU is allocated as active and passive slots, respectively. Each partitioned slot provides a space for executing existing software while simultaneously downloading new updates. This configuration features simple hardware configuration, high security, and fast bank switching through address remapping. However, it requires twice the flash memory density compared to the software size, resulting in increased hardware costs.

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• External NOR flash memory method
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This method uses external NOR flash memory connected to the application processor (AP)/microcontroller (MCU) via the QSPI (Quad SPI) or OSPI (Octal SPI) interface. Its large flash memory density makes it ideal for large-scale software updates. The update file or binary image is stored in flash memory and then copied to the internal flash memory. This method overcomes internal memory limitations and facilitates the storage of multiple versions of backup binary images, including emergency recovery binary images.

Let’s look at the classification of FOTA based on its implementation mechanism. These mechanisms can be used independently or combined and reconfigured.

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• A/B update (seamless update)
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The active slot (bank) where the current software/firmware is running and the passive slot (bank) for update downloads are physically separated, and software is installed or disabled across the two banks. This physical separation ensures that even if power is cut or a malfunction occurs during an update, the bank where the current software is running is preserved, preventing bricking.

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• Execute-in-place (XIP) and concurrency
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FOTA relies entirely on external NOR flash memory, meaning that code is read directly from external NOR flash memory. This technique involves executing code in one flash memory area while simultaneously downloading new updates to another area. However, the large capacity NOR flash memory used for FOTA is logically configured as a single bank, even when using multi-chip packaging technology. Therefore, the use of XIP for FOTA is limited.

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• Delta update
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This update only receives the changed differences or patches, rather than the entire software update or binary image. By reducing the amount of data transmitted, it reduces the time required for FOTA and saves on flash memory writes (program/erase cycles). Currently, optimized compression algorithm solutions are being employed to enable delta updates even on MCUs with low hardware specifications.

Reliability and security enhancements

FOTA design goes beyond simply writing data. It focuses on maximizing uptime (zero downtime) by leveraging safety, efficiency, and continuity, and securely controlling flash memory within a Trusted Execution Environment (TEE).

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• Integrity verification
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To ensure that data written to flash memory has not been corrupted or altered, the digital signature of the downloaded data is verified using a hardware security module (HSM) or TrustZone. After writing to flash memory, a checksum or CRC check is performed on the entire area to check defects in the flash memory.

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• Rollback
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If a boot failure occurs with a new update or software, the system must have the ability to immediately revert to the previous version.

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• Flash memory life management (wear leveling)
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Maximize the hardware lifespan of flash memory by preventing flash writes from being concentrated on specific areas of flash memory.

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• Secure boot integration
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Root of Trust (RoT) verifies that the software written to flash memory is signed by a trusted manufacturer.

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• Secure storage
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In addition to securing communication between the host and flash memory, flash memory must provide secure storage. The latest secure flash memory features a built-in HSM, enabling real-time encryption and decryption without performance degradation and providing secure storage capabilities.

NOR in FOTA architecture

Among the explanations mentioned above, the FOTA architecture utilizing external NOR flash memory is a strategy that overcomes the physical limitations of embedded memory and maximizes system flexibility. As of 2026, the role of external NOR flash memory is becoming increasingly important due to the increasing size of firmware and strengthened security requirements.

FOTA utilizing external NOR flash memory offers overwhelming advantages over embedded methods in terms of safety, density, and flexibility, and is becoming the standard for industrial devices requiring high reliability and smart devices using large-capacity firmware. We will delve into the five key advantages of FOTA using external NOR flash memory.

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1. Scalability and cost efficiency
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• Large image accommodation: Firmware containing the latest operating systems (RTOS, Embedded Linux), graphics libraries, and AI models often exceed tens of MBs in size. Adding relatively inexpensive external NOR flash memory is more advantageous for reducing overall bill of materials (BOM) costs than increasing the internal flash capacity of expensive MCUs.
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• Multi-image storage: Simultaneously storing multiple versions of firmware backups and user data images dramatically increases memory resource management flexibility.
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1. Provides a stable backup and rollback environment
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• Fail-safe mechanism: Even if a power failure or communication error occurs during an update, the existing executable code in the internal flash remains intact. The replacement process only begins after the new image has been fully downloaded and verified to prevent bricking.
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• Factory recovery: Factory recovery firmware can be stored in external memory. If a critical bug is discovered in a new version, it can be immediately restored to a stable previous version or factory settings from external memory without a server connection.
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1. Minimized downtime
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• Non-intrusive background downloads: The internal flash memory focuses on running the current application, while the external flash memory receives data in the background via an independent bus. This facilitates zero-downtime implementation, ensuring device service is not interrupted even while receiving update packets.
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• Bus separation: Using separate interfaces such as QSPI and OSPI prevents bus conflicts between internal memory access (command fetch) and external memory access (update write), minimizing system performance degradation.
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1. Extended flash life and maintainability
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• Internal flash memory protection: Flash memory has a limited number of write/erase cycles (P/E cycles). During development with frequent updates or when frequent firmware changes are required, a significant portion of write operations are handled by external memory, protecting the life of the MCU’s internal flash, which cannot be replaced.
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• Modular capacity expansion: Even if firmware capacity increases due to added functionality in the product lineup, the burden of hardware redesign is reduced because only the external flash memory can be replaced with a larger capacity without replacing the MCU.
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1. Security and data isolation
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• Physical isolation: The executable code (internal) and the update standby image (external) can be physically separated and managed.
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• Security update patch: By storing the firmware in an encrypted state in external memory and decrypting it only at boot time and uploading it to internal memory or RAM, an additional layer of defense against firmware theft attacks can be added.
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FOTA implementation

The success of a FOTA solution hinges on the ability to provide secure and seamless updates. The implementation of the above architecture will be key to achieving this.

The automotive industry is already responding to the changes that make FOTA essential. As the transition to software-defined vehicles (SDVs) becomes more concrete, demand for software updates is skyrocketing. This is because it enables flexible changes or additions to vehicle functions even after mass production, enabling rapid response to errors and defects and continuous delivery of new services to customers.

As the frequency of software updates increases, their importance is also increasing. United Nations Economic Commission for Europe (UNECE) WP.29 enacted R156 in June 2020, which now covers not only passenger cars, commercial vehicles, and trailers with towing devices, but also agricultural machinery equipped with software update capabilities.

UNECE WP.29 R155 and R156 define the requirements OEMs must meet in the areas of cybersecurity and software updates. UNECE regulations R155 and R156 introduce framework conditions for cybersecurity and software update capabilities for all vehicles. They also require automakers to establish certified Cyber Security Management Systems (CSMS) and Software Update Management Systems (SUMS).

R155 requires the establishment of a cybersecurity risk identification and response system, consideration of security throughout the entire vehicle lifecycle, documentation and maintenance of a CSMS based on ISO/SAE 21434, and submission of documentation and evidence during the Vehicle Type Approval (VTA) audit.

R156 addresses the security assurance of OTA or wired updates, change impact analysis and verification systems, update history management, and auditability. It’s based on the ISO 24089 standard for software updates.

The introduction of FOTA is no longer an option. It’s essential for improving system quality, adding new features, fixing vulnerabilities, enhancing system performance, and reducing recall costs.

We have examined the important considerations before adopting these new solutions. In addition to providing safe and fast update methods for improved user experience, we have also briefly discussed the security regulations that must be considered.

Scott Heo is lead principal engineer at Infineon Technologies.

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The post Memory solutions for firmware OTA updates appeared first on EDN.

At Arduino, our mission has always been clear: make complex technology accessible to everyone. But accessibility also means reaching people, inspiring them, and helping them understand what’s possible.

That’s why we’re especially proud to share that our “From Blink to Think” campaign for the launch of the Arduino® UNO Q board has been recognized by Unione Industriali Torino with the Mattia Serafini Award in the Best Digital Strategy category. 

The award was created by the Unione Industriali Torino to honor the memory of Mattia Serafini, a valuable member of their communication department and celebrates the most effective digital communication campaigns created by companies in 2025, across categories such as brand, sustainability, and product launches. Our campaign was selected as the top product launch in the small and medium enterprise category, among 29 finalists, highlighting not only creativity but also impact and clarity of message.

Communicating complexity, simply

Launching UNO Q was a unique challenge. It represented a new step forward for Arduino: a board designed to enable more advanced applications, bridging the gap between the Linux and the microcontroller worlds. But how do you communicate that evolution without losing what makes Arduino… Arduino? “From Blink to Think” was our answer. We started from the most iconic first step in a developer’s journey — blinking an LED — and showed how far users can go from there, following an exciting path to innovation that Arduino has enabled for two generations of developers, from a few lines of code to machines that act as fast as they can think.

Because ultimately, technology adoption starts with understanding. And understanding starts with clear, effective communication. As our Marketing Director Stefano Implicito said during his acceptance speech, “Today, we are living in a unique moment — a kind of renaissance of electronics — where AI, which many people still identify as a simple chat producing answers, is now moving into the physical world. We are entering the era of physical AI, and the real challenge now is to give people the tools to create tangible AI applications themselves. We can’t keep technology confined to a small group of engineers working in isolation, building black boxes that few can truly understand; it has to be something accessible, transparent, and within everyone’s reach.”

What matters most: what you build next

Awards are meaningful, especially when they recognize the work of an entire team and the value of clear communication in a complex technological landscape. But what we’re most proud of isn’t the campaign itself, but what it started. Since the launch of UNO Q, we’ve seen a growing number of projects, ideas, and experiments coming to life, powered by this new platform. That’s the real measure of success: not just telling a story, but enabling thousands of new ones.

The post The Arduino Marketing Team receives Best Digital Strategy award for “From Blink to Think” appeared first on Arduino Blog.

While hundreds of Arduino Days celebrations took place simultaneously in over 100 countries worldwide, on March 28th Vietnam stood out by hosting synchronized events in four major cities – Hanoi, Ho Chi Minh City, Da Nang, and Can Tho – bringing more than 1,000 students together for a day of hands-on technology learning. Activities included an international watch party, project showcases, workshops, talk shows, and a highlight Mini Hackathon where student teams were challenged to build functional health monitoring devices capable of measuring heart rate and SpO2 levels.

The event was organized by FPT Polytechnic in collaboration with Arduino and Qualcomm Technologies, Inc., demonstrating – in the words of Julián Caro Linares, Arduino Senior Engineer for Qualcomm Europe – the university’s “experience in training young people who can create impactful innovations and contribute to economic growth.” This event showed not just the energy and passion from the students from various cities and backgrounds on using technology to solve real world problems, but also how today the barriers to entry for AI at a device level are significantly lower. Participants showed how using Arduino solutions and the new Arduino® UNO Q board can truly democratize physical AI.

From knowing to doing

The theme for this year’s Arduino Days – “Writing the next chapter of AI together!” – reflects a moment when everyone is called to play an active role in defining a new era of innovation, shifting from theoretical knowledge into direct engagement with global technology standards. Everyone is the keyword here. Dr. Vu Chi Thanh, Principal of FPT Polytechnic, commented, “We do not want access to technology to be concentrated in just one place. By organizing the event simultaneously in four cities, students from different regions can connect directly with the global ecosystem and experience a real technology environment, rather than just hearing about it.”

Guneet Bedi, Senior Director of Sales at Qualcomm Technologies, emphasized the significance of Vietnam’s participation in the global Arduino community. “We are entering the AI era, and we need to train students – the future generations – not just how to use AI in everyday life, but how to stop being afraid of this technology,” he said. “Currently, there are millions of people developing on the Arduino platform, creating the world’s largest open-source community, and Vietnam has an incredibly active community that we are eager to support.”

The Mini Hackathon exemplified the event’s hands-on philosophy. Teams – including local students in fields such as automation, electrical engineering, information technology, as well as middle school and high school students interested in STEM – worked under tight time constraints to complete health-tracking devices. The challenge demanded not only technical knowledge in electronics and programming but also teamwork, troubleshooting skills, and product-oriented thinking. One student reflected on the experience: “When our product was reviewed by experts from Arduino and Qualcomm Technologies, we could clearly see the gap between an academic model and a product that could actually be deployed in real life. It is a pressure, but also a strong motivation.”

For Hoang Hung Hai, Product Marketing Staff Manager for Qualcomm Vietnam who helped bring to life the Hanoi event, this hands-on approach represents the future of technology education. “We want students to access Qualcomm and Arduino technologies while they are still in school, and then turn that knowledge into practical exercises, projects, and eventually larger-scale products in the future,” he said.

The strong message behind the success

The entire event embodied a powerful message: AI isn’t something to fear but something to master. As Bedi told students, “You need to learn not only how to use AI, but also how to build and customize it to solve real-world problems. Start now. Do not let yourselves fall behind in the AI revolution.”

At Arduino, we are certain you have the curious mindset and proactive attitude to shift from “using” AI to “making” AI, adding value with every project, prototype, or full-fledged product you create. Our mission is to provide you with access to the technologies you need, and to help you bridge any gaps on your way. The success of the event held by FPT Polytechnic during Arduino Days 2026 is a demonstration of how technology education can be both locally accessible and globally connected, how regional educational institutions can create synergies with the global technology ecosystem, and how each one of us is already part of something bigger.

Qualcomm branded products are products of Qualcomm Technologies, Inc. and/or its subsidiaries. Arduino is a trademark or registered trademark of Arduino S.r.l.

The post Arduino Days 2026 empowers students across Vietnam through hands-on technology experiences appeared first on Arduino Blog.

As explained in the E series Wikipedia page: “The E series is a system of preferred numbers (also called preferred values) derived for use in electronic components. It consists of the E3, E6, E12, E24, E48, E96, and E192 series, where the number after the ‘E’ designates the quantity of logarithmic value ‘steps’ per decade. Although it is theoretically possible to produce components of any value, in practice, the need for inventory simplification has led the industry to settle on the E series for  resistors, capacitors, inductors, and zener diodes.”

Wow the engineering world with your unique design: Design Ideas Submission Guide

It’s convenient at times to have a desktop calculator that accepts a computed value x and returns the standard, commercially available value closest to it for a specified E series. Here, “closest” means that candidate value for which the absolute value of the computed error (candidate/x – 1) is the smallest.

The following GitHub link:

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• https://github.com/Christopherrpaul/E-series-Calculator
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hosts the files needed to create the desktop icon, which calls the application, both of which are shown in Figure 1. It also contains a README file, which details how to install the files on a Windows PC, and a User Manual.

Figure 1 The desktop icon that calls the application, which is also shown. The E3 series has been selected, and a computed value of 56 has been entered. The closest E3 series value of 47 is apparent, along with the calculated error of the selected candidate.

Selecting a different series will automatically calculate and present the nearest value and its error for that series. Pressing the key in the Enter Value box will clear the entry so that a new one can be checked. The Enter Value numeric sequence may be followed by an exponent (e6, E-2, etc.). A single alpha character (for instance, M, k, n, or others) also may be appended. Neither is necessary, but the format of the Nearest E value will always follow that of the Enter value.

Although not needed often, this is convenient to have around with the touch of a Desktop icon. Move it elsewhere if the Desktop is not your preferred location.

Christopher Paul has worked in various engineering positions in the communications industry for over 40 years.

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I’ve always been interested in sensors and their related electronics. These devices are the interface between the real, physical world and the telemechanical systems that make use of their outputs. It’s also fascinating how many basic sensor approaches have been devised and enhanced for basic parameters such as temperature, pressure, distance, light intensity, and more.

Now we are entering a new phase where advances in materials—especially metamaterials, often aided by lasers—are creating breakthrough in sensors that could not be envisioned or implemented just a few years ago.

In short, a metamaterial is an engineered, 2D structure composed of subwavelength-scale elements that precisely control electromagnetic waves, such as light or microwaves, at an interface. The metasurface is an ultra-thin resonant element with special physical properties.

It’s typically composed of sub-wavelength structures (meta-elements) arranged in a 2D plane, enabling control over the propagation and scattering of electromagnetic waves at sub-wavelength scale by adjusting the phase, amplitude, or polarization of the incident waves

A good example of such an innovation is seen in the thermally based photon-detector project at Duke University, where researchers have demonstrated the fastest pyroelectric photodetector to date. It works by absorbing heat generated by incoming light and can capture light from wavelengths across the electromagnetic spectrum. The ultrathin device requires no external power, operates at room temperature, and can be readily integrated into on-chip applications.

Conventional semiconductor photodetectors work by initiating electron flow when struck by visible light. In contrast, the pyroelectric detector approach (also called a thermal detector) generates electric signals when it’s heated up after absorbing light.

Pyroelectric detectors have been in use for decades due to their wideband characteristic, unlike semiconductor sensors that tend to be narrowband devices (which is not necessarily a bad thing, of course). However, these pyroelectric devices are not as responsive as solid-state devices, since they are relatively bulky and have larger thermal mass.

Although using a thermal scheme is normally slow compared to using photons to stimulate electrical current, it does not have to be that way. In the Duke approach, the metasurface-enabled pyroelectric photodetectors are fabricated by layering a well-established nanogap cavity metasurface structure on top of a pyroelectric thin film (Figure 1).

Figure 1 Schematic representation of metasurface-enabled photodetectors illustrating key dimensions (a) with SEM image of the metasurface absorber (b). The red area represents the metasurface array. Finite element simulations of a single plasmonic nanostructure showing a cross-section of the pyroelectric layer 30 ps after resonant excitation of the metasurface (c).

The metallic metasurface consists of an array of nanoscale silver square prisms (90 nm × 90 nm × 35 nm) separated from a gold film by a thin (10 nm) dielectric layer of Al₂O₃ (aluminum oxide or alumina).

When light strikes the surface of a nanocube, it excites the silver’s electrons, trapping the light’s energy through a phenomenon known as plasmonics (the interaction between electromagnetic radiation such as light and conduction electrons at metallic-dielectric interfaces), but only at a specific frequency controlled by the nanocubes’ sizes and spacings.

In the latest iteration, the light-absorbing metasurface is circular rather than rectangular to maximize its exposure while minimizing the distance the signal must travel. This phenomenon is so efficient at trapping light and absorbing its energy that it only requires an extremely thin layer of pyroelectric material beneath it to create an electric signal.

Measuring the performance is another challenge. So, they devised an innovative arrangement with two distributed-feedback lasers that “brightened” when their frequencies became close to the same as the device’s operating speed.

The nearly perfect, spectrally selective absorption of the metasurface, which initiates the photodetector response, is shown by white light reflectivity spectra (Figure 2).

Figure 2 White light reflectance spectrum of a detector is shown with a 1.3 × 10⁻³ mm² active area of 40 μm diameter (a). Photocurrent responsivity spectra of the detector shown in (a) measured upon pulsed 100 nW light excitation as compared to that of a detector in which a gold film rather than a metasurface layer acts as an absorber (b). Photocurrent measured for the device presented in a) and b) upon pulsed 783 nm excitation at the indicated power with the beam size maintained to consistently have a diameter 5 μm smaller than that of the device (c).

The gold mirror alone efficiently reflects near-infrared light, while the metasurface exhibits a relative decrease (>95%) in reflectivity centered at 790 nm. The resonance wavelength is determined by the size of the Ag nanostructures and the thickness of the Al₂O₃ dielectric layer, as it allows the possibility of photodetectors that are spectrally selective across the visible and infrared portions of the spectrum.

The team found that their new thermal photodetector operates at record-breaking 3-dB bandwidth of 2.8 GHz, which corresponds to a rise time of just 125 picoseconds. Also important, these ultrafast speeds were achieved while maintaining competitive responsivities and noise equivalent power (NEP) as low as 96 pW/√Hz.

This is just one of the many innovative applications in the RF and optical worlds which leverage metamaterials and metasurfaces. Among many other uses, these materials enable new ways to manage and channel electromagnetic energy at these wavelengths, often to create sensors of extraordinary accuracy and precision.

The full details of this work by the Duke University team are in their paper “Metasurface-Enhanced Thermal Photodetector Operating at Gigahertz Frequencies” published in Advanced Functional Materials. While that posted paper is behind a paywall, the Duke team has thoughtfully posted an open-source version at their departmental website here.

Have you seen or used any sensors based on metamaterials or metasurfaces? What sensing challenges would you tackle if you had the needed meta resources?

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Motion is invisible until something makes it measurable. That is where inertial measurement units (IMUs) step in—the silent sensors that give machines their hidden sense of balance, orientation, and trajectory. From smartphones that know when you have rotated the screen, to drones that hold steady against the wind, IMUs translate raw acceleration and angular velocity into actionable awareness.

In this installment of Fun with Fundamentals, we will peel back the layers of these compact marvels, showing how they evolved from bulky gyroscopes into today’s precision-packed silicon companions.

The silent navigators: IMUs

An IMU is a compact, high-precision device that captures how an object moves and orients itself in space. Whether steering rockets into orbit, stabilizing drones overhead, or enabling smartphones to guide us through crowded streets, IMUs are the unseen systems that make modern navigation possible.

At the heart of an IMU are sensors that detect linear acceleration with accelerometers and rotational velocity with gyroscopes. Many designs also incorporate a magnetometer to provide heading information. A typical configuration combines a 3-axis accelerometer and a 3-axis gyroscope, forming a 6-axis IMU. When a 3-axis magnetometer is added, the system becomes a 9-axis IMU. Together, these sensors deliver measurements of specific force, angular rate, and surrounding magnetic fields—producing a complete dataset for motion and orientation tracking.

The accelerometers, gyroscopes, and—when included—magnetometers inside an IMU are collectively referred to as inertial sensors. These components form the foundation of inertial navigation, working together to capture motion and orientation data without relying on external signals. By fusing their outputs, engineers can derive precise information about how a device moves through space, even in environments where GPS or other external references are unavailable.

So, accelerometers measure linear acceleration, capturing how quickly an object speeds up or slows down. Gyroscopes sense angular velocity, revealing the rate and direction of rotation. Magnetometers, when included, detect magnetic fields and provide heading information relative to Earth’s magnetic north.

It’s worth noting that engineers still deploy both 6-axis and 9-axis IMUs, depending on the demands of the application. A 6-axis unit, built from accelerometers and gyroscopes, is often sufficient for tasks like stabilizing drones, balancing robots, or monitoring automotive motion, where relative movement and rotation are the primary concerns.

In contrast, a 9-axis IMU adds a magnetometer, giving it the ability to resolve absolute heading. This makes it the preferred choice in smartphones, wearables, and advanced navigation systems, where orientation relative to Earth’s magnetic field is critical. In practice, the simpler 6-axis design remains a cost-effective workhorse, while the 9-axis variant dominates in consumer electronics and navigation-heavy applications.

Figure 1 A vintage mechanical inertial navigation system (INS) component achieves autonomous navigation by integrating an inertial measurement unit with a computational unit. Source: Author’s archives

Simply put, a typical IMU places one accelerometer and one gyroscope along each of the three principal axes, ensuring motion and rotation are captured in all directions. In some designs, a magnetometer is also added per axis to provide heading information, but this is not always the case—many IMUs operate effectively without it.

Beyond these core sensors, certain IMUs incorporate auxiliary elements such as temperature monitors, since accelerometers and gyroscopes are prone to thermal fluctuations that can compromise accuracy. By recording temperature data, the system compensates for thermal drift, stabilizing sensor outputs and improving overall reliability.

Evolution and types of IMUs

From the gimbaled IMUs of the aerospace pioneers to today’s miniaturized MEMS-based devices, IMUs have undergone a remarkable transformation. Early gimbaled systems relied on mechanically stabilized platforms, bulky yet precise, before giving way to strapdown IMUs that fixed sensors directly to the vehicle body, reducing size and complexity.

With the rise of microelectromechanical systems (MEMS), silicon MEMS IMUs became the standard for consumer electronics, robotics, and drones, prized for their low cost, compact size, and efficiency. For tactical and industrial applications, Quartz MEMS IMUs emerged, offering greater stability and resilience under temperature and vibration compared to silicon designs.

At the high-end, ring laser gyroscope (RLG) IMUs and fiber-optic gyroscope (FOG) IMUs represent the pinnacle of precision, both exploiting the Sagnac Effect to measure rotation. RLGs use laser beams circulating in a closed cavity, while FOGs rely on long coils of optical fiber—an approach that reduces maintenance needs and improves durability while delivering comparable accuracy.

Today, engineers select from this spectrum—silicon MEMS for affordability and portability, quartz MEMS for tactical reliability, and RLG/FOG systems for uncompromising accuracy—depending on mission requirements.

Figure 2 The Motus ultra‑high‑accuracy MEMS IMU enables precision in autonomous system applications. Source: Advanced Navigation

As a side note, it’s worth mentioning that while IMUs deliver raw measurements of acceleration and angular velocity, an attitude and heading reference system (AHRS) builds on this foundation by applying sensor fusion algorithms to provide stabilized orientation outputs: pitch, roll, yaw, and heading. In practice, AHRS units are IMUs with embedded processing, making them more directly usable in aircraft, marine, and robotic platforms where orientation data is required in real time.

Advanced IMU categories

Beyond the broad spectrum of MEMS and optical gyroscope technologies, IMUs can also be classified by their functional purpose. A north-seeking IMU is designed to determine true north without relying on external references such as the global navigation satellite system (GNSS) or magnetic compasses.

By exploiting the Earth’s rotation and combining precise gyroscope measurements, these systems achieve sub-degree heading accuracy, making them invaluable in marine navigation, underground operations, and defense applications where absolute orientation is critical.

In contrast, a navigation IMU focuses on tracking motion and orientation over time. It provides raw acceleration and angular velocity data that, when processed within an inertial navigation system (INS), yields position, velocity, and displacement. Navigation IMUs are widely deployed in aerospace, robotics, and consumer electronics, where continuous motion tracking and drift management are more important than absolute north-finding.

Together, these advanced categories highlight how IMUs are not only differentiated by sensor technology—silicon MEMS, quartz MEMS, RLG, or FOG—but also by the specific role they play in navigation systems, from heading determination to full trajectory tracking.

Practical pointers for engineering minds

IMUs are no longer the nightmares they once seemed. Thanks to today’s accessible sensor modules, open-source libraries, and low-cost development boards, even a novice maker can experiment with inertial measurement units without needing aerospace-grade expertise. What was once the domain of defense labs and high-end avionics has now become approachable for hobbyists, students, and engineers alike, making hand-on exploration of motion sensing and navigation both practical and affordable.

First off, note that modern inertial modules often advertise “IMU, AHRS, and INS options” because the same hardware platform can deliver different levels of functionality depending on firmware and processing. At the most basic level, the unit acts as an IMU, outputting raw accelerometer and gyroscope data. With onboard sensor-fusion algorithms, it becomes an AHRS, providing stabilized orientation in pitch, roll, yaw, and heading.

When paired with a computational unit and often GNSS input, the same device scales up to a full INS, achieving autonomous navigation with position, velocity, and orientation. This tiered approach lets engineers choose the level of integration that matches their application, from hobbyist UAVs to aerospace systems.

Modern IMUs give engineers and makers practical choices across performance levels. High-end devices like Analog Devices’ ADIS16575/ADIS16576/ADIS16577 deliver factory calibration, low bias drift, and digital outputs for precision robotics, autonomous systems, and aerospace projects.

At the same time, compact modules such as Murata’s SCH16T-K01 integrate gyro and accelerometer sensing for embedded applications, wearables, and IoT nodes. Together, these platforms show how inertial technology now scales from aerospace-grade accuracy down to plug-and-play modules, offering practical options for projects at every level.

Figure 3 The SCH16T‑K01 module combines a high‑performance 3‑axis angular rate sensor and 3‑axis accelerometer, delivering precise motion tracking for embedded, wearable, and IoT applications. Source: Murata

Besides, makers and hobbyists do not need to wrestle with bare chips anymore—prewired IMU breakout boards are widely available and come with headers and libraries, making motion sensing experiments plug-and-play. For newer designs, boards built around ST’s LSM6DSO/LSM6DSOX deliver reliable performance in a maker-friendly format, ensuring parts that are safe for ongoing projects.

Figure 4 Today’s prewired cards like the LSM6DSOX module—and other readily available IMU boards—let makers explore motion sensing with ease and enable reliable integration into advanced embedded projects. Source: Author

IMUs in practice and everyday life

Well, we are not balanced yet, but we have touched some fundamental and practical points in a rather random way. Still, the journey through IMUs shows how these sensors are not just abstract components for engineers; they are part of our everyday lives. From the stabilizing gimbals that keep cameras steady, to the motion tracking inside wearables, gaming controllers, and even automotive systems, IMUs quietly enable the seamless experiences we take for granted.

Figure 5 Today’s IMUs act as the unseen hand across entertainment, healthcare, and navigation—guiding cameras, gimbals, ships, trains, satellites, and aerospace systems, while also enabling makers to explore motion sensing with ease and integrate it reliably into advanced projects. Source: Author

The call now is to explore further—experiment with modules, build small projects, and see firsthand how this complex yet easy topic can transform ideas into motion-aware innovations.

T. K. Hareendran is a self-taught electronics enthusiast with a strong passion for innovative circuit design and hands-on technology. He develops both experimental and practical electronic projects, documenting and sharing his work to support fellow tinkerers and learners. Beyond the workbench, he dedicates time to technical writing and hardware evaluations to contribute meaningfully to the maker community.

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Clem Mayer over at element14 Presents got his hands on a big old LED matrix display and when he turned it on, it worked perfectly. It even displayed the last programmed message, like an inadvertent time capsule. But upon opening up the enclosure, Mayer found danger and some strange control quirks. So, he used an Arduino UNO R4 WiFi to rebuild the LED sign, making it both safe and usable.

The danger lurking inside was thanks to a brick-style AC-to-DC adapter. That wouldn’t be a problem on its own, but the AC input wires were soldered directly to the adapter’s pins. That’s a big no-no, because a loose wire could contact the enclosure and send deadly voltage through it for anyone to touch.

Mayer’s first task was to replace that with a simple and correctly wired external power supply that outputs a safe 5V DC. That was easy and wasn’t particularly interesting, but it was absolutely crucial for peace of mind.

The second task was programming new messages. Mayer thought he’d be able to send data to the display’s controller via serial, but wasn’t able to get that working. Attempts to communicate didn’t result in a response from the display.

However, the display did come with a PS/2 keyboard and some intriguing instructions. It turns out that the display’s controller accepts input directly from the PS/2 keyboard, which is quite unusual. But it gave Clem an access path: he used an UNO R4 WiFi board with a PS/2 library to emulate keyboard input. As long as it “types” slowly, the Arduino can program the display with any arbitrary message.

And because it has Wi-Fi capability, Clem can make the Arduino work via his network. It would, for example, be possible to have the Arduino check the weather each morning and then program the display with a weather description.

The post An Arduino gives this quirky old LED sign a new life as a smart display appeared first on Arduino Blog.

A granular synthesizer — or more appropriately, a granular audio processor — is a device that chops audio samples into small “grains” that are just a few milliseconds long. It then manipulates them and rearranges them, before outputting the result. The auditory effect is interesting and appealing to experimental artists, but even low-end granular synthesizers are pricey. So, Sid Rockett used an Arduino Nano R4 to build his own open-source granular synthesizer called Arena Digitalis.

Granular synthesizers are expensive because they have to store audio samples, which takes memory, and then manipulate them in real-time, which requires processing power. Luckily, the Arduino Nano R4’s Renesas RA4M1 microcontroller has generous memory (32kB of RAM) and processing power (48MHz clock speed) at a low price. It also has analog input pins and a digital-to-analog converter (DAC).

Aside from the Nano R4, the only components required to build an Arena Digitalis are some audio jacks, potentiometers, buttons, LEDs, capacitors, and resistors. 

Those components provide input and output connections, plus the user interface. Musicians can adjust grain size and tweak tone, mix, and speed — or simply press the “random” button to make interesting sounds without any fuss. 

Because Arena Digitalis doesn’t generate audio on its own, the sound will depend entirely on the input. That can be anything from a CD to a synthesizer to an electric instrument. But no matter what you use for input, the glitching effect will add a layer of texture that you really can’t achieve in any other way and this is the most affordable way to get it.

The post Glitchy goodness from an open-source granular synthesizer appeared first on Arduino Blog.

Editor’s note: This is a multi-part series on how to design a digital-controlled PFC: 

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• How to design a digital-controlled PFC, Part 1
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• How to design a digital-controlled PFC, Part 2
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• How to design a digital-controlled PFC, Part 3
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Total harmonic distortion (THD) and power factor are two major criteria used to evaluate power factor correction (PFC) performance. Meeting strict THD and power factor requirements is always a challenge for PFC designs. In this third installment of the series, I will introduce a set of digital methods to reduce THD and improve the power factor.

THD definition

THD is the total harmonic distortion present in a signal, defined as the ratio of the root-mean-square (RMS) amplitude of the total higher harmonic frequencies to the RMS amplitude of the fundamental frequency. Equation 1 expresses THD:

where Vn is the RMS value of the nth harmonic, and V1 is the RMS value of the fundamental component.

THD requirements have become stricter, especially in server applications, but meeting low THD requirements is more difficult than ever. The following methods can help reduce THD.

Make sure that the sensed signals are clean

To reduce THD, the first thing is to make sure that all of the sensed signals are clean. Because the sensed AC input voltage modulates the current reference, any spikes on the sensed AC signal will cause current reference distortion and affect THD. 

One common practice is to put a decoupling capacitor close to the analog-to-digital converter (ADC) pin of the controller and set the resistor-capacitor filter cutoff frequency about 10 times higher than the frequency you are interested in. If the sensed AC voltage is still noisy, you can use a software phase-locked loop (SPLL) [1] to generate an internal sine-wave signal in phase with the AC voltage, and then use that generated sine-wave signal to modulate the current reference. Since the SPLL-generated sine wave is clean, even if there is some noise on the sensed AC voltage, the current loop reference will still be clean.

For VOUT sensing, you can use a digital infinite impulse response filter, as shown in Equation 2, to process the sensed VOUT to further reduce noise; because the PFC voltage loop is slow, the extra delay caused by this digital filter is acceptable.

where k<1.

Oversampling

The PFC inductor current has switching ripples. The current-sensing circuit may not provide sufficient attenuation to this current ripple. If you sample this signal only once in each switching period, there is no perfect, fixed location where the signal represents the average current all of the time. To get a more accurate feedback signal, consider using an oversampling mechanism.

Figure 1 shows an example that evenly samples the current feedback signal eight times in every switching cycle, averages the results, and sends them to the control loop. This oversampling effectively averages the current ripple out such that the measured current signal gets closer to the average current value. Also, the controller becomes less sensitive to noise.

Figure 1 Oversampling eight times in every switching cycle to average the current ripple out in order to allow the measured current signal to get closer to the average current value. (Source: Texas Instruments)

Reduce the current spikes at AC zero crossing

Current spikes at AC zero crossing are an inherent issue for totem-pole bridgeless PFC. These spikes can be so big that it becomes impossible to pass THD specifications. Reference [2] analyzes the root cause of these spikes and provides a PWM soft-start algorithm to effectively reduce them, as shown in Figure 2.

Figure 2 PWM soft start after AC zero crossing to prevent current spikes common to totem-pole brideless PFCs.(Source: Texas Instruments)

In this algorithm, when VAC changes from a negative to a positive cycle after AC zero crossing, boost switch Q2 turns on first with a very small pulse width, then gradually increases to the duty cycle (D) generated by the control loop. A soft start on Q2 gradually discharges the switch-node drain-to-source voltage (VDS) to zero. Once Q2 soft start is complete, synchronous transistor Q1 starts to turn on. It begins with a tiny pulse width and gradually increases until the pulse width reaches 1–D. When Q2 soft start is complete and Q1 soft start begins, the low-frequency switch Q4 turns on.

The transition from the AC positive cycle to the negative cycle is similar. Turning off all of the switches at the end of each half AC cycle leaves a small dead zone at AC zero crossing. Figure 3 shows the test result.

Figure 3 Current waveforms without and with a PWM soft start: the traditional control method (a); PWM soft start (b). (Source: Texas Instruments)

Reduce voltage-loop effects

The PFC output voltage has double-line frequency ripples. Although the voltage loop compensator can reduce these ripples, it cannot totally remove them; there are still some ripples coupled to the current reference that then affect THD.

One way to reduce the effect of these ripples is to add a digital notch (band-stop) filter between the VOUT sensed signal and the voltage loop. This notch filter can effectively attenuate the double-line frequency ripple while still passing all other frequency signals, including the sudden VOUT change caused by the transient load. The load transient response will not be affected.

Another approach is to use VOUT at the AC zero-crossing value, or VOUT_ZC(t), as a voltage feedback signal; see Figure 4. Since VOUT_ZC(t) equals the average value of VOUT, and since it is a “constant” in steady state, using it as feedback signal can eliminate the double-line frequency ripple.

Figure 4 VOUT at the AC zero-crossing instant, using this method can eliminate the double-line frequency ripple. (Source: Texas Instruments)

To handle the load transient, use the voltage loop control law shown in Figure 5.

Figure 5 Using VOUT_ZC(t) as a feedback signal in the steady state. (Source: Texas Instruments)

If the instantaneous error is small, use the value at the AC zero-crossing instance, which is VOUT_ZC, and a small Kp, Ki for the voltage loop compensator Gv. When a load transient occurs, causing an instantaneous VOUT error greater than the threshold, use the instantaneous VOUT value and a large Kp, Ki for Gv to rapidly bring VOUT back to its nominal value.

Duty-ratio feedforward control

As the name suggests, duty-ratio feedforward control precalculates a duty ratio, then adds this duty ratio to the feedback controller. For a boost topology operating in continuous conduction mode, Equation 3 gives the duty ratio feedforward (dFF) as:

Figure 6 depicts the resulting control scheme. After using Equation 3 to calculate dFF, add dFF to the traditional average current-mode control output (dI). Then use the final duty ratio (d) to generate a PWM waveform to control PFC.

Figure 6 Average current-mode control with dFF. (Source: Texas Instruments)

Since dFF generates the majority of the duty cycle, the control loop only adjusts the calculated duty slightly. This technique can help improve THD for applications with a limited controller loop bandwidth.

Harmonic injection

In cases where a specific order of harmonics is too high, and the methods I’ve described still cannot meet the THD specification, a harmonic injection method [3] may resolve the problem. The basic idea of this method is to generate a sinusoidal signal with the same order of the harmonic that you want to compensate, and inject this signal into the PFC current control loop to compensate for that harmonic.

There are two ways to generate a sinusoidal signal. The first method is to use an SPLL to track the AC voltage and then generate the corresponding high-order harmonics. The second method is to generate a sine-wave table and then read the table element at a different speed to obtain different orders of sine waves [3]. Figure 7 shows a test result on a PFC that initially has high third- and fifth-order harmonics.

Figure 7 Harmonic injection to reduce third- and fifth-order harmonics. (Source: Texas Instruments)

Power factor definition

The power factor is the ratio of real power in watts to apparent power, which is the product of the RMS current and RMS voltage in volt amperes, as shown in Equation 4:

Ideally, the power factor should be 1; the load will then appear as a resistor to the AC source. In the real world, however, electrical loads not only cause distortions in AC current waveforms but also make the AC current either lead or lag with respect to the AC voltage, resulting in a poor power factor. For this reason, Equation 5 calculates the power factor by multiplying the distortion power factor by the displacement power factor:

where φ is the phase angle between the current and voltage, and THD is the total harmonic distortion of the current.

Equation 5 also shows that to improve the power factor, the first thing to do is to reduce THD. However, low THD does not necessarily mean that the power factor is high. If the PFC AC input current and AC input voltage are not in phase, even if the current is a perfect sine wave (low THD), φ will result in a power factor less than 1.

The phase difference between the input current and input voltage is mainly caused by the electromagnetic interference (EMI) filter used in the PFC. Figure 8 shows a typical PFC circuit diagram that consists of three major parts: an EMI filter, a diode bridge rectifier, and a boost converter.

Figure 8 Circuit diagram of a typical PFC comprising an EMI filter, a diode bridge rectifier, and a boost converter. (Source: Texas Instruments)

In Figure 8, C1, C2, C3 and C4 are EMI X-capacitors. Simplifying Figure 8 results in Figure 9, where C is now a combination of C1, C2, C3, and C4.

Figure 9 Simplified EMI filter combining the capacitances shown in Figure 8. (Source: Texas Instruments)

The X-capacitor causes the AC input current to lead the AC voltage, as shown in Figure 10. The PFC inductor current is , the input voltage is , and the X-capacitor reactive current is . The total PFC input current is , which is also the current from where the power factor is measured. Although the PFC current control loop forces to follow , the reactive current of leads by 90 degrees, which causes to lead . The result is a poor power factor.

This effect is amplified at a light load and high line, as takes more weight in the total current. As a result, it is difficult for the power factor to meet a rigorous specification.

Figure 10 X-capacitor causes the AC current to lead the AC voltage. (Source: Texas Instruments)

Fortunately, with a digital controller, you can resolve this problem with one of the following methods.

Delay the current reference

Since makes the total current lead the input voltage, you can force to lag  by some degree, as shown in Figure 11. The total current will then be in phase with the input voltage, improving the power factor.

Figure 11 Forcing to lag . (Source: Texas Instruments)

Since the current loop forces the inductor current to follow its reference, to let lag , the current reference needs to lag . To delay the current reference, a circulate buffer stores the measurement V_AC results. Then, instead of using the newest input voltage V_AC data, use previously stored V_AC data to calculate the current reference for the present moment. The current reference will lag ; the current loop will then make  lag . This can compensate the leading X-capacitor  and improve the power factor.

The delay period needs dynamic adjustment based on the input voltage and output load. The lower the input voltage and the heavier the load, the shorter the delay needed. Otherwise will be over delayed, making the power factor worse than if there were no delay at all. To resolve this problem, use a look-up table to precisely and dynamically adjust the delay time based on the operating condition.

Subtract from the current reference

Since a poor power factor is caused mainly by the EMI X-capacitor , if you calculate  for a given X-capacitor value and input voltage and then subtract  from the total ideal input current to form a new current reference for the PFC current loop, you will get a better total input current that is in phase with the input voltage and can achieve a good power factor.

To explain in more detail, for a PFC with a unity power factor of 1, is in phase with . Equation 6 expresses the input voltage:

where VAC is the AC input peak value, and f is the AC frequency. The ideal input current then needs to be totally in phase with the input voltage, expressed by Equation 7:

where IAC is the input current peak value.

Equation 8 expresses the capacitor current:

Equation 9 comes from Figure 9:

Combining Equation 7, Equation 8, and Equation 9 results in Equation 10:

If you use Equation 10 as the current reference for the PFC current loop, you can fully compensate the EMI X-capacitor , achieving a unity power factor. In Figure 12, the blue curve is the waveform of the preferred input current, i_AC(t), which is in phase with . The green curve is the capacitor current, i_C(t), which leads  by 90 degrees. The red curve is i_AC(t) ‒ i_C(t). In theory, if the PFC current loop uses this red curve as its reference, you can fully compensate the EMI X-capacitor  and increase the power factor.

Figure 12 New current reference. (Source: Texas Instruments)

Equation 10 requires a cosine waveform cos (2πƒt). To get this cosine waveform, use an SPLL to generate an internal sine wave synchronized with the input voltage. For microcontrollers that cannot perform trigonometric calculations, reference [4] describes another way to calculate iC(t).

Reduce THD and improve PF

If you need to reduce THD and improve the power factor, choose one or a combination of the methods discussed here. In the next installment of this series, I will talk about how to improve efficiency, limit re-rush current, implement e-metering, and reduce PFC bulk cap with a baby boost converter.

Related Content

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• How to design a digital-controlled PFC, Part 1
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• How to design a digital-controlled PFC, Part 2
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• Power Tips #116: How to reduce THD of a PFC
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• Power Tips #124: How to improve the power factor of a PFC
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References

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1. Bhardwaj, Manish. “Software Phase Locked Loop Design Using C2000 Microcontrollers for Single Phase Grid Connected Inverter.” Texas Instruments application report, literature No. SPRABT3A, July 2017.
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2. Sun, Bosheng. “How to Reduce Current Spikes at AC Zero Crossing for Totem-Pole PFC.” Texas Instruments Analog Design Journal article, literature No. SLYT650, 4Q 2015.
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3. Sun, Bosheng. “A Harmonic Injection Method to Reduce Harmonics and THD for PFC.” Power Electronics News, Nov. 20, 2023.
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4. Sun, Bosheng. “Increase power factor by digitally compensating for PFC EMI-capacitor reactive current.” Texas Instruments Analog Design Journal article, literature No. SLYT673, 2Q 2016.
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The post How to design a digital-controlled PFC, Part 3 appeared first on EDN.

Differential oscilloscope probes are indispensable tools for engineers who need to measure signals accurately in complex environments. Whether you are troubleshooting everyday low-voltage circuits or tackling the challenges of high-voltage power electronics, the right probe ensures safety, precision, and reliable data capture. Yet, with so many options available—each designed for specific ranges and applications—understanding how to select and use differential probes effectively can make the difference between clear insights and misleading results.

This article explores the essentials of differential probes, highlighting their role in both common and high-voltage measurements, and offering practical guidance for engineers who want to master their use.

Understanding differential probes

At their core, differential probes are designed to measure the voltage difference between two points that are not referenced to ground. Unlike single-ended probes, which assume one side of the signal is tied to earth ground, differential probes float with the circuit under test, making them ideal for analyzing signals in isolated systems, switching power supplies, motor drives, and other environments where ground-referenced measurements can be misleading—or even unsafe.

By rejecting common-mode noise and providing accurate readings across a wide voltage range, differential probes give engineers the confidence to capture clean waveforms in both everyday low-voltage circuits and demanding high-voltage applications.

The poor man’s alternative: A-B math mode

Some engineers turn to the oscilloscope’s A–B math mode as a low-cost substitute for a true differential probe. By connecting two standard single-ended probes to separate channels and subtracting one from the other, the scope can display the voltage difference between two points. While this trick works for basic low-voltage measurements, it suffers from a critical drawback: poor common-mode rejection ratio (CMRR).

Furthermore, this method creates a dangerous grounding hazard; because standard probes remain tied to the scope’s Earth-grounded chassis, attempting this on floating high-voltage circuits can cause a catastrophic short circuit that a true, isolated differential probe would easily prevent.

Dedicated differential probes are carefully designed with matched inputs, shielding, and circuitry that reject common-mode noise and interference. In contrast, the A–B math method relies on two independent channels that rarely match perfectly in gain, phase, or frequency response.

As a result, common-mode signals leak into the measurement, producing distorted or noisy waveforms. This makes A–B math unsuitable for precision work and unsafe for high-voltage applications, where accurate rejection of common-mode voltage is essential (while floating-input oscilloscopes are an effective alternative, we will not be covering them in this post).

Figure 1 The A–B math mode on an oscilloscope uses two channels to approximate a differential measurement. Source: Author

Isolation transformers: A stopgap, not a solution

One of the most dangerous pitfalls in high-voltage oscilloscope measurements is the ground clip trap. Even if the circuit is floated, the probe’s ground clip remains internally tied to earth ground. Accidentally clipping to a high-voltage node can instantly short the circuit, destroy equipment, and pose a severe shock hazard.

A common workaround is to power the device under test (DUT) through an isolation transformer, breaking the direct connection to earth ground. This allows probes to be connected more flexibly and can make certain measurements possible when a proper probe is unavailable.

Floating a circuit also introduces new risks: exposed nodes may sit at dangerous potentials relative to ground, and the oscilloscope itself can be compromised if isolation fails. For these reasons, the 1:1 isolation transformer approach should be regarded only as a stopgap “poor man’s” option. When working with high-voltage systems, the safe and reliable solution is always a properly rated probe designed for the task.

Figure 2 A 1:1 isolation transformer lets probes connect without a ground reference, but the ground clip stays internally tied to earth and poses risk. Source: Author

It’s worth noting is that isolating the DUT—rather than the oscilloscope—is a standard power electronics practice that significantly assists a differential probe by floating the entire circuit’s reference. This setup effectively eliminates ground loops that otherwise inject EMI into your measurements via the probe’s cable shielding.

More importantly, it reduces common-mode stress on the probe’s internal amplifiers; since the DUT is no longer hard-tied to Earth ground, the probe does not have to fight a massive voltage potential relative to the scope’s chassis. This results in a much cleaner signal with higher fidelity, particularly when probing high-side MOSFETs or bridge rectifiers where the reference point is constantly swinging.

The right take: Differential scope probes

So, differential probes are specialized tools for measuring the voltage difference between two points in a circuit. They feature two inputs that can be connected anywhere without requiring a ground reference. An internal differential amplifier produces an output voltage proportional to the difference between the chosen points, typically scaled by a user-defined attenuation factor.

Figure 3 An active differential probe extends the measurement capabilities of a standard oscilloscope. Source: Pico Technology

Recall that a major advantage of differential probes is their ability to reject common-mode signals—voltages present simultaneously at both inputs. This makes them highly effective for capturing low-level signals in noisy environments. They can also be used for single-ended measurements by grounding one of the leads.

As an aside, it’s worth mentioning that a differential probe is not the same as a differential preamplifier like the Tektronix ADA400A. Probes are designed for general oscilloscope measurements across a wide bandwidth, while preamplifiers are specialized for ultra-low-level, low-frequency signals. ADA400A, for example, offers selectable gain and filtering, making it ideal for micro-volt level work in noisy environments.

Although ADA400A is still supported and available through some distributors, it’s considered more of a legacy accessory than a mainstream option. In practice, that means it remains useful for precision applications but is not promoted for new designs the way modern differential probes are. In short, use a probe for broad, everyday measurements, and reach for a preamp when chasing precision at the very bottom of the signal scale.

Getting back on track, high-voltage differential probes are among the most widely used types in modern test and measurement setups. And, galvanically isolated HV differential probes go further by providing complete electrical separation between the high-voltage circuit under test and the oscilloscope, protecting both the operator and sensitive equipment.

This isolation—often implemented through optical coupling techniques—prevents ground loops, reduces noise interference, and ensures accurate measurements even in environments with large voltage swings. Their combination of safety, fidelity, and versatility makes them indispensable tools in high-voltage and high-power applications.

As a summary (kept simple for clarity), all differential probes rely on active circuitry, since measuring the voltage difference between two points requires rejecting common-mode signals. Everyday differential active probes are used for precision work in high-speed digital and low-level analog circuits.

For power electronics, high-voltage differential active probes are the standard, enabling safe measurement of floating signals and large common-mode voltages. And when maximum safety and fidelity are needed, galvanically isolated differential probes—often using optical isolation—provide complete separation between the circuit under test and the oscilloscope, preventing ground loops and protecting both operator and equipment.

Practical session: Use cases and key specifications

This session is on the practical side, focusing on when differential probes are actually needed and the key specifications that matter most when choosing one.

Needless to say, differential probes are required whenever signals are not referenced to ground or involve large common-mode voltages. A classic case is measuring the gate-to-source voltage on a high-side MOSFET in a switching converter. Because the source terminal is floating and rides on the switching node, a standard single-ended probe tied to ground would be unsafe and misleading.

In this situation, a high-voltage differential active probe captures the true waveform safely, and if voltages or noise are extreme, an optically isolated probe adds full separation between circuit and oscilloscope for maximum protection and accuracy.

Figure 4 A practical application example using a differential probe to capture floating gate-to-source voltage signals in a power electronics circuit. Source: Author

Below are the key specifications engineers should keep in mind:

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• Common mode rejection ratio (CMRR): Measures how well the probe ignores “noise” or voltages that appear equally on both leads. Note that CMRR is frequency-dependent and typically drops as the signal frequency increases. A higher CMRR ensures cleaner measurements in high-interference environments.
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• Voltage rating: Defined by both differential voltage (between leads) and common-mode voltage (leads to ground), often categorized by CAT safety ratings such as CAT II and CAT III). These ratings ensure the probe can safely handle both the signal’s magnitude and any potential transients in your application.
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• Attenuation ratio: Most differential probes provide fixed or switchable ratios. This setting defines how much the input signal is scaled down before reaching the oscilloscope, balancing high-voltage safety with signal fidelity.
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• Bandwidth: Determines how faithfully fast signals are captured. Because square waves are composed of high-frequency harmonics, a probe’s bandwidth should ideally be 3 to 5 times higher than the signal’s fundamental frequency to avoid “rounding off” sharp transitions.
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• Input Impedance: High resistance minimizes DC loading on the circuit. However, be aware that effective impedance drops significantly at high frequencies due to the effects of internal capacitance.
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• Input capacitance: This is the primary factor that “slows down” fast transitions or causes circuit loading at high speeds. Lower capacitance is essential for maintaining signal integrity and preventing the probe from changing the behavior of the circuit under test.
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Clearing the mist on differential probes

As often, this post also leaves some mist but hopefully clears enough to reveal the essentials. Differential probes are not exotic extras—they are the right tool whenever signals float, swing at high voltages, or demand precision beyond what a single-ended probe can safely deliver.

From active types for clean digital and analog work, to high-voltage versions for power electronics, and galvanically isolated probes for maximum safety, the choice comes down to matching probe and specs to the measurement challenge. And those specs—CMRR, bandwidth, risetime, voltage rating, attenuation ratio, input impedance, capacitance—are not just numbers; they decide whether your waveform is faithfully captured or dangerously distorted.

So next time you reach for a probe, pause to check your choice and its specs—the right differential probe is not optional, it’s essential for accuracy, safety, and confidence in your measurements.

T. K. Hareendran is a self-taught electronics enthusiast with a strong passion for innovative circuit design and hands-on technology. He develops both experimental and practical electronic projects, documenting and sharing his work to support fellow tinkerers and learners. Beyond the workbench, he dedicates time to technical writing and hardware evaluations to contribute meaningfully to the maker community.

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The post Mastering differential probes: Fundamentals and advanced insights appeared first on EDN.

It may not support the latest-and-greatest cellular data tech. But in a pinch, it’ll cost-effectively still do the Internet-access trick.

In one of last month’s posts, covering cellular hotspots for maintaining broadband connectivity when premises power goes down, as well as when you’re on the road, I wrote:

Last January I’d purchased on sale from Amazon two NETGEAR LM1200 cellular broadband modems, one for teardown-to-come and the other for precisely the scenario—premises power-loss connectivity backup—that I experienced in mid-December. They aren’t as-is usable [unless you only need to have one wired-connected device online, that is], requiring tether to a router. But I have plenty of those in inventory. And had we stuck around the home more than one night I probably would have pressed the modem-plus-router combo into service, fueled by a portable power unit. But another limitation, bandwidth, was the same one that already soured me on the Surface Pro X’s integrated modem (along in the ones in my Intel-based Surface Pros, for that matter). The LM1200 “only” supports 4G LTE, which is likely why I bought them (on closeout, I suspect) for only $19.99 each a year-plus back, versus the original $49.99 MSRP.

Today, I’ll be actualizing my year-plus back teardown aspiration, as usual beginning with some outer box shots…as usual accompanied by a 0.75″ (19.1 mm) diameter U.S. penny for size comparison purposes:

Flip up the top flap:

and the first things you’ll see are our patient, underneath two slips of paper (also found here in PDF form, along with a fuller user manual). Below them:

are two cables, one for power and the other for data connectivity, along with a power adapter:

Last things first; the AC-to-DC adapter, with a USB-A output (with only notable sides shown):

and the two cables:

Now for our patient:

TS-9 connectors (plus other interesting things, such as the nano SIM slot) ‘round back, the same as with the high-end NETGEAR MR6110 cellular hotspot I showcased a month back:

and as before intended for tethering the cellular modem to an optional external antenna:

Onward:

Note the passive ventilation abundance underneath; a curious choice, given that heat rises, not sinks (and don’t get me started on the confusion inherent to the term “heatsink”), but better than nothing, I guess:

A closeup of the label reveals, among other things, the all-important FCC ID (PY320300503):

60 FCC certification record entry results. That’s a new record, at least for me!

Rubberized feet tend to hide (albeit not always, mind you) screw heads, providing pathways inside:

The typical presence pans out once again in this instance:

And we’re in. The top and bottom chassis pieces both detach:

leaving behind the PCB, along with chassis remnants around the periphery:

which also separate straightaway, this time with no additional screws to mess with:

Let’s start with the top of the PCB:

Dominating the landscape is a Quectel EC25-AF PCIe LTE Cat 4 module, rotated 180° in this photo so you can discern the topside printing right-side-up:

Below it are the four status LEDs whose illumination ends up shining out the holes at the top of the device. And above it are two Youth Electronics GS12401C LAN transformers, one each for the cellular modem’s LAN and WAN ports.

Next, those two long-and-skinny shiny metal pieces, one on each side of the PCB:

They’re, you’ve probably already guessed, the 4G cellular antennae.

Now for the other (bottom) side of the PCB:

Faraday Cages. Regular readers already know what comes next:

Nothing terribly exciting here, that is unless you’re an RF engineer:

How about the larger one?

Another 4R7 (4.7 microhenry) inductor. Plus, a Qualcomm Atheros QCA8334 four-port Gbit Ethernet switch IC, only two ports’ worth of resources which are presumably in use (for the aforementioned LAN and WAN backside ports). And scattered about the remainder of this PCB side’s real estate are clusters of test points, passives, discretes and other diminutive doodads.

And there we are! After this writeup is published and I answer any lingering reader questions, I’ll pop the Faraday Cage tops back on, reassemble the surrounding chassis and see if it still works. And speaking of questions, please do sound off with your thoughts in the comments!

—Brian Dipert is the associate editor, as well as a contributing editor, at EDN Magazine.

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The post Netgear’s LM1200: A 4G LTE modem, modestly funded appeared first on EDN.

If you spend enough time around casino games, you start to notice a pattern. The players who last the longest or at least feel the most in control are rarely the ones trying to track everything at once. They’re not juggling five ideas at the same time or building complicated systems around every spin. Most of the time, they’re doing something much simpler than that.

When Overthinking Breaks the Flow

It usually starts with good intentions. A player wants to be more structured, so they begin adding rules. Only play at certain times. Only stay in a game after a specific type of result. Adjust bets based on what just happened. On platforms like betway nigeria, where everything is built to move quickly from one round to the next, those extra layers tend to stand out even more once they begin to pile up. Individually, none of these ideas is unreasonable. But once they stack up, the session starts to feel different.

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Less like a smooth run, more like something you have to manage step by step. You pause more. You think more. You second-guess more. And in casino gaming, that shift matters. Because a lot of the experience depends on rhythm. You spin, you react, you move forward. Once that rhythm breaks, everything starts to feel heavier than it should.

Simple Play Keeps Decisions Clean

There’s something underrated about not having to think too much between rounds. Players who stick to simple approaches tend to move more naturally. They decide what they’re comfortable with before the session starts, then just follow it without constantly adjusting. It might be something as basic as fixed bet sizes or deciding in advance how long they’re going to stay in a game. Nothing complex, but it removes friction. You’re not recalculating after every outcome. You’re not trying to interpret patterns that may or may not mean anything. You’re just playing within a structure that’s already clear. And that clarity makes a difference over time.

More “Signals” Don’t Mean Better Decisions

A lot of complex strategies in casino gaming come from trying to read into every detail. Tracking streaks, watching sequences, trying to spot when something is “due.” It feels like more information should help, but in practice, it often just creates noise. One moment suggests staying in, another suggests leaving. Now you’re stuck in between, trying to decide which signal matters more. That hesitation builds quietly. When you strip it back, decisions become easier. Not because you know more, but because you’re not trying to process everything at once. You’ve already decided how you’re going to play, so you just follow it.

The Platform Itself Favors Simplicity

There’s also a technical side to this that people don’t always think about. Modern casino platforms are built for speed. You open a game, it loads quickly, and everything is designed to keep you moving without interruption. The spin button is immediate, the feedback is instant, and transitions between rounds are smooth. That kind of setup naturally fits simple behavior. When a player introduces too many steps between actions, it doesn’t really align with how the platform is built to work. You end up slowing yourself down inside an environment that’s designed to feel effortless. And that mismatch can make the whole experience feel off.

Easier to Stay Consistent

One of the biggest differences shows up in longer sessions. Complex systems are hard to maintain. Even if you start with a clear plan, it’s easy to drift away from it. You forget one rule, adjust another, react differently than you intended. Not in a big way, just small changes that add up. Simpler approaches are easier to stick with. There’s less to remember, less to interpret, and less to adjust on the fly. You’re more likely to stay consistent from start to finish. And in casino gaming, consistency often matters more than trying to be overly precise.

What Actually Holds Up Over Time

There’s always a temptation to make things more advanced. To feel like you’re adding control or improving your approach. But most of the time, the opposite is true. The players who keep things simple aren’t doing less. They’ve just removed what doesn’t really help. No extra layers, no unnecessary rules, nothing that slows them down or makes decisions harder than they need to be. And that’s usually what holds up. Not complexity. Just something clear enough to follow without getting in your own way.

Pick and place (PnP) machines are the linchpin on which modern electronics manufacturing rests. A PnP is a special kind of robot with a vacuum end effector designed to pick up SMD (surface-mount device) components and place them on a PCB for soldering. But for hobbyists, they’re usually overkill. So, John LeClair bridged the gap with these manual PnP vacuum tweezers.

This is just a PnP machine, but without all that fancy CNC robot stuff. With this, you’re the robot and you hold the “end effector.” You likely won’t have the precision or work ethic of a robot, but you’ll be able to place SMD components on your board without resorting to sticky, staticky, pinchy tweezers.

The end effector here is just a small Weller handheld tool with flat cup nozzle. All of the interesting stuff is related to controlling vacuum. An Arduino UNO Rev3 handles that by sending power to a 12V diaphragm air compressor pump working in reverse to pull vacuum. The Arduino controls it and a solenoid valve through MOSFETs. By modulating power to the pump MOSFET via PWM, the Arduino can control the pump’s speed. 

For ease of use, there are only four user controls. The first is a power switch to turn on the whole machine. The second is a potentiometer to set the pump speed. The third is a potentiometer to set the amount of time the pump stays on. The last is a footswitch to activate the pump.

When you’re ready to grab something, simply depress the footswitch and the pump will come on. Then use the tool to start picking up and placing your SMD components. 

The post Pick and place without the CNC appeared first on Arduino Blog.

We’ve been working on some updates to Arduino Cloud that honestly make the whole experience better. Dark theme? Finally. A way to undo deletes? Yes. And we completely rebuilt the Thing Page so you don’t have to jump between a million tabs anymore. Here’s what changed.

Dark theme is finally here

^{Arduino Cloud offers a dark theme across the entire platform}

Okay, this one’s been requested forever, and we finally did it. Arduino Cloud now has a proper dark theme across the entire platform – home, dashboard, Cloud Editor, Things, Devices, Triggers, everything.

We didn’t just flip some colors around and call it done. We actually went through and redesigned the visual experience to make sure it looks good and stays readable when you’re coding at 2 AM. The app defaults to light mode, but you have full control. You can sync it with your OS settings, or just toggle to dark mode whenever you want.

We’re also planning to add custom color themes for Pro and Education organizations down the road.

New sidebar with Trash

We redesigned the sidebar to make it cleaner and easier to use, but the real win here is the new Trash section. Now when you delete something, it’s not just gone into the void forever. You have the ability to restore a deleted operation.

^{You can now restore deleted dashboards, Things, triggers and sketches from your Trash}

Dashboards, Things, Triggers, Sketches – they can all be recovered now. We figured if we’re building tools this powerful, they should also be forgiving. You should be able to experiment without the risk of breaking something permanently.

The Thing Page: rebuilt from scratch

^{The Thing is now the central place to manage your device and Cloud variables}

This is the big one. A Thing should be the center of everything in Arduino Cloud. It’s the hub. Everything else connects to it. And we wanted the whole system to actually feel like that instead of like a bunch of features bolted together.

^{A more central and intuitive way to manage your Things}

So we rebuilt the whole Thing Page from the ground up. Our design team spent a lot of time trying to make sure you can find your stuff easily. We wanted the interface to support a navigation that feels natural, friction-less. And we wanted the powerful features to just make sense, without needing to read documentation.

Up until now, you had to go to different pages to associate a Device, open the Cloud Editor, or check Triggers. You’d end up with a bunch of tabs open, constantly jumping around. It was annoying, and you could lose your bearings.

Now everything’s in one place. You can associate Devices, open the Cloud Editor, set up Triggers, and manage everything connected to your Thing without leaving the page. No more tab chaos. No more “Wait, where was I?”

This isn’t just about adding a little convenience to your journey, but about putting Things where they should be – at the center of your IoT projects. Now the Arduino Cloud interface actually reflects that.

Try it out

Everything we just talked about is live in production right now, ready for you to test out! Here’s what we recommend trying first:

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• Log into app.arduino.cc (it’s free) 
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• Open a Thing Page. Notice how everything’s integrated right there?
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• Turn on the dark theme. See how it feels – your eyes might prefer it, especially during those long coding sessions.
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• Delete something, then restore it. Go ahead, try it. Head to Trash and bring it back.
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As always, we’re committed to continuously improving Arduino Cloud based on your actual, ever-evolving needs. These updates represent our vision for a more intuitive, forgiving, and powerful platform – but they are also the result of essential feedback and collaboration from the community. 

So, feel free to head to Arduino Forums to ask for support or let us know what you think about the new features. Let’s blaze a new path to innovation, together! 

Arduino is a trademark or registered trademark of Arduino S.r.l.

The post Here’s what’s new in Arduino® Cloud: a completely rebuilt Thing Page, dark theme and more! appeared first on Arduino Blog.

As a leading digital transformation and software engineering company, Arduino system integrator Softeq Development Corp. is a proven innovator in the industrial space – working with clients to deliver sophisticated, reliable solutions that leverage power and accessibility at the same time.

In a recent project, the company developed a cutting-edge controller for a client specializing in automation technology. The goal was to create a reliable system capable of transporting items along complex pathways using multiple conveyor belts and diverters. This required a centralized brain to manage the sequence and timing of all moving parts and sensors.

The challenge of complex transport and remote control

The client needed a solution that went beyond simple, straight-path conveyor control. As a first step, the system supports multiple conveyor belts operating in line with each other, establishing the foundation for future capabilities like managing transitions between belts and routing items to specific destinations.

The key technical challenge was twofold:

1. Centralized, reliable control: Developing a controller that could successfully manage the sequence of multiple conveyor belts, photo-eye, and contact sensors.

2. Wireless connectivity: For future, large-scale deployments, the client wanted to avoid running extensive control and sensor cables to every unit. The solution required robust, production-ready wireless control capabilities.

The Arduino advantage: off-the-shelf and industrial-grade

Softeq selected two key Arduino products to deliver the solution: Arduino® Opta WiFi and Arduino® MKR WiFi 1010. While the Opta WiFi served as the micro PLC (programmable logic controller) for the system, managing sensor inputs (origin, destination, door) and controlling the power output for the conveyor motor, the MKR WiFi 1010 provided wireless remote control and intelligent status updates, enabling the system to be managed without extensive hardwired cabling.

By utilizing these industrial-grade devices, the Softeq team was able to meet the demanding requirements for sensor inputs and motor control outputs. The choice simplified firmware programming and eliminated the need for costly, time-consuming custom hardware development. The resulting hardware controller box is a robust unit that integrates seamlessly with the conveyor system to ensure safe, intelligent, and efficient package handling. For instance, the system ensures the conveyor only runs when conditions are met and automatically returns packages if they linger too long at the destination or after a door cycle.

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“The decision to use Arduino was driven by the client’s need to wirelessly control conveyor belts in a large warehouse with multiple conveyor systems. They wanted to avoid running extensive control and sensor cabling to each conveyor. The solution required three sensors (Origin, Destination, and Door open/close) along with motor power control, making off-the-shelf Arduino devices a strong fit. This approach eliminated the need for custom hardware, saving both time and cost. With built-in Bluetooth and Wi-Fi support, and Opta handling sensor inputs and motor outputs, only minimal firmware was needed to manage sensor states and Bluetooth inputs from the MKR 1010 control box.” – Paul Fruia, Senior Advisor with Softeq Development Corp.

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A successful partnership for smart logistics

This smart conveyor belt is a prime example of the synergies between Softeq and Arduino in the industrial IoT space – following the previous successful collaboration for a non-invasive glucose monitoring prototype. Softeq’s client expressed strong satisfaction with the delivered controller box and is already preparing specifications for extending the solution to new applications.

Industrial innovation is no longer reserved for companies with massive R&D budgets: accessible and production-ready industrial hardware makes smart logistics and automation easier and more accessible for everyone.

The post The smart conveyor belt from Softeq uses Arduino for a robust wireless control solution appeared first on Arduino Blog.

We’re excited to announce Arduino App Lab 0.6, a release that makes managing your Arduino® UNO Q board easier, extends your creative toolkit, and brings AI capabilities right to your fingertips.

A new settings page for full board visibility

The standout feature in 0.6 is the new board settings page. Think of it as mission control for your UNO Q: everything you need to know about your board in one place. At a glance, you can see your firmware version, operating system details, and whether updates are available. 

^{New settings page gives you full visibility into your board}

You can also access your board’s serial identifiers, system specs, kernel information, and configuration options like external sensor support, keyboard language, and remote access.

No more hunting through menus or switching between tools. It’s the kind of feature that just makes sense once you start using it.

Retrain your Edge Impulse models with one click

New Bricks, new examples!

The 0.6 release brings fresh Bricks to your toolbox:

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• Sound Generator Brick: Create audio feedback, alarms, or musical elements with ease.
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• Telegram Bot Brick: Connect your projects to Telegram for notifications, remote control, and more.
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• Automatic Speech Recognition (Cloud) Brick: Build voice-controlled projects without the complexity of managing inference pipelines yourself.
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And here is something every beginner (and veteran) will appreciate: every Brick now includes a basic use example. 

For instance, here are a few more examples that show what is possible:

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• Telegram Bot: See how to wire up messaging and commands.
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• Music Composer: Turn your UNO Q into a musical instrument.
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• Cloud AI Assistant: Explore conversational AI integration.
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As a reminder, you can save a copy of any of these pre-built examples into your own apps in the Arduino App Lab, then run it quickly on your UNO Q. 

Try Arduino App Lab now

Arduino App Lab 0.6 is available now for UNO Q. Update through the app or download the latest version from arduino.cc/app-lab. The full changelog and technical documentation are available in our release notes.

What will you build with 0.6? Share your projects with us on Arduino Project Hub or tag us on social media. We can’t wait to see what you create.

Get started in your edge AI development journey

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• Arduino App Lab latest documentation
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• UNO Q documentation
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• Find inspiration on Project Hub 
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• Download Arduino App Lab
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• Purchase UNO Q
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Arduino is a trademark or registered trademark of Arduino S.r.l.

The post Arduino® App Lab 0.6: more control, more Bricks, faster AI appeared first on Arduino Blog.

Diodes has added a 100-V MOSFET to its lineup of 40-V to 80-V devices, all in 8×8-mm gullwing-leaded packages for automotive systems. With a maximum on-resistance of 1.5 mΩ, the DMTH10H1M7SPGWQ is well suited for 48-V BLDC motor drives used in power steering and braking systems. Like other family members, it minimizes conduction losses, reducing heat generation and maximizing overall efficiency.

The MOSFET’s PowerDI8080-5 package occupies a footprint of just 64 mm², approximately 40% less than the legacy TO-263 (D2PAK). It also offers a slim off-board profile of 1.7 mm. Copper clip die bonding reduces thermal resistance to as low as 0.3°C/W, enabling drain currents as high as 847 A without risk of damage. The gull-wing lead configuration supports automated optical inspection and enhances temperature-cycling reliability.

AEC-Q101 qualified, the DMTH10H1M7SPGWQ is rated to +175°C for high-ambient-temperature operation. One-hundred-percent unclamped inductive switching (UIS) testing during production ensures reliable, robust end applications.

The DMTH10H1M7SPGWQ is priced at $1.71 each in quantities of 5000. Contact sales via the product page for availability and purchase details.

Diodes

The post MOSFET ensures automotive thermal reliability appeared first on EDN.

Infineon’s TDM24745T quad-phase power module with trans-inductor voltage regulator (TLVR) magnetics provides high current density for AI workloads. Integrating four power stages, proprietary magnetics, and decoupling capacitors in a compact 9×10×5-mm package, the module achieves 2 A/mm² and delivers up to 320 A peak.

The device optimizes transient response and supports the high-current core rails required by advanced GPU and AI processors in both lateral and vertical power delivery configurations. Powered by OptiMOS-6 MOSFETs, it offers enhanced efficiency and thermal performance in dense AI server designs. The TLVR architecture further improves transient performance while reducing required output capacitance by up to 50%.

The TDM24745T power module integrates with Infineon’s end-to-end AI server power delivery ecosystem. Availability was not disclosed at the time of this announcement. For more information about Infineon’s voltage regulation solutions for AI and data centers, click here.

Infineon Technologies 

The post TLVR power module supplies 320 A for AI processors appeared first on EDN.

Two TVS diode series from Littelfuse provide DO-160 Waveform 5A Level 5 lightning protection for avionics, military, and other mission-critical systems. The SM15KPA-HR/HRA and SM30KPA-HR/HRA offer peak pulse power ratings of 15 kW and 30 kW (10/1000 µs), respectively, protecting I/O lines, power buses, and sensitive electronics from lightning-induced transients and high-energy surges.

Both families offer fast response times—typically less than 1 ps from 0 V to V_BR minimum—30-kV ESD protection per IEC 61000-4-2 on data lines, and low incremental surge resistance. The devices remain stable across a junction temperature range of –55°C to +150°C. While all diodes undergo high-reliability 100% screening tests, the HR versions additionally pass MIL-STD-750 Group B tests for extra test rigor and extended reliability margins.

The TVS diodes come in compact SPD4-1 surface-mount packages compatible with automated assembly. These packages reduce weight and board space while eliminating the through-hole mounting typically required for high-energy TVS components.

The SM15KPA-HR, SM15KPA-HRA, SM30KPA-HR, and SM30KPA-HRA series are available in tape-and-reel format in quantities of 500. Samples can be requested through authorized Littelfuse distributors worldwide.

Littelfuse

The post Lightning-resistant TVS diodes safeguard avionics appeared first on EDN.

Why does one battery (or a few) in a multi-battery pack always seem to drain faster than others, and how does this outcome affect both its siblings and the system they jointly power? Read on.

A recent teardown noted a surprisingly (at least to me) common occurrence that I’ve repeatedly experienced: a tendency for an Amazon Echo smart speaker (or other similarly powered device, for that matter) to functionally fail due to the demise (specifically: droop or other DC output voltage compromise under high load, I’m assuming) of an easily replaceable AC power adapter:

I’ve had a few second-generation “Dot” devices’ external power supplies fail in the past; the end result is either a flat-out refusal to start at all or a perpetual repetition of partial boots followed by abrupt restarts. In those cases, the consistent “fix” was straightforward and non-wasteful. Since the AC/DC converter with USB-A output was distinct from the USB-A to microUSB cable that fed the device, I could just swap in a replacement for the former and be up and running again in no time. Every time I did this, by the way, I wondered how many Echo Dots prematurely ended up in the landfill due to typical-consumer ignorance of both the exhibited issue’s root cause and simple resolution solution.

An oldie-but-goodie

In this post, I’ll cover another situation that I come across a higher-than-expected percentage of the time, whenever a multi-battery-powered device goes down for the count. To begin, I’d like to introduce you to a long-time, frequent-use friend of mine, my BT-168 battery tester:

I was happily surprised, while researching the BT-168 online just now while writing, to come across a link to a colleague’s review and teardown of it from a few years back:

Within his writeup, T.K also briefly mentioned a digital display-based successor, the BT-168D, whose existence I wasn’t aware of until now but which is apparently less accurate than my “old school” original analog version due to a comparative applied-load deficit:

I have no idea how long I’ve owned it, or for that matter, how it originally came into my possession. That said, it’s still available for sale (variously company-name branded by multiple retail sources) at Amazon and other distribution intermediaries, as is the follow-on BT-168D.

What’s this got to do with “single-battery failures in multi-battery arrangements”? Well, whenever a two-AA-powered remote control, for example, or a three-AAA-based bathroom scale:

or an LED flashlight, or even (an extreme example) the six-AAA-each (!!!) LED illumination-augmented automatic salt and pepper grinders we recently received as a gift:

functionally fades, I never reflexively slot all the batteries in a charger for refresh or toss ‘em all in the trash (depending, duh, on whether they’re rechargeable). Instead, I sequentially stick each of them in the BT-168 and see what remaining-charge level each reads. Invariably, one is significantly more “dead” than the other(s), even if they were all brand-new when originally installed. Replacing only the drained one more cost-effectively (for non-rechargeables) gets the gear going again, not to mention a reduced landfill payload…until the next one inevitably fails.

Organization determines compromise-outcome specifics

Why, though, does this operating-life inconsistency occur at all? I’d long been aware that batteries’ initial from-factory charges, therefore measured voltages, were predominantly-to-completely a function of their inherent chemical processes. To wit, so-called “precharged” rechargeable batteries are fundamentally just a marketing-driven relabel of low self-discharge, therefore longer-than-otherwise shelf life, battery chemistries and internal architectures.

But I admittedly didn’t fully realize until researching this writeup just how inconsistent battery-to-battery internal resistance can be, even within a common chemistry-and-architecture combination, both manufacturing batch-to-batch and even within a given batch. To be clear, Ohm’s Law, which I learned way back in my first semester of electrical engineering at university, has long informed me of the effects of higher-than-normal resistance: greater “waste” heat output, reduced current output and lower voltage, especially under load. And I also had some inkling of the fact that for a given battery, resistance also evolves over time and use, typically increasing (unless, of course, the battery develops an internal short). But notable battery-to-battery variability even fresh from the factory? That was, I confess, news to me, although in retrospect I shouldn’t have been surprised, especially for off brand, “cheap” battery options.

The resultant effects of internal resistance variability on multi-battery combos, as suggested by my research results along with another set of fundamental electronics laws, this time from Kirchhoff, are intriguing (IMHO, at least). For multiple batteries connected in series, as I’ve recently editorially inferred by analogy to solar panel connections, the outcomes of a higher-than-spec internal resistance for one of them are reduced aggregate output voltage along with bottlenecked peak current flow. Speaking of current, and on the other hand, batteries connected in parallel—where incremental peak current output potential is one key motivation for this organization, along with increased aggregate charge capacity—are hampered in both of these regards when one of the batteries is high resistance-compromised.

Multi-cell battery pack structures that connect their contents both in serial and parallel are increasingly common, both to boost the effective voltage (serial) and increase overall system runtime (parallel). As I was writing this post, for example, I came across editorial coverage of a YouTuber’s (modestly successful) project to power a (modestly equipped) desktop PC motherboard using only AA batteries:

You’ll see that he has four rows of 16 batteries each. Do the math and you’ll conclude, as I did (unless my methodology was flawed, which is always a possibility; if so, let me know in the comments) that each 16-battery bank is serially tethered (to generate ~25 V) and the four banks then connect in parallel (to boost capacity, therefore runtime). Battery degradation anywhere within the series/parallel cluster will thus result in both voltage and capacity compromises.

The YouTuber’s commentary, elementary as it may be, also makes important points about the importance of robust wiring and connectors, both topics which an excellent white paper (PDF) I came across in my research, published by Victron Energy, discusses at length. While both wiring and connectors, along with the batteries themselves, have resistances typically measured in dozens to hundreds of mΩ (that’s milli, not Mega), none is a perfect conductor. Use, for example, excessively thin wire, and you’ll end up with performance-degrading current flow constraints (along with maybe a fire). The same goes for a corroded battery contact, as anyone who’s dealt with a geriatric vehicle battery likely already knows. And each wiring run’s length is also a critical factor; if one span of a multi-battery parallel configuration is notably longer than the other(s), the resultant (slightly, but still) higher resistance will act akin to higher-than-average resistance in the battery itself.

More to say (but not today)

With brevity in mind, I’m only focusing here on the more common case of higher-than-average internal battery resistance (initially and, especially, over time). That said, as I already alluded to with my earlier “internal short” comments, resistance can also both inherently exist and evolve over time in the opposite (lower) direction. Such a situation is, perhaps obviously, particularly problematic in a multi-battery parallel configuration, both for the affected battery, the others in the parallel bank, and whatever they’re commonly powering.

For similar brevity reasons, I’m also covering today only situations where the installed batteries are either non-rechargeable or are removed for recharging. Multi-battery packs recharged in situ (while installed inside a portable power unit, for example) translate to an even more complicated scenario involving, among other factors, the critical importance (and difficulty) of balancing the various cells within the likely series/parallel cluster. The earlier-mentioned Vitron Energy white paper also explores this topic at length. More generally, I also found the various resources at Cadex Electronics’ Battery University quite helpful. And I’ll likely have more to say about these topics in future posts as well. Until then, and as always, I welcome your thoughts in the comments!

—Brian Dipert is the Principal at Sierra Media and a former technical editor at EDN Magazine, where he still regularly contributes as a freelancer.

Related Content

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• Inside the battery: A quick look at internal resistance 
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• Cell balancing maximizes the capacity of multi-cell batteries
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• Active balancing: How it works and what are its advantages
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• Internal Resistance Tester for Batteries
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The post Single-battery failures in multi-battery arrangements: diagnosing selective cell derangements appeared first on EDN.

The rapid integration of artificial intelligence (AI) and machine learning (ML) into safety-critical systems is one of the most significant engineering challenges of our time. Whether it’s a medical device diagnosing an anomaly, an autonomous robot on a factory floor, or a train’s obstacle detection system, the question is no longer if we will use AI, but how can we guarantee its safe operation?

Enter ISO/PAS 8800, a new specification focused on the safety of AI applications in road vehicles. At first glance, the title implies that it’s solely for the automotive industry. However, for engineers in medical devices, industrial automation, rail, aerospace, and defense, dismissing this document as “just for cars” would be a missed opportunity.

Figure 1 ISO/PAS 8800 provides consensus-based framework for managing the unique risks of AI. Source: Parasoft