On-Board FPGA Trace Compression

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  Traces Decompressed

Inspiration

I work a decent amount with FPGAs, and sim debugging can only do so much, but board debugging is very hard (extraordinarily high throughput and low RAM)

What it does

Locally compresses signal data from the board to allow for far more data to be gathered in the small RAM, to later be transmitted off chip and be analyzed, losslessly, in as minimal area as possible.

Traces generate truly tremendous amounts of data. Just one 16 bit bus at 100Mhz is 16*100M = 1.6 billion bits per second = 200MB per second. That's just one bus!
There is no transmission protocal fast enough for a full system, and FPGA BRAM is usuualy sub 1 GB. So, working around our limitations, if we locally compress the data, we can fit signifigantly more in the same limited BRAM, for later reading. Luckily, FPGA data is fairly predictable, and thus easily compressed.

I used 4 different data compression modes:

Compression Strategies:

RAW: if data changes too much to properly compress: don’t compress it! Delta magnitudes are large Run lengths are short Entropy is high

RAW: 2.5 bytes: 2 bits for code, 2 bits for signal 8 bits for first half of value 8 bits for second half of value

Normal RLE (Run-Length Encoding Mode) Long runs of the same number. Replace 9,9,9,9 with {9,4} (4 9s in a row)

RLE: 1 byte: 2 bits for code, 2 bits for signal, 4 bits for run length

Delta RLE Mode Long runs of the same delta (like a counter). Replace 1,2,3,4 with {1,4} (a run of 4 numbers that are each 1 higher then the last)

Delta RLE: 1 byte: 2 bits for code, 2 bits for signal, 4 bits for run length

Small Delta Some signals change frequently and unpredictably but only by a small amount. This can be saved in a much smaller space then RAW just by saving a small delta instead of the full value

Small Delta: 1 byte 2 bits for code, 2 bits for signal, 4 bits for delta

How we built it

This is designed for the Basys3 FPGA test board, written in SystemVerilog using Vivado

Challenges we ran into

This is crazy hard to testbench! Also, UART is very confusing, and I'm not a CS student so the Python receiver I wrote may be literally all wrong. Being alone on this project was also unfortunate, my teammates had to drop at the last minute

Accomplishments that we're proud of

My compression algorithim! It takes up just 0.89% of the LUTs and 0.59% of the registers, allowing it to piggyback on other much larger projects without causing issues.

What we learned

The basics of UART, how to save to BRAM, how to do low area compression

What's next for On-Board FPGA Trace Compression

Actually getting the data to decompress properly. I am like 95% sure it is to do with how I am saving to BRAM, but I'm unsure

Built With

• basys3
• systemverilog
• vivado