MandelBoard

Background

This was the final project for a computer organization course in which we were allowed to make anything. I had wanted to try rendering the Mandelbrot set for quite some time and I had never gotten around to it, so my partner and I decided to make a renderer for it. This project was partially finished during the course, at which point we were successfully able to render the set. After the course had ended, it was brought to it's present state in a polishing phase, in which I:

• Added the ability to pan around and zoom into the set
• Parallelized the computations used determine if a pixel is in the set or not

How we built it

Because we're just doing a set of computations, finite state machines (FSMs) became an attractive tool for solving our problem. The circuit consists of a set of three computational FSMs that mirror an algorithm for rendering the set. During the polishing phase, this set of three computational FSMs was replicated, each set being responsible for a different region of pixels, allowing us to do computations in parallel, thereby speeding up the rendering process. Controlling these sets of computational FSMs is a module that responds to user input.

Challenges we ran into

Because we were performing arithmetic on non-integral values, we needed to figure out how to represent numbers with fractional parts discretely, as well as carrying out arithmetic on these numbers correctly. After receiving some advice from our course instructor, we opted to use fixed-point numbers. After a lot of trial and error (and assistance with Verilog where needed), we were able to start performing the arithmetic correctly. Additionally, Hardware design / hardware description languages were new paradigms for us, so we faced a learning curve with that.

Oh, and I have to mention off-by-one errors too. Quite a pain.

Accomplishments that I'm proud of

I managed to do something interesting in an environment I was new to (i.e. hardware programming).

What I learned

The coolest thing I learned / realized was the notion of parallel computation on an FPGA such as the De1. Anything you deploy to an FPGA can essentially be thought of as a machine, which takes up a physical amount of space. So long as there's space left on the FPGA, you can replicate parts of that "machine" to speed up your computations! For a renderer such as this, that can lead to massive increases in performance.

Built With

• verilog