About the project

What inspired us

We were motivated by the hackathon theme: finding problems where custom digital hardware can outperform general-purpose software in determinism, throughput, and efficiency. Image deblurring was a strong fit because it is compute-dense, structured, and naturally expressed as a streaming pipeline.

How we built it

We built a grayscale deblurring accelerator in SystemVerilog using the following modules:

  1. 2D FFT on the input image
  2. Wiener gain generation in frequency domain
  3. Complex multiplication (Y(u,v)\cdot G(u,v))
  4. 2D IFFT to reconstruct the deblurred image

We integrated these blocks in a top module with handshake-based streaming I/O, then created a Python + Verilator + C++ flow to feed images, run hardware, reconstruct output images, and collect metrics. Finally, we wrapped the design for Tiny Tapeout and validated it through synthesis/hardening checks.

Challenges we faced

The biggest challenges were:

  • fixed-point precision/scaling consistency across FFT, Wiener, multiply, and IFFT,
  • mapping/order alignment between transform stages,
  • balancing deblur quality with strict area/frequency constraints,
  • debugging hardening issues in the physical design flow.

What we learned

We learned that hardware optimization is a system-level problem, not only an individual-module problem. For instance, after integrating FFT, Wiener, complex multiply, and IFFT, the key improvements came from cross-stage fixed-point tuning, stream handshake scheduling, and frame-level control so each stage is fed correctly with deterministic behavior. In short, end-to-end dataflow and numeric consistency mattered more than optimizing any single block in isolation.

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