HDL to Minecraft

Inspiration

Previous masters students attempted this, however they didn't add states and D type flip flops to their project, which we accomplished.

What it does

Our project takes a verilog file, which is a hardware description language defining logic gates exactly as you'd find on a chip. It parses the verilog file and builds the logic gate circuit graph representation which we then display in Minecraft and run.

How we built it

To convert a verilog file to JSON we used an existing open source library yosys. This JSON file was then parsed into a python readable format. We then randomly placed the logic gates with enough spacing between them on a new graph. Djikstra's algorithm was used to route wires between the logic gates in 3 dimensions and avoiding collisions. The resulting graph then was converted into a Minecraft schema file, which can be opened in a Minecraft world.

Challenges we ran into

Routing was especially hard due to the nature of redstone and repeaters in order to sustain a redstone connection. The routing problem was a huge challenge for us, the problem is that we need to find connections between logic gates with no proper optimised solution. This is also a challenge that hardware companies face, such as Intel.

Accomplishments that we're proud of

We managed to get all logic gates to be generated in Minecraft from a verilog file. Getting repeaters to function within the logic circuit Minecraft representation.

What we learned

We learnt about what verilog is, along with the routing problem, how to do Djikstra's algorithm in 3D and Minecraft schemas. We learned the common challenges chip manufacturers face when designing chips.