Team 25: DUC - Data Unlimited Compile for FPGAs

Abstract

CPUs, being scalar processors, are painfully slow at specialized, data-parallel computation. Chips will often have custom hardware for signal processing, video compression, machine learning, and other computationally expensive tasks. However, custom silicon chips (ASCICs) are extremely expensive and slow to design, verify, and manufacture. Moreover, they cannot be revised once fabricated. FPGAs (field programmable gate arrays) can implement arbitrary digital circuits, but also come with the advantage of being reconfigurable after fabrication. An FPGA chip has switches for all the logic on the chip such that connections can be rerouted electronically. Somewhat similar to ASIC design, designing for FPGAs is currently extremely slow for large designs. This makes testing changes and debugging designs much more time consuming and mentally taxing than developing software. Furthermore, FPGA design often requires lots of expertise in knowing all the idiosyncrasies of the target hardware and software toolchain. The problem we are attempting to tackle with our project is both the time commitment and expertise required to design FPGA-based accelerators. Our project is a framework that will enable software engineers to utilize hardware software co-design without new knowledge or training. Currently, there are some methods to achieve this such as breaking down the compilation into heterogeneous building blocks, but they are quite limited in that there is not enough embedded memory in the FPGA fabric alone to store them. We hope to alleviate this issue by allowing the DRAM to be networked with the building blocks and have access to their substantially larger memory.

Built With

• prflow