<?xml version="1.0" encoding="US-ASCII"?>
<dblp>
<phdthesis key="phd/ch/Afshar12" mdate="2025-06-25">
<author>Hadi Parandeh-Afshar</author>
<title>Closing the Gap between FPGA and ASIC - Balancing Flexibility and Efficiency.</title>
<school>EPFL, Switzerland</school>
<year>2012</year>
<ee>https://doi.org/10.5075/epfl-thesis-5339</ee>
<ee>https://infoscience.epfl.ch/record/175046</ee>
<ee>https://infoscience.epfl.ch/handle/20.500.14299/77930</ee>
<ee>https://hdl.handle.net/20.500.14299/77930</ee>
<ee>https://www.base-search.net/Record/74b6333780f9390d5eb638fcf793fbfa5ace5d8cd196bc170e085c0c20fb42d9</ee>
<note type="source">base-search.net (ftinfoscience:oai:infoscience.tind.io:175046)</note>
</phdthesis>
</dblp>
