On High-Bandwidth Data Cache Design for Multi-Issue Processors.

Jude A. Rivers Gary S. Tyson Edward S. Davidson Todd M. Austin On High-Bandwidth Data Cache Design for Multi-Issue Processors. 46-56 1997 conf/micro/1997 MICRO https://doi.org/10.1109/MICRO.1997.645796 https://doi.ieeecomputersociety.org/10.1109/MICRO.1997.645796 https://dl.acm.org/doi/10.5555/266800.266805 db/conf/micro/micro97.html#RiversTDA97