15.4 A 20-to-1000MHz ±14ps peak-to-peak jitter reconfigurable multi-output all-digital clock generator using open-loop fractional dividers in 65nm CMOS.

Ahmed Elkholy Amr Elshazly Saurabh Saxena Guanghua Shu Pavan Kumar Hanumolu 15.4 A 20-to-1000MHz ±14ps peak-to-peak jitter reconfigurable multi-output all-digital clock generator using open-loop fractional dividers in 65nm CMOS. 272-273 2014 ISSCC https://doi.org/10.1109/ISSCC.2014.6757431 conf/isscc/2014 db/conf/isscc/isscc2014.html#ElkholyESSH14