<?xml version="1.0" encoding="US-ASCII"?>
<dblp>
<inproceedings key="conf/glvlsi/JiangYSS19" mdate="2019-05-16">
<author>Zhewei Jiang</author>
<author>Shihui Yin</author>
<author>Jae-sun Seo</author>
<author>Mingoo Seok</author>
<title>XNOR-SRAM: In-Bitcell Computing SRAM Macro based on Resistive Computing Mechanism.</title>
<pages>417-422</pages>
<year>2019</year>
<booktitle>ACM Great Lakes Symposium on VLSI</booktitle>
<ee>https://doi.org/10.1145/3299874.3319458</ee>
<crossref>conf/glvlsi/2019</crossref>
<url>db/conf/glvlsi/glvlsi2019.html#JiangYSS19</url>
</inproceedings>
</dblp>
