<?xml version="1.0" encoding="US-ASCII"?>
<dblp>
<inproceedings key="conf/fpga/SuDLLWS024" mdate="2025-01-19">
<author orcid="0000-0002-8655-8536">Chunyou Su</author>
<author orcid="0000-0002-3007-4890">Linfeng Du</author>
<author orcid="0000-0002-0390-2320">Tingyuan Liang</author>
<author orcid="0009-0002-1594-2335">Zhe Lin 0007</author>
<author orcid="0000-0001-7449-9834">Maolin Wang 0002</author>
<author orcid="0000-0002-4532-2017">Sharad Sinha</author>
<author orcid="0000-0002-7622-6714">Wei Zhang 0012</author>
<title>GraFlex: Flexible Graph Processing on FPGAs through Customized Scalable Interconnection Network.</title>
<pages>143-153</pages>
<year>2024</year>
<booktitle>FPGA</booktitle>
<ee>https://doi.org/10.1145/3626202.3637573</ee>
<ee>https://www.wikidata.org/entity/Q130813095</ee>
<crossref>conf/fpga/2024</crossref>
<url>db/conf/fpga/fpga2024.html#SuDLLWS024</url>
</inproceedings>
</dblp>
