Shaping a VLSI wire to minimize Elmore delay.

John P. Fishburn Shaping a VLSI wire to minimize Elmore delay. 244-251 1997 ED&TC https://doi.org/10.1109/EDTC.1997.582366 https://doi.ieeecomputersociety.org/10.1109/EDTC.1997.582366 https://dl.acm.org/doi/10.5555/787260.787672 conf/date/1997 db/conf/date/edtc1997.html#Fishburn97