Efficient Techniques for Modeling Chip-Level Interconnect, Substrate and Package Parasitics.

Peter Feldmann Sharad Kapur David E. Long Efficient Techniques for Modeling Chip-Level Interconnect, Substrate and Package Parasitics. 418-417 1999 conf/date/1999 DATE https://doi.org/10.1109/DATE.1999.761158 https://doi.ieeecomputersociety.org/10.1109/DATE.1999.761158 https://doi.org/10.1145/307418.307536 db/conf/date/date1999.html#FeldmanKL99