A 21-Gb/s, 0.96-pJ/bit serial receiver with non-50% duty-cycle clocking 1-tap decision feedback equalizer in 65nm CMOS.

Yang You Sudipto Chakraborty Rui Wang 0035 Jinghong Chen A 21-Gb/s, 0.96-pJ/bit serial receiver with non-50% duty-cycle clocking 1-tap decision feedback equalizer in 65nm CMOS. 1-4 2015 A-SSCC https://doi.org/10.1109/ASSCC.2015.7387469 conf/asscc/2015 db/conf/asscc/asscc2015.html#YouCWC15