I attended the nineteenth design automation conference.

C. L. Liu 0001 Chung Laung (Dave) Liu 劉炯朗 National Cheng Kung University, Tainan, Taiwan National Tsing Hua University, Hsinchu, Taiwan IEEE James H. Mulligan, Jr. Education Medal https://mathgenealogy.org/id.php?id=4786 https://en.wikipedia.org/wiki/Chung_Laung_Liu https://www.wikidata.org/entity/Q5116323 http://isni.org/isni/0000000109849834 https://viaf.org/viaf/70175627 https://id.loc.gov/authorities/names/n50053480 https://d-nb.info/gnd/1034180517 https://mathscinet.ams.org/mathscinet/MRAuthorID/201668 https://zbmath.org/authors/?q=ai:liu.chung-laung C. L. Liu C. L. Liu 0002 East China University of Science and Technology, Shanghai, China C. L. Liu 0003 Shandong University, Department of Physics, Jinan, China C. L. Liu 0004 Hebei University of Technology, School of Mechanical Engineering, Tianjin, China C. L. Liu 0001 I attended the nineteenth design automation conference. 69-70 2012 ISPD https://doi.org/10.1145/2160916.2160932 conf/ispd/2012 db/conf/ispd/ispd2012.html#Liu12 C. L. Liu 0001 The High Walls have Crumpled. 21-24 2005 conf/vlsid/2005 VLSI Design https://doi.org/10.1109/ICVD.2005.163 https://doi.ieeecomputersociety.org/10.1109/ICVD.2005.163 db/conf/vlsid/vlsid2005.html#Liu05

Ali Pinar C. L. Liu 0001 Compacting sequences with invariant transition frequencies. 214-221 2003 8 ACM Trans. Design Autom. Electr. Syst. 2 https://doi.org/10.1145/762488.762492 https://www.wikidata.org/entity/Q130972745 db/journals/todaes/todaes8.html#PinarL03

Ki-Wook Kim Seong-Ook Jung Unni Narayanan C. L. Liu 0001 Sung-Mo Kang Noise-aware interconnect power optimization in domino logic synthesis. 79-89 2003 11 IEEE Trans. Very Large Scale Integr. Syst. 1 https://doi.org/10.1109/TVLSI.2002.801630 db/journals/tvlsi/tvlsi11.html#KimJNLK03

Ki-Wook Kim Seong-Ook Jung Taewhan Kim 0001 Prashant Saxena C. L. Liu 0001 S.-M. S. Kang Coupling delay optimization by temporal decorrelation using dual threshold voltage technique. 879-887 2003 11 IEEE Trans. Very Large Scale Integr. Syst. 5 https://doi.org/10.1109/TVLSI.2003.817111 db/journals/tvlsi/tvlsi11.html#KimJKSLK03

Ki-Seok Chung Taewhan Kim 0001 C. L. Liu 0001 A Complete Model for Glitch Analysis in Logic Circuits. 137-154 2002 11 J. Circuits Syst. Comput. 2 https://doi.org/10.1142/S0218126602000367 db/journals/jcsc/jcsc11.html#ChungKL02

Ki-Wook Kim Taewhan Kim 0001 C. L. Liu 0001 Sung-Mo Kang Domino logic synthesis based on implication graph. 232-240 2002 21 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2 https://doi.org/10.1109/43.980261 db/journals/tcad/tcad21.html#KimKLK02

Ki-Wook Kim Taewhan Kim 0001 TingTing Hwang Sung-Mo Kang C. L. Liu 0001 Logic transformation for low-power synthesis. 265-283 2002 7 ACM Trans. Design Autom. Electr. Syst. 2 https://doi.org/10.1145/544536.544539 db/journals/todaes/todaes7.html#KimKHKL02

Ki-Seok Chung Rajesh K. Gupta 0001 Taewhan Kim 0001 C. L. Liu 0001 Synthesis and Optimization of Combinational Interface Circuits. 243-261 2002 31 J. VLSI Signal Process. 3 https://doi.org/10.1023/A:1015413306258 db/journals/vlsisp/vlsisp31.html#ChungGKL02

S. L. Lung Dennis Lin S. S. Chen Gary Weng C. L. Liu 0001 S. C. Lai C. W. Tsai T. B. Wu Rich Liu Modularized low temperature LNO/PZT/LNO ferroelectric capacitor-over-interconnect (COI) FeRAM for advanced SOC (ASOC) application. 479-482 2002 CICC https://doi.org/10.1109/CICC.2002.1012882 conf/cicc/2002 db/conf/cicc/cicc2002.html#LungLCWLLTWL02 Shih-Liang Chen TingTing Hwang C. L. Liu 0001 A technology mapping algorithm for CPLD architectures. 204-210 2002 FPT https://doi.org/10.1109/FPT.2002.1188683 conf/fpt/2002 db/conf/fpt/fpt2002.html#ChenHL02

Prashant Saxena C. L. Liu 0001 Optimization of the maximum delay of global interconnects duringlayer assignment. 503-515 2001 20 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 4 https://doi.org/10.1109/43.918209 db/journals/tcad/tcad20.html#SaxenaL01

Chau-Shen Chen TingTing Hwang C. L. Liu 0001 Architecture driven circuit partitioning. 383-389 2001 9 IEEE Trans. Very Large Scale Integr. Syst. 2 https://doi.org/10.1109/92.924060 db/journals/tvlsi/tvlsi9.html#ChenHL01

Ki-Seok Chung Taewhan Kim 0001 C. L. Liu 0001 G-vector: A New Model for Glitch Analysis in Logic Circuits. 235-251 2001 27 J. VLSI Signal Process. 3 https://doi.org/10.1023/A:1008139232134 db/journals/vlsisp/vlsisp27.html#ChungKL01

Ki-Wook Kim Seong-Ook Jung Prashant Saxena C. L. Liu 0001 Sung-Mo Kang Coupling Delay Optimization by Temporal Decorrelation using Dual Threshold Voltage Technique. 732-737 2001 conf/dac/2001 DAC https://doi.org/10.1145/378239.379056 db/conf/dac/dac2001.html#KimJSLK01 Yi-Yu Liu Kuo-Hua Wang TingTing Hwang C. L. Liu 0001 Binary decision diagram with minimum expected path length. 708-712 2001 conf/date/2001 DATE https://doi.org/10.1109/DATE.2001.915105 https://doi.ieeecomputersociety.org/10.1109/DATE.2001.915105 http://dl.acm.org/citation.cfm?id=367858 db/conf/date/date2001.html#LiuWHL01

Prashant Saxena C. L. Liu 0001 A postprocessing algorithm for crosstalk-driven wire perturbation. 691-702 2000 19 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 6 https://doi.org/10.1109/43.848090 db/journals/tcad/tcad19.html#SaxenaL00

Chaeryung Park Taewhan Kim 0001 C. L. Liu 0001 An Integrated Approach to Data Path Synthesis for Behavioral-level Power Optimization. 381-396 2000 11 VLSI Design 4 https://doi.org/10.1155/2000/76384 db/journals/vlsi/vlsi11.html#ParkKL00

Junhyung Um Taewhan Kim 0001 C. L. Liu 0001 A fine-grained arithmetic optimization technique for high-performance/low-power data path synthesis. 98-103 2000 conf/dac/2000 DAC https://doi.org/10.1145/337292.337325 db/conf/dac/dac2000.html#UmKL00 Ki-Wook Kim Kwang-Hyun Baek Naresh R. Shanbhag C. L. Liu 0001 Sung-Mo Kang Coupling-Driven Signal Encoding Scheme for Low-Power Interface Design. 318-321 2000 conf/iccad/2000 ICCAD db/conf/iccad/iccad2000.html#KimBSLK00 https://doi.org/10.1109/ICCAD.2000.896492 https://doi.ieeecomputersociety.org/10.1109/ICCAD.2000.896492 http://dl.acm.org/citation.cfm?id=602973 Ki-Wook Kim Seong-Ook Jung Unni Narayanan C. L. Liu 0001 Sung-Mo Kang Noise-aware power optimization for on-chip interconnect. 108-113 2000 conf/islped/2000 ISLPED https://doi.org/10.1145/344166.344537 db/conf/islped/islped2000.html#KimJNLK00

Peichen Pan C. L. Liu 0001 Partial Scan with Preselected Scan Signals. 1000-1005 1999 48 IEEE Trans. Computers 9 db/journals/tc/tc48.html#PanL99 https://doi.org/10.1109/12.795228 http://doi.ieeecomputersociety.org/10.1109/12.795228

Prashant Saxena C. L. Liu 0001 Crosstalk Minimization Using Wire Perturbations. 100-103 1999 conf/dac/1999 DAC https://doi.org/10.1145/309847.309887 db/conf/dac/dac99.html#SaxenaL99 Ki-Wook Kim Sung-Mo Kang TingTing Hwang C. L. Liu 0001 Logic Transformation for Low Power Synthesis. 158-162 1999 conf/date/1999 DATE https://doi.org/10.1109/DATE.1999.761112 https://doi.ieeecomputersociety.org/10.1109/DATE.1999.761112 https://doi.org/10.1145/307418.307480 db/conf/date/date1999.html#KimKHL99 Ki-Wook Kim C. L. Liu 0001 Sung-Mo Kang Implication graph based domino logic synthesis. 111-114 1999 conf/iccad/1999 ICCAD https://doi.org/10.1109/ICCAD.1999.810632 https://doi.ieeecomputersociety.org/10.1109/ICCAD.1999.810632 http://dl.acm.org/citation.cfm?id=339492.339593 db/conf/iccad/iccad1999.html#KimLK99 Junhyung Um Taewhan Kim 0001 C. L. Liu 0001 Optimal allocation of carry-save-adders in arithmetic optimization. 410-413 1999 conf/iccad/1999 ICCAD https://doi.org/10.1109/ICCAD.1999.810685 https://doi.ieeecomputersociety.org/10.1109/ICCAD.1999.810685 http://dl.acm.org/citation.cfm?id=339492.340050 db/conf/iccad/iccad1999.html#UmKL99 Chaeryung Park Taewhan Park C. L. Liu 0001 An efficient data path synthesis algorithm for behavioral-level power optimization. 294-297 1999 conf/iscas/1999 ISCAS (1) https://doi.org/10.1109/ISCAS.1999.777861 db/conf/iscas/iscas1999-1.html#ParkPL99 C. L. Liu 0001 From Time Sharing to Real Time-Sharing of a Really Good Time in the Last 40 Years. 5 1999 conf/rtss/1999 RTSS https://doi.org/10.1109/RTSS.1999.10000 https://doi.ieeecomputersociety.org/10.1109/RTSS.1999.10000 db/conf/rtss/rtss1999.html#Liu99 Prashant Saxena Peichen Pan C. L. Liu 0001 The Retiming of Single-Phase Clocked Circuits Containing Level-Sensitive Latches. 402-407 1999 conf/vlsid/1999 VLSI Design https://doi.org/10.1109/ICVD.1999.745189 https://doi.ieeecomputersociety.org/10.1109/ICVD.1999.745189 db/conf/vlsid/vlsid1999.html#SaxenaPL99

Peichen Pan Arvind K. Karandikar C. L. Liu 0001 Optimal clock period clustering for sequential circuits with retiming. 489-498 1998 17 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 6 https://doi.org/10.1109/43.703830 db/journals/tcad/tcad17.html#PanKL98

Peichen Pan C. L. Liu 0001 Optimal clock period FPGA technology mapping for sequential circuits. 437-462 1998 3 ACM Trans. Design Autom. Electr. Syst. 3 https://doi.org/10.1145/293625.293632 db/journals/todaes/todaes3.html#PanL98

Chaeryung Park Taewhan Kim 0001 C. L. Liu 0001 Register Allocation - A Hierarchical Reduction Approach. 269-285 1998 19 J. VLSI Signal Process. 3 https://doi.org/10.1023/A:1008073925779 db/journals/vlsisp/vlsisp19.html#ParkKL98

Prashant Saxena C. L. Liu 0001 A performance-driven layer assignment algorithm for multiple interconnect trees. 124-127 1998 conf/iccad/1998 ICCAD https://doi.org/10.1145/288548.288589 https://doi.ieeecomputersociety.org/10.1109/ICCAD.1998.742861 db/conf/iccad/iccad1998.html#SaxenaL98 Chau-Shen Chen TingTing Hwang C. L. Liu 0001 Architecture driven circuit partitioning. 408-411 1998 conf/iccad/1998 ICCAD https://doi.org/10.1145/288548.289062 https://doi.org/10.1109/ICCAD.1998.742905 https://doi.ieeecomputersociety.org/10.1109/ICCAD.1998.742905 db/conf/iccad/iccad1998.html#ChenHL98 Ali Pinar C. L. Liu 0001 Power invariant vector sequence compaction. 473-476 1998 conf/iccad/1998 ICCAD https://doi.org/10.1145/288548.289073 https://doi.ieeecomputersociety.org/10.1109/ICCAD.1998.742951 db/conf/iccad/iccad1998.html#PinarL98 Unni Narayanan Peichen Pan C. L. Liu 0001 Low power logic synthesis under a general delay model. 209-214 1998 conf/islped/1998 ISLPED https://doi.org/10.1145/280756.280900 db/conf/islped/islped1998.html#NarayananPL98 Ki-Seok Chung C. L. Liu 0001 Local transformation techniques for multi-level logiccircuits utilizing circuit symmetries for power reduction. 215-220 1998 conf/islped/1998 ISLPED https://doi.org/10.1145/280756.280904 db/conf/islped/islped1998.html#ChungL98

Peichen Pan Sai-keung Dong C. L. Liu 0001 Optimal Graph Constraint Reduction for Symbolic Layout Compaction. 560-574 1997 18 Algorithmica 4 db/journals/algorithmica/algorithmica18.html#PanDL97 https://doi.org/10.1007/PL00009173

Yachyang Sun Ting-Chi Wang Chak-Kuen Wong C. L. Liu 0001 Routing for symmetric FPGAs and FPICs. 20-31 1997 16 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1 https://doi.org/10.1109/43.559329 db/journals/tcad/tcad16.html#SunWWL97

Anmol Mathur C. L. Liu 0001 Timing-driven placement for regular architectures. 597-608 1997 16 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 6 https://doi.org/10.1109/43.640618 db/journals/tcad/tcad16.html#MathurL97

Chau-Shen Chen TingTing Hwang C. L. Liu 0001 Low Power FPGA Design - A Re-engineering Approach. 656-661 1997 conf/dac/1997 DAC https://doi.org/10.1145/266021.266312 db/conf/dac/dac97.html#ChenHL97 Unni Narayanan C. L. Liu 0001 Low power logic synthesis for XOR based circuits. 570-574 1997 conf/iccad/1997 ICCAD https://doi.org/10.1109/ICCAD.1997.643596 https://doi.ieeecomputersociety.org/10.1109/ICCAD.1997.643596 https://dl.acm.org/citation.cfm?id=266554 db/conf/iccad/iccad1997.html#NarayananL97 Arvind K. Karandikar Peichen Pan C. L. Liu 0001 Optimal Clock Period Clustering for Sequential Circuits with Retiming. 122-127 1997 conf/iccd/1997 ICCD db/conf/iccd/iccd97.html#KarandikarPL97 https://doi.org/10.1109/ICCD.1997.628858 https://doi.ieeecomputersociety.org/10.1109/ICCD.1997.628858

Peichen Pan Weiping Shi C. L. Liu 0001 Area Minimization for Hierarchical Floorplans. 550-571 1996 15 Algorithmica 6 db/journals/algorithmica/algorithmica15.html#PanSL96 https://doi.org/10.1007/BF01940881

Tong Gao C. L. Liu 0001 Minimum crosstalk channel routing. 465-474 1996 15 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 5 https://doi.org/10.1109/43.506134 db/journals/tcad/tcad15.html#GaoL96

Sue-Hong Chow Yi-Cheng Ho TingTing Hwang C. L. Liu 0001 Low power realization of finite state machines - a decomposition approach. 315-340 1996 1 ACM Trans. Design Autom. Electr. Syst. 3 https://doi.org/10.1145/234860.234862 db/journals/todaes/todaes1.html#ChowHHL96

Srilata Raman C. L. Liu 0001 Larry G. Jones Timing-Constrained FPGA Placement: A Force-Directed Formulation and Its Performance Evaluation. 345-355 1996 4 VLSI Design 4 https://doi.org/10.1155/1996/53238 db/journals/vlsi/vlsi4.html#Raman0J96

Taewhan Kim 0001 C. L. Liu 0001 An integrated algorithm for incremental data path synthesis. 265-285 1996 12 J. VLSI Signal Process. 3 https://doi.org/10.1007/BF00924989 db/journals/vlsisp/vlsisp12.html#KimL96

Peichen Pan C. L. Liu 0001 Optimal Clock Period FPGA Technology Mapping for Sequential Circuits. 720-725 1996 conf/dac/1996 DAC https://doi.org/10.1145/240518.240655 db/conf/dac/dac96.html#PanL96 Xiangfeng Chen Peichen Pan C. L. Liu 0001 Desensitization for Power Reduction in Sequential Circuits. 795-800 1996 conf/dac/1996 DAC https://doi.org/10.1145/240518.240668 db/conf/dac/dac96.html#ChenPL96 Anmol Mathur C. L. Liu 0001 Timing Driven Placement Reconfiguration for Fault Tolerance and Yield Enhancement in FPGAs. 165-169 1996 ED&TC https://doi.org/10.1109/EDTC.1996.494143 https://doi.ieeecomputersociety.org/10.1109/EDTC.1996.494143 https://dl.acm.org/doi/10.5555/787259.787574 conf/date/1996 db/conf/date/edtc1996.html#MathurL96 Srilata Raman C. L. Liu 0001 Larry G. Jones A Timing-Constrained Incremental Routing Algorithm for Symmetrical FPGAs. 170-175 1996 ED&TC https://doi.org/10.1109/EDTC.1996.494144 https://doi.ieeecomputersociety.org/10.1109/EDTC.1996.494144 https://dl.acm.org/doi/10.5555/787259.787576 conf/date/1996 db/conf/date/edtc1996.html#RamanLJ96 Vamsi Boppana Prashant Saxena Prithviraj Banerjee W. Kent Fuchs C. L. Liu 0001 A Parallel Algorithm for the Technology Mapping of LUT-Based FPGAs. 828-831 1996 conf/europar/1996-1 Euro-Par, Vol. I db/conf/europar/europar96-1.html#BoppanaSBFL96 https://doi.org/10.1007/3-540-61626-8_109 Peichen Pan C. L. Liu 0001 Technology Mapping of Sequential Circuits for LUT-Based FPGAs for Performance. 58-64 1996 conf/fpga/1996 FPGA https://doi.org/10.1145/228370.228379 db/conf/fpga/fpga96.html#PanL96 Ki-Seok Chung Rajesh K. Gupta 0001 C. L. Liu 0001 An algorithm for synthesis of system-level interface circuits. 442-447 1996 conf/iccad/1996 ICCAD https://doi.org/10.1109/ICCAD.1996.569835 https://doi.ieeecomputersociety.org/10.1109/ICCAD.1996.569835 https://dl.acm.org/citation.cfm?id=244852 db/conf/iccad/iccad1996.html#ChungGL96

Taewhan Kim 0001 C. L. Liu 0001 A new approach to the multiport memory allocation problem in data path synthesis. 133-160 1995 19 Integr. 3 https://doi.org/10.1016/0167-9260(95)00009-5 https://www.wikidata.org/entity/Q127865128 db/journals/integration/integration19.html#KimL95

Tong Gao C. L. Liu 0001 Minimum crosstalk switchbox routing. 161-180 1995 19 Integr. 3 https://doi.org/10.1016/0167-9260(95)00011-3 https://www.wikidata.org/entity/Q127526098 db/journals/integration/integration19.html#GaoL95

Peichen Pan C. L. Liu 0001 Area minimization for floorplans. 123-132 1995 14 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1 https://doi.org/10.1109/43.363119 db/journals/tcad/tcad14.html#PanL95

Ran Libeskind-Hadas Nimish Shrivastava Rami G. Melhem C. L. Liu 0001 Optimal Reconfiguration Algorithms for Real-Time Fault-Tolerant Processor Arrays. 498-511 1995 6 IEEE Trans. Parallel Distributed Syst. 5 https://doi.org/10.1109/71.382318 http://doi.ieeecomputersociety.org/10.1109/71.382318 db/journals/tpds/tpds6.html#Libeskind-HadasSML95

Peichen Pan C. L. Liu 0001 Partial Scan with Pre-selected Scan Signals. 189-194 1995 conf/dac/1995 DAC https://doi.org/10.1145/217474.217528 db/conf/dac/dac95.html#PanL95 Anmol Mathur Kuang-Chien Chen C. L. Liu 0001 Applications of Slack Neighborhood Graphs to Timing Driven Optimization Problems in FPGAs. 118-124 1995 conf/fpga/1995 FPGA https://doi.org/10.1145/201310.201329 db/conf/fpga/fpga95.html#MathurCL95 Anmol Mathur Kuang-Chien Chen C. L. Liu 0001 Re-engineering of timing constrained placements for regular architectures. 485-490 1995 conf/iccad/1995 ICCAD https://doi.org/10.1109/ICCAD.1995.480161 https://doi.ieeecomputersociety.org/10.1109/ICCAD.1995.480161 https://dl.acm.org/citation.cfm?id=225097 db/conf/iccad/iccad1995.html#MathurCL95

Taewhan Kim 0001 Noritake Yonezawa Jane W.-S. Liu C. L. Liu 0001 A scheduling algorithm for conditional resource sharing-a hierarchical reduction approach. 425-438 1994 13 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 4 https://doi.org/10.1109/43.275353 db/journals/tcad/tcad13.html#KimYLL94

Yachyang Sun C. L. Liu 0001 Routing in a New 2-Dimensional FPGA/FPIC Routing Architecture. 171-176 1994 conf/dac/1994 DAC https://doi.org/10.1145/196244.196327 db/conf/dac/dac94.html#SunL94 Srilata Raman C. L. Liu 0001 Larry G. Jones A delay driven FPGA placement algorithm. 277-282 1994 EURO-DAC http://dl.acm.org/citation.cfm?id=198263 conf/eurodac/1994 db/conf/eurodac/euro-dac1994.html#RamanLJ94 Anmol Mathur C. L. Liu 0001 Compression-relaxation: a new approach to performance driven placement for regular architectures. 130-136 1994 conf/iccad/1994 ICCAD https://doi.org/10.1109/ICCAD.1994.629755 https://doi.ieeecomputersociety.org/10.1109/ICCAD.1994.629755 https://dl.acm.org/citation.cfm?id=191379 db/conf/iccad/iccad1994.html#MathurL94 Peichen Pan Weiping Shi C. L. Liu 0001 Area minimization for hierarchical floorplans. 436-440 1994 conf/iccad/1994 ICCAD https://doi.org/10.1109/ICCAD.1994.629840 https://doi.ieeecomputersociety.org/10.1109/ICCAD.1994.629840 https://dl.acm.org/citation.cfm?id=191509 db/conf/iccad/iccad1994.html#PanSL94 Tong Gao C. L. Liu 0001 Minimum crosstalk switchbox routing. 610-615 1994 conf/iccad/1994 ICCAD https://doi.org/10.1109/ICCAD.1994.629884 https://doi.ieeecomputersociety.org/10.1109/ICCAD.1994.629884 https://dl.acm.org/citation.cfm?id=191585 db/conf/iccad/iccad1994.html#GaoL94

Jason Cong Bryan Preas C. L. Liu 0001 Physical models and efficient algorithms for over-the-cell routing in standard cell design. 723-734 1993 12 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 5 https://doi.org/10.1109/43.277618 db/journals/tcad/tcad12.html#CongPL93

Wei-Kuan Shih Jane W.-S. Liu C. L. Liu 0001 Modified Rate-Monotonic Algorithm for Scheduling Periodic Jobs with Deferred Deadlines. 1171-1179 https://doi.org/10.1109/32.249662 http://doi.ieeecomputersociety.org/10.1109/32.249662 1993 19 IEEE Trans. Software Eng. 12 db/journals/tse/tse19.html#ShihLL93

Taewhan Kim 0001 C. L. Liu 0001 Utilization of Multiport Memories in Data Path Synthesis. 298-302 1993 conf/dac/1993 DAC https://doi.org/10.1145/157485.164900 db/conf/dac/dac93.html#KimL93 Peichen Pan Sai-keung Dong C. L. Liu 0001 Optimal Graph Constraint Reduction for Symbolic Layout Compaction. 401-406 1993 conf/dac/1993 DAC https://doi.org/10.1145/157485.164950 db/conf/dac/dac93.html#PanDL93 Tong Gao Chung Laung (Dave) Liu Kuang-Chien Chen A performance driven hierarchical partitioning placement algorithm. 33-38 1993 EURO-DAC https://doi.org/10.1109/EURDAC.1993.410613 conf/eurodac/1993 db/conf/eurodac/euro-dac1993.html#GaoLC93 Chaeryung Park Taewhan Kim 0001 C. L. Liu 0001 Register allocation for data flow graphs with conditional branches and loops. 232-237 1993 EURO-DAC https://doi.org/10.1109/EURDAC.1993.410643 conf/eurodac/1993 db/conf/eurodac/euro-dac1993.html#ParkKL93 Yachyang Sun Ting-Chi Wang Chak-Kuen Wong C. L. Liu 0001 Routing for symmetric FPGAs and FPICs. 486-490 1993 conf/iccad/1993 ICCAD https://doi.org/10.1109/ICCAD.1993.580102 https://doi.ieeecomputersociety.org/10.1109/ICCAD.1993.580102 https://dl.acm.org/citation.cfm?id=259874 db/conf/iccad/iccad1993.html#SunWWL93 Tong Gao C. L. Liu 0001 Minimum crosstalk channel routing. 692-696 1993 conf/iccad/1993 ICCAD https://doi.org/10.1109/ICCAD.1993.580163 https://doi.ieeecomputersociety.org/10.1109/ICCAD.1993.580163 https://dl.acm.org/citation.cfm?id=259904 db/conf/iccad/iccad1993.html#GaoL93 Tong Gao Pravin M. Vaidya C. L. Liu 0001 A Performance Driven Macro-Cell Placement Algorithm. 147-152 1992 conf/dac/1992 DAC http://portal.acm.org/citation.cfm?id=113938.119627 db/conf/dac/dac92.html#GaoVL92 Peichen Pan C. L. Liu 0001 Area minimization for general floorplans. 606-609 1992 conf/iccad/1992 ICCAD https://doi.org/10.1109/ICCAD.1992.279305 https://doi.ieeecomputersociety.org/10.1109/ICCAD.1992.279305 https://dl.acm.org/citation.cfm?id=304175 db/conf/iccad/iccad1992.html#PanL92 Yachyang Sun C. L. Liu 0001 An Area Minimizer for Floorplans with L-Shaped Regions. 383-386 1992 conf/iccd/1992 ICCD db/conf/iccd/iccd1992.html#SunL92 https://doi.org/10.1109/ICCD.1992.276295 https://doi.ieeecomputersociety.org/10.1109/ICCD.1992.276295 C. L. Liu 0001 Fundamentals of Real-Time Scheduling (Extended Abstract). 1-7 1992 NATO ASI RTC https://doi.org/10.1007/978-3-642-88049-0_1 conf/nato/1992 db/conf/nato/rtc1992.html#Liu92

Nany Hasan C. L. Liu 0001 Minimum fault covering in reconfigurable arrays. 215-234 1991 11 Integr. 3 https://doi.org/10.1016/0167-9260(91)90047-O db/journals/integration/integration11.html#HasanL91

Philip K. McKinley Nany Hasan Ran Libeskind-Hadas C. L. Liu 0001 Disjoint Covers in Replicated Heterogeneous Arrays. 281-292 1991 4 SIAM J. Discret. Math. 2 db/journals/siamdm/siamdm4.html#McKinleyHLL91 https://doi.org/10.1137/0404026

Jason Cong C. L. Liu 0001 On the k-layer planar subset and topological via minimization problems. 972-981 1991 10 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 8 https://doi.org/10.1109/43.85735 db/journals/tcad/tcad10.html#CongL91

Tong Gao Pravo M. Vaidya C. L. Liu 0001 A New Performance Driven Placement Algorithm. 44-47 1991 conf/iccad/1991 ICCAD db/conf/iccad/iccad1991.html#GaoVL91 https://doi.org/10.1109/ICCAD.1991.185187 https://doi.ieeecomputersociety.org/10.1109/ICCAD.1991.185187 Taewhan Kim 0001 Jane W.-S. Liu C. L. Liu 0001 A Scheduling Algorithm for Conditional Resource Sharing. 84-87 1991 conf/iccad/1991 ICCAD db/conf/iccad/iccad1991.html#KimLL91 https://doi.org/10.1109/ICCAD.1991.185198 https://doi.ieeecomputersociety.org/10.1109/ICCAD.1991.185198 Yachyang Sun Sai-keung Dong Shinji Sato C. L. Liu 0001 A Channel Router for Single Layer Customization Technology. 436-439 1991 conf/iccad/1991 ICCAD db/conf/iccad/iccad1991.html#SunDSL91 https://doi.org/10.1109/ICCAD.1991.185297 https://doi.ieeecomputersociety.org/10.1109/ICCAD.1991.185297

Xianjin Yao C. L. Liu 0001 PLA logic minimization by simulated annealing. 243-257 1990 9 Integr. 3 https://doi.org/10.1016/0167-9260(90)90018-V db/journals/integration/integration9.html#YaoL90

Jason Cong C. L. Liu 0001 Over-the-cell channel routing. 408-418 1990 9 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 4 https://doi.org/10.1109/43.45872 db/journals/tcad/tcad9.html#CongL90

Jason Cong Bryan Preas C. L. Liu 0001 General Models and Algorithms for Over-the-Cell Routing in Standard Cell Design. 709-715 1990 conf/dac/1990 DAC https://doi.org/10.1145/123186.123448 db/conf/dac/dac90.html#CongPL90 Jason Cong C. L. Liu 0001 On the k-layer planar subset and via minimization problems. 459-463 1990 EURO-DAC https://doi.org/10.1109/EDAC.1990.136691 http://dl.acm.org/citation.cfm?id=950073 conf/eurodac/1990 db/conf/eurodac/euro-dac1990.html#CongL90 Xianjin Yao C. L. Liu 0001 Solution of a module orientation and rotation problem. 584-588 1990 EURO-DAC https://doi.org/10.1109/EDAC.1990.136714 http://dl.acm.org/citation.cfm?id=950102 conf/eurodac/1990 db/conf/eurodac/euro-dac1990.html#YaoL90 Nany Hasan C. L. Liu 0001 Fault covers in reconfigurable PLAs. 166-173 1990 FTCS https://doi.org/10.1109/FTCS.1990.89352 conf/ftcs/1990 db/conf/ftcs/ftcs1990.html#HasanL90

D. F. Wong 0001 C. L. Liu 0001 Floorplan Design of VLSI Circuits. 263-291 1989 4 Algorithmica 2 db/journals/algorithmica/algorithmica4.html#WongL89 https://doi.org/10.1007/BF01553890

Xiaojun Shen Y. Z. Cai C. L. Liu 0001 Clyde P. Kruskal Generalized latin squares I. 155-178 1989 25 Discret. Appl. Math. 1-2 https://doi.org/10.1016/0166-218X(89)90052-8 db/journals/dam/dam25.html#ShenCLK89

Thomas R. Mueller D. F. Wong 0001 C. L. Liu 0001 An enhanced bottom-up algorithm for floorplan design. 189-201 1989 7 Integr. 2 https://doi.org/10.1016/0167-9260(89)90036-9 db/journals/integration/integration7.html#MuellerWL89

Xianjin Yao Masaaki Yamada C. L. Liu 0001 A new approach to the pin assignment problem. 999-1006 1989 8 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9 https://doi.org/10.1109/43.35552 db/journals/tcad/tcad8.html#YaoYL89

Ran Libeskind-Hadas C. L. Liu 0001 Solutions to the Module Orientation and Rotation Problems by Neural Computation Networks. 400-405 1989 conf/dac/1989 DAC https://doi.org/10.1145/74382.74449 https://www.wikidata.org/entity/Q130990470 db/conf/dac/dac89.html#Libeskind-HadasL89 Sai-keung Dong Jason Cong C. L. Liu 0001 Constrained floorplan design for flexible blocks. 488-491 1989 ICCAD https://doi.org/10.1109/ICCAD.1989.76997 https://doi.ieeecomputersociety.org/10.1109/ICCAD.1989.76997 conf/iccad/1989 db/conf/iccad/iccad1989.html#DongCL89

Jason Cong Martin D. F. Wong C. L. Liu 0001 A new approach to three- or four-layer channel routing. 1094-1104 1988 7 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10 https://doi.org/10.1109/43.7808 db/journals/tcad/tcad7.html#CongWL88

Xianji Yao Masaaki Yamada C. L. Liu 0001 A New Approach to the Pin Assignment Problem. 566-572 1988 conf/dac/1988 DAC http://portal.acm.org/citation.cfm?id=285730.285822 db/conf/dac/dac88.html#YaoYL88 Nany Hasan C. L. Liu 0001 Minimum fault coverage in reconfigurable arrays. 348-353 1988 FTCS https://doi.org/10.1109/FTCS.1988.5342 conf/ftcs/1988 db/conf/ftcs/ftcs1988.html#HasanL88 Jingsheng Cong C. L. Liu 0001 Over-the-cell channel routing. 80-83 1988 ICCAD https://doi.org/10.1109/ICCAD.1988.122467 https://doi.ieeecomputersociety.org/10.1109/ICCAD.1988.122467 conf/iccad/1988 db/conf/iccad/iccad1988.html#CongL88 Nany Hasan Jason Cong C. L. Liu 0001 A new formulation of yield enhancement problems for reconfigurable chips. 520-523 1988 ICCAD https://doi.org/10.1109/ICCAD.1988.122562 https://doi.ieeecomputersociety.org/10.1109/ICCAD.1988.122562 conf/iccad/1988 db/conf/iccad/iccad1988.html#HasanCL88

H. W. Leong C. L. Liu 0001 Algorithms for permutation channel routing. 17-45 1987 5 Integr. 1 https://doi.org/10.1016/S0167-9260(87)80004-4 db/journals/integration/integration5.html#LeongL87

D. F. Wong 0001 C. L. Liu 0001 Array Optimization for VLSI Synthesis. 537-543 1987 conf/dac/1987 DAC https://doi.org/10.1145/37888.37968 db/conf/dac/dac87.html#WongL87

D. F. Wong 0001 C. L. Liu 0001 Compacted channel routing with via placement restrictions. 287-307 1986 4 Integr. 4 https://doi.org/10.1016/0167-9260(86)90011-8 db/journals/integration/integration4.html#WongL86

James L. Lewandowski C. L. Liu 0001 Jane W.-S. Liu An Algorithmic Proof of a Generalization of the Birkhoff-Von Neumann Theorem. 323-330 1986 7 J. Algorithms 3 db/journals/jal/jal7.html#LewandowskiLL86 https://doi.org/10.1016/0196-6774(86)90024-6

D. F. Wong 0001 C. L. Liu 0001 A new algorithm for floorplan design. 101-107 1986 conf/dac/1986 DAC https://doi.org/10.1145/318013.318030 db/conf/dac/dac1986.html#WongL86

Prakash V. Ramanan C. L. Liu 0001 Permutation Representation of k-Ary Trees. 83-98 1985 38 Theor. Comput. Sci. db/journals/tcs/tcs38.html#RamananL85 https://doi.org/10.1016/0304-3975(85)90211-7

Prakash V. Ramanan Jitender S. Deogun C. L. Liu 0001 A Personnel Assignment Problem. 132-144 1984 5 J. Algorithms 1 db/journals/jal/jal5.html#RamananDL84 https://doi.org/10.1016/0196-6774(84)90043-9

Jack R. Egan C. L. Liu 0001 Bipartite Folding and Partitioning of a PLA. 191-199 1984 3 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 3 https://doi.org/10.1109/TCAD.1984.1270075 db/journals/tcad/tcad3.html#EganL84

James L. Lewandowski C. L. Liu 0001 A branch and bound algorithm for optimal pla folding. 426-433 1984 DAC http://dl.acm.org/citation.cfm?id=800833 conf/dac/1984 db/conf/dac/dac1984.html#LewandowskiL84

W.-D. Wei C. L. Liu 0001 On a Periodic Maintenance Problem. 90-93 1983 2 Oper. Res. Lett. 2 db/journals/orl/orl2.html#WeiL83

James L. Lewandowski Jane W.-S. Liu C. L. Liu 0001 SS/TDMA Time Slot Assignment with Restricted Switching Modes. 149-154 1983 31 IEEE Trans. Commun. 1 https://doi.org/10.1109/TCOM.1983.1095734 db/journals/tcom/tcom31.html#LewandowskiLL83

D. T. Lee C. L. Liu 0001 C. K. Wong (g 0, g 1, ... g k)-Trees and Unary OL Systems. 209-217 1983 22 Theor. Comput. Sci. db/journals/tcs/tcs22.html#LeeLW83 https://doi.org/10.1016/0304-3975(83)90145-7

Hon Wai Leong C. L. Liu 0001 A new channel routing problem. 584-590 1983 DAC http://dl.acm.org/citation.cfm?id=800728 conf/dac/1983 db/conf/dac/dac1983.html#LeongL83

C. L. Liu 0001 Jane W.-S. Liu Arthur L. Liestman Scheduling with Slack Time. 31-41 1982 17 Acta Informatica db/journals/acta/acta17.html#LiuLL82 https://doi.org/10.1007/BF00262974

Jack R. Egan C. L. Liu 0001 Optimal bipartite folding of PLA. 141-146 1982 DAC https://doi.org/10.1145/800263.809199 conf/dac/1982 db/conf/dac/dac1982.html#EganL82 C. L. Liu 0001 Generation of trees. 45-53 1980 CLAAP conf/caap/1980 db/conf/caap/caap80.html#Liu80

Jane W.-S. Liu C. L. Liu 0001 Performance Analysis of Multiprocessor Systems Containing Functionally Dedicated Processors. 95-104 1978 10 Acta Informatica db/journals/acta/acta10.html#LiuL78 https://doi.org/10.1007/BF00260927

K. M. Chung C. L. Liu 0001 A generalization of Ramsey theory for graphs. 117-127 1978 21 Discret. Math. 2 https://doi.org/10.1016/0012-365X(78)90084-5 db/journals/dm/dm21.html#ChungL78

Sudarshan K. Dhall C. L. Liu 0001 On a Real-Time Scheduling Problem. 127-140 1978 26 Oper. Res. 1 https://doi.org/10.1287/opre.26.1.127 db/journals/ior/ior26.html#DhallL78

C. L. Liu 0001 Deterministic Job Scheduling in Computing Systems. 241-254 1976 conf/performance/1976 Performance db/conf/performance/performance1976.html#Liu76

C. L. Liu 0001 Sperner's theorem on maximal-sized antichains and its generalization. 133-139 1975 11 Discret. Math. 2 https://doi.org/10.1016/0012-365X(75)90005-9 db/journals/dm/dm11.html#Liu75

Jane W.-S. Liu C. L. Liu 0001 Bounds on Scheduling Algorithms for Heterogeneous Comnputing Systems. 349-353 1974 conf/ifip/1974 IFIP Congress db/conf/ifip/ifip74.html#LiuL74 N. F. Chen C. L. Liu 0001 On a Class of Scheduling Algorithms for Multiprocessors Computing Systems. 1-16 1974 conf/sagamore/1974 Sagamore Computer Conference db/conf/sagamore/sagamore1974.html#ChenL74 https://doi.org/10.1007/3-540-07135-0_106

C. L. Liu 0001 B. G. Ong Gregory R. Ruth A construction scheme for linear and non-linear codes. 171-184 1973 4 Discret. Math. 2 https://doi.org/10.1016/0012-365X(73)90080-0 db/journals/dm/dm4.html#LiuOR73

C. L. Liu 0001 James W. Layland Scheduling Algorithms for Multiprogramming in a Hard-Real-Time Environment. 46-61 1973 20 J. ACM 1 https://doi.org/10.1145/321738.321743 https://www.wikidata.org/entity/Q55879022 db/journals/jacm/jacm20.html#LiuL73 JACM/20/P0046.pdf

C. L. Liu 0001 Analysis of sorting algorithms. 453 1973 AFIPS National Computer Conference https://doi.org/10.1145/1499586.1499702 conf/afips/1973 db/conf/afips/ncc73.html#Liu73 C. K. Wong C. L. Liu 0001 J. Apter A drum scheduling algorithm. 267-275 1973 conf/automata/1973 Automatentheorie und Formale Sprachen db/conf/automata/automata1973.html#WongLA73 https://doi.org/10.1007/BFb0039164

C. L. Liu 0001 Analysis and Synthesis of Sorting Algorithms. 290-304 1972 1 SIAM J. Comput. 4 db/journals/siamcomp/siamcomp1.html#Liu72 https://doi.org/10.1137/0201021

Chin-Chong Tseng C. L. Liu 0001 Complementary sets of sequences. 644-652 1972 18 IEEE Trans. Inf. Theory 5 https://doi.org/10.1109/TIT.1972.1054860 db/journals/tit/tit18.html#TsengL72

Optimal Scheduling on Multi-Processor Computing Systems C. L. Liu 0001 155-160 conf/focs/FOCS13 1972 SWAT db/conf/focs/focs72.html#Liu72 https://doi.org/10.1109/SWAT.1972.16 https://doi.ieeecomputersociety.org/10.1109/SWAT.1972.16 Analysis of Sorting Algorithms C. L. Liu 0001 207-215 conf/focs/FOCS12 1971 SWAT db/conf/focs/focs71.html#Liu71 https://doi.org/10.1109/SWAT.1971.3 https://doi.ieeecomputersociety.org/10.1109/SWAT.1971.3

A Note on Definite Stochastic Sequential Machines C. L. Liu 0001 407-421 Inf. Control. April 1969 14 4 db/journals/iandc/iandc14.html#Liu69 https://doi.org/10.1016/S0019-9958(69)90106-5

C. L. Liu 0001 Lattice Functions, Pair Algebras, and Finite-State Machines. 442-454 1969 16 J. ACM 3 https://doi.org/10.1145/321526.321533 db/journals/jacm/jacm16.html#Liu69

C. L. Liu 0001 G. D. Chang R. E. Marks The design and implementation of a table driven compiler system. 691-697 1967 AFIPS Spring Joint Computing Conference https://doi.org/10.1145/1465482.1465593 conf/afips/1967s db/conf/afips/afips67s.html#LiuCM67

C. L. Liu 0001 Some algebraic properties of multi-threshold functions. 935-938 1966 15 IEEE Trans. Electron. Comput. 6 https://doi.org/10.1109/PGEC.1966.264482 db/journals/tc/tc15.html#Liu66

Pair Algebra and Its Application C. L. Liu 0001 103-112 conf/focs/FOCS7 1966 SWAT db/conf/focs/focs66.html#Liu66 https://doi.org/10.1109/SWAT.1966.16 https://doi.ieeecomputersociety.org/10.1109/SWAT.1966.16

C. L. Liu 0001 kth-Order Finite Automaton. 642 1964 13 IEEE Trans. Electron. Comput. 5 https://doi.org/10.1109/PGEC.1964.263751 db/journals/tc/tc13.html#Liu64a

Sequential-machine realization using feedback shift registers C. L. Liu 0001 209-227 conf/focs/FOCS5 1964 SWCT db/conf/focs/focs64.html#Liu64 https://doi.org/10.1109/SWCT.1964.24 https://doi.ieeecomputersociety.org/10.1109/SWCT.1964.24 J. Apter Kwang-Hyun Baek Prithviraj Banerjee Vamsi Boppana Y. Z. Cai G. D. Chang Chau-Shen Chen Kuang-Chien Chen N. F. Chen S. S. Chen Shih-Liang Chen Xiangfeng Chen Sue-Hong Chow K. M. Chung Ki-Seok Chung Jason Cong Jingsheng Cong Jitender S. Deogun Sudarshan K. Dhall Sai-keung Dong Jack R. Egan W. Kent Fuchs Tong Gao Rajesh K. Gupta 0001 Nany Hasan Yi-Cheng Ho TingTing Hwang Larry G. Jones Seong-Ook Jung S.-M. S. Kang Sung-Mo Kang Arvind K. Karandikar Ki-Wook Kim Taewhan Kim 0001 Clyde P. Kruskal S. C. Lai James W. Layland D. T. Lee H. W. Leong Hon Wai Leong James L. Lewandowski Ran Libeskind-Hadas Arthur L. Liestman Dennis Lin Jane W.-S. Liu Rich Liu Yi-Yu Liu S. L. Lung R. E. Marks Anmol Mathur Philip K. McKinley Rami G. Melhem Thomas R. Mueller Unni Narayanan B. G. Ong Peichen Pan Chaeryung Park Taewhan Park Ali Pinar Bryan Preas Srilata Raman Prakash V. Ramanan Gregory R. Ruth Shinji Sato Prashant Saxena Naresh R. Shanbhag Xiaojun Shen Weiping Shi Wei-Kuan Shih Nimish Shrivastava Yachyang Sun C. W. Tsai Chin-Chong Tseng Junhyung Um Pravin M. Vaidya Pravo M. Vaidya Kuo-Hua Wang Ting-Chi Wang W.-D. Wei Gary Weng Chak-Kuen WongC. K. Wong Martin D. F. WongD. F. Wong 0001 T. B. Wu Masaaki Yamada Xianji Yao Xianjin Yao Noritake Yonezawa