Graphiti: Formally Verified Out-of-Order Execution in Dataflow Circuits.

Paolo Ienne Swiss Federal Institute of Technology in Lausanne, Switzerland https://people.epfl.ch/paolo.ienne https://scholar.google.com/citations?user=oB0wsDcAAAAJ https://orcid.org/0000-0002-6142-7345 https://www.wikidata.org/entity/Q130805872 Yann Herklotz Ayatallah Elakhras Martina Camaioni Paolo Ienne Lana Josipovic Thomas Bourgeat Graphiti: Formally Verified Out-of-Order Execution in Dataflow Circuits. 821-837 2026 ASPLOS (2) https://doi.org/10.1145/3779212.3790166 conf/asplos/2026-2 db/conf/asplos/asplos2026-2.html#HerklotzECIJB26 Canberk Sönmez Mohamed Shahawy Paolo Ienne Chext: A Domain-specific Language for Safe and Agile Elastic Dataflow Accelerators. 37 2026 FPGA https://doi.org/10.1145/3748173.3779543 conf/fpga/2026 db/conf/fpga/fpga2026.html#SonmezSI26 Rouzbeh Pirayadi Ayatallah Elakhras Mirjana Stojilovic Paolo Ienne Out with LSQs: Custom Circuits for Memory Access Reordering in Dynamic HLS. 92-102 2026 FPGA https://doi.org/10.1145/3748173.3779204 conf/fpga/2026 db/conf/fpga/fpga2026.html#PirayadiESI26 Paolo Ienne Laura Pozzi 0001 Philip Brisk The Rise and Fall of Automatic Instruction-Set Extensions. 119-120 2025 ASAP https://doi.org/10.1109/ASAP65064.2025.00027 conf/asap/2025 db/conf/asap/asap2025.html#IennePB25 streams/conf/asap Ayatallah Elakhras Jiahui Xu Martin Erhart Paolo Ienne Lana Josipovic ElasticMiter: Formally Verified Dataflow Circuit Rewrites. 293-308 2025 ASPLOS (2) https://doi.org/10.1145/3676641.3715993 conf/asplos/2025-2 db/conf/asplos/asplos2025-2.html#ElakhrasXEIJ25 Canberk Sönmez Mohamed Shahawy Paolo Ienne HBMex: An Attachment for Nonbursting Accelerators to Enhance HBM Performance. 29-37 2025 FCCM https://doi.org/10.1109/FCCM62733.2025.00037 conf/fccm/2025 db/conf/fccm/fccm2025.html#SonmezSI25 Menzo Bouaissi Paolo Ienne Lana Josipovic Andrea Guerrieri DRSA: Accelerating Macro Placement on Commercial FPGAs. 287 2025 FCCM https://doi.org/10.1109/FCCM62733.2025.00059 conf/fccm/2025 db/conf/fccm/fccm2025.html#BouaissiIJG25 Louis Coulon Lucas Ramirez Jason Helge Anderson Mirjana Stojilovic Paolo Ienne FRIDA: Reconfigurable Arrays for Dynamically Scheduled High-Level Synthesis. 147-158 2025 FPGA https://doi.org/10.1145/3706628.3708880 conf/fpga/2025 db/conf/fpga/fpga2025.html#CoulonRASI25 Andrea Guerrieri Isaac John Wetenkamp Chris Lavin Eddie Hung Lana Josipovic Paolo Ienne Compile in Seconds and Run on an FPGA with DynaRapid. FPL 2025 1 conf/fpl/2025 https://doi.org/10.1109/FPL68686.2025.00068 db/conf/fpl/fpl2025.html#GuerrieriWLHJI25 streams/conf/fpl Louis Coulon Adham Ragab Jason Anderson 0001 Mirjana Stojilovic Paolo Ienne FRESCO: Efficient Subgraph Enumeration for Scalable Clustering in Heterogeneous CGRAs. 1-9 2025 ICCAD https://doi.org/10.1109/ICCAD66269.2025.11240852 conf/iccad/2025 db/conf/iccad/iccad2025.html#CoulonRASI25 streams/conf/iccad

Mohamed Shahawy Julien de Castelnau Paolo Ienne Bombyx: OpenCilk Compilation for FPGA Hardware Acceleration. 2025 November abs/2511.21346 CoRR https://doi.org/10.48550/arXiv.2511.21346 db/journals/corr/corr2511.html#abs-2511-21346 streams/journals/corr

Stefan Nikolic 0001 Paolo Ienne Exploring FPGA Switch-Blocks without Explicitly Listing Connectivity Patterns. 14:1-14:39 2024 March 17 ACM Trans. Reconfigurable Technol. Syst. 1 https://doi.org/10.1145/3597417 https://www.wikidata.org/entity/Q130805874 db/journals/trets/trets17.html#NikolicI24

Mohamed Shahawy Canberk Sönmez Cemalettin Belentepe Paolo Ienne HardCilk: Cilk-like Task Parallelism for FPGAs. 140-150 2024 FCCM https://doi.org/10.1109/FCCM60383.2024.00025 conf/fccm/2024 db/conf/fccm/fccm2024.html#ShahawySBI24 streams/conf/fccm Andrea Guerrieri Srijeet Guha Lana Josipovic Paolo Ienne DynaRapid: From C to FPGA in a Few Seconds. 40 2024 FPGA https://doi.org/10.1145/3626202.3637580 https://www.wikidata.org/entity/Q130805952 conf/fpga/2024 db/conf/fpga/fpga2024.html#GuerrieriGJI24 Ayatallah Elakhras Andrea Guerrieri Lana Josipovic Paolo Ienne Survival of the Fastest: Enabling More Out-of-Order Execution in Dataflow Circuits. 44-54 2024 FPGA https://doi.org/10.1145/3626202.3637556 conf/fpga/2024 db/conf/fpga/fpga2024.html#ElakhrasGJI24 Andrea Guerrieri Srijeet Guha Chris Lavin Eddie Hung Lana Josipovic Paolo Ienne DynaRapid: Fast-Tracking from C to Routed Circuits. 24-32 2024 FPL https://doi.org/10.1109/FPL64840.2024.00014 conf/fpl/2024 db/conf/fpl/fpl2024.html#GuerrieriGLHJI24 Canberk Sönmez Mohamed Shahawy Cemalettin Cem Belentepe Paolo Ienne FlexiMem: Flexible Shared Virtual Memory for PCIe-attached FPGAs. 78-86 2024 FPL https://doi.org/10.1109/FPL64840.2024.00020 conf/fpl/2024 db/conf/fpl/fpl2024.html#SonmezSBI24 Mohamed Shahawy Canberk Sönmez Cemalettin Belentepe Paolo Ienne HardCilk: Cilk-like Task Parallelism for FPGAs. 2024 April https://doi.org/10.5281/zenodo.10971564 Zenodo streams/repo/zenodo

Beatriz Borges Negar Foroutan Deniz Bayazit Anna Sotnikova Syrielle Montariol Tanya Nazaretzky Mohammadreza Banaei Alireza Sakhaeirad Philippe Servant Seyed Parsa Neshaei Jibril Frej Angelika Romanou Gail Weiss Sepideh Mamooler Zeming Chen 0001 Simin Fan Silin Gao Mete Ismayilzada Debjit Paul Alexandre Schöpfer Andrej Janchevski Anja Tiede Clarence Linden Emanuele Troiani Francesco Salvi Freya Behrens Giacomo Orsi Giovanni Piccioli Hadrien Sevel Louis Coulon Manuela Pineros-Rodriguez Marin Bonnassies Pierre Hellich Puck van Gerwen Sankalp Gambhir Solal Pirelli Thomas Blanchard Timothée Callens Toni Abi Aoun Yannick Calvino Alonso Yuri Cho Alberto Silvio Chiappa Antonio Sclocchi Étienne Bruno Florian Hofhammer Gabriel Pescia Geovani Rizk Leello Dadi Lucas Stoffl Manoel Horta Ribeiro Matthieu Bovel Yueyang Pan Aleksandra Radenovic Alexandre Alahi Alexander Mathis Anne-Florence Bitbol Boi Faltings Cécile Hébert Devis Tuia François Maréchal George Candea Giuseppe Carleo Jean-Cédric Chappelier Nicolas Flammarion Jean-Marie Fürbringer Jean-Philippe Pellet Karl Aberer Lenka Zdeborová Marcel Salathé Martin Jaggi Martin Rajman Mathias Payer Matthieu Wyart Michael Gastpar Michele Ceriotti Ola Svensson Olivier Lévêque Paolo Ienne Rachid Guerraoui Robert West 0001 Sanidhya Kashyap Valerio Piazza Viesturs Simanis Viktor Kuncak Volkan Cevher Philippe Schwaller Sacha Friedli Patrick Jermann Tanja Käser Antoine Bosselut Could ChatGPT get an Engineering Degree? Evaluating Higher Education Vulnerability to AI Assistants. 2024 abs/2408.11841 CoRR https://doi.org/10.48550/arXiv.2408.11841 db/journals/corr/corr2408.html#abs-2408-11841 streams/journals/corr

Jovan Blanusa Kubilay Atasu Paolo Ienne Fast Parallel Algorithms for Enumeration of Simple, Temporal, and Hop-constrained Cycles. 15:1-15:35 2023 September 10 ACM Trans. Parallel Comput. 3 https://doi.org/10.1145/3611642 db/journals/topc/topc10.html#BlanusaAI23

Lana Josipovic Axel Marmet Andrea Guerrieri Paolo Ienne Resource Sharing in Dataflow Circuits. 54:1-54:27 2023 December 16 ACM Trans. Reconfigurable Technol. Syst. 4 https://doi.org/10.1145/3597614 db/journals/trets/trets16.html#JosipovicMGI23

Paolo Ienne Introduction to the Special Section on FPGA 2022. 56:1-56:2 2023 December 16 ACM Trans. Reconfigurable Technol. Syst. 4 https://doi.org/10.1145/3618114 https://www.wikidata.org/entity/Q130827476 db/journals/trets/trets16.html#Ienne23

Ayatallah Elakhras Riya Sawhney Andrea Guerrieri Lana Josipovic Paolo Ienne Straight to the Queue: Fast Load-Store Queue Allocation in Dataflow Circuits. 39-45 2023 FPGA https://doi.org/10.1145/3543622.3573050 conf/fpga/2023 db/conf/fpga/fpga2023.html#ElakhrasSGJI23 Stefan Nikolic 0001 Paolo Ienne Regularity Matters: Designing Practical FPGA Switch-Blocks. 99-109 2023 FPGA https://doi.org/10.1145/3543622.3573192 https://www.wikidata.org/entity/Q130813457 conf/fpga/2023 db/conf/fpga/fpga2023.html#NikolicI23 Paolo Ienne Zhiru Zhang Proceedings of the 2023 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2023, Monterey, CA, USA, February 12-14, 2023 ACM FPGA 2023 978-1-4503-9417-8 https://doi.org/10.1145/3543622 db/conf/fpga/fpga2023.html

Jovan Blanusa Kubilay Atasu Paolo Ienne Fast Parallel Algorithms for Enumeration of Simple, Temporal, and Hop-Constrained Cycles. 2023 abs/2301.01068 CoRR https://doi.org/10.48550/arXiv.2301.01068 db/journals/corr/corr2301.html#abs-2301-01068

Jianyi Cheng Lana Josipovic George A. Constantinides Paolo Ienne John Wickerson DASS: Combining Dynamic & Static Scheduling in High-Level Synthesis. 628-641 2022 41 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 3 https://doi.org/10.1109/TCAD.2021.3065902 db/journals/tcad/tcad41.html#ChengJCIW22

Lana Josipovic Andrea Guerrieri Paolo Ienne From C/C++ Code to High-Performance Dataflow Circuits. 2142-2155 2022 41 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7 https://doi.org/10.1109/TCAD.2021.3105574 db/journals/tcad/tcad41.html#JosipovicGI22

Lana Josipovic Shabnam Sheikhha Andrea Guerrieri Paolo Ienne Jordi Cortadella Buffer Placement and Sizing for High-Performance Dataflow Circuits. 4:1-4:32 2022 15 ACM Trans. Reconfigurable Technol. Syst. 1 https://doi.org/10.1145/3477053 db/journals/trets/trets15.html#JosipovicSGIC22

Mikhail Asiatici Paolo Ienne Request, Coalesce, Serve, and Forget: Miss-Optimized Memory Systems for Bandwidth-Bound Cache-Unfriendly Applications on FPGAs. 13:1-13:33 2022 15 ACM Trans. Reconfigurable Technol. Syst. 2 https://doi.org/10.1145/3466823 https://www.wikidata.org/entity/Q125769064 db/journals/trets/trets15.html#AsiaticiI22

Stefan Nikolic 0001 Grace Zgheib Paolo Ienne Detailed Placement for Dedicated LUT-Level FPGA Interconnect. 37:1-37:33 2022 15 ACM Trans. Reconfigurable Technol. Syst. 4 https://doi.org/10.1145/3501802 https://www.wikidata.org/entity/Q130809001 db/journals/trets/trets15.html#NikolicZI22

Lana Josipovic Axel Marmet Andrea Guerrieri Paolo Ienne Resource Sharing in Dataflow Circuits. 1-9 2022 FCCM https://doi.org/10.1109/FCCM53951.2022.9786084 conf/fccm/2022 db/conf/fccm/fccm2022.html#JosipovicMGI22 Ayatallah Elakhras Andrea Guerrieri Lana Josipovic Paolo Ienne Unleashing Parallelism in Elastic Circuits with Faster Token Delivery. 253-261 2022 FPL https://doi.org/10.1109/FPL57034.2022.00046 conf/fpl/2022 db/conf/fpl/fpl2022.html#ElakhrasGJI22 Carmine Rizzi Andrea Guerrieri Paolo Ienne Lana Josipovic A Comprehensive Timing Model for Accurate Frequency Tuning in Dataflow Circuits. 375-383 2022 FPL https://doi.org/10.1109/FPL57034.2022.00063 conf/fpl/2022 db/conf/fpl/fpl2022.html#RizziGIJ22 Jovan Blanusa Paolo Ienne Kubilay Atasu Scalable Fine-Grained Parallel Cycle Enumeration Algorithms. 247-258 2022 SPAA https://doi.org/10.1145/3490148.3538585 conf/spaa/2022 db/conf/spaa/spaa2022.html#BlanusaIA22 Michael Adler Paolo Ienne FPGA '22: The 2022 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Virtual Event, USA, 27 February 2022 - 1 March 2022 ACM FPGA 2022 978-1-4503-9149-8 https://doi.org/10.1145/3490422 db/conf/fpga/fpga2022.html

Jovan Blanusa Paolo Ienne Kubilay Atasu Scalable Fine-Grained Parallel Cycle Enumeration Algorithms. 2022 abs/2202.09685 CoRR https://arxiv.org/abs/2202.09685 db/journals/corr/corr2202.html#abs-2202-09685

Mikhail Asiatici Damian Maiorano Paolo Ienne How Many CPU Cores is an FPGA Worth? Lessons Learned from Accelerating String Sorting on a CPU-FPGA System. 1405-1417 2021 93 J. Signal Process. Syst. 12 https://doi.org/10.1007/s11265-021-01686-8 db/journals/vlsisp/vlsisp93.html#AsiaticiMI21

Stefan Nikolic 0001 Francky Catthoor Zsolt Tokei Paolo Ienne Global Is the New Local: FPGA Architecture at 5nm and Beyond. 34-44 2021 FPGA https://doi.org/10.1145/3431920.3439300 https://www.wikidata.org/entity/Q130819808 conf/fpga/2021 db/conf/fpga/fpga2021.html#NikolicCTI21 Lana Josipovic Axel Marmet Andrea Guerrieri Paolo Ienne Resource Sharing in Dataflow Circuits. 226 2021 FPGA https://doi.org/10.1145/3431920.3439472 conf/fpga/2021 db/conf/fpga/fpga2021.html#JosipovicMGI21 Stefan Nikolic 0001 Paolo Ienne Turning PathFinder Upside-Down: Exploring FPGA Switch-Blocks by Negotiating Switch Presence. 225-233 2021 FPL https://doi.org/10.1109/FPL53798.2021.00044 conf/fpl/2021 db/conf/fpl/fpl2021.html#NikolicI21 Mikhail Asiatici Paolo Ienne Large-Scale Graph Processing on FPGAs with Caches for Thousands of Simultaneous Misses. 609-622 2021 ISCA https://doi.org/10.1109/ISCA52012.2021.00054 https://www.wikidata.org/entity/Q130853847 conf/isca/2021 db/conf/isca/isca2021.html#AsiaticiI21

Jovan Blanusa Radu Stoica Paolo Ienne Kubilay Atasu Many-Core Clique Enumeration with Fast Set Intersections. 2676-2690 2020 13 Proc. VLDB Endow. 11 http://www.vldb.org/pvldb/vol13/p2676-blanusa.pdf db/journals/pvldb/pvldb13.html#BlanusaSIA20

Mikhail Asiatici Damian Maiorano Paolo Ienne FPGAs in the Datacenters: the Case of Parallel Hybrid Super Scalar String Sample Sort. 133-140 2020 ASAP https://doi.org/10.1109/ASAP49362.2020.00031 conf/asap/2020 db/conf/asap/asap2020.html#AsiaticiMI20 Lana Josipovic Andrea Guerrieri Paolo Ienne Invited Tutorial: Dynamatic: From C/C++ to Dynamically Scheduled Circuits. 1-10 2020 FPGA https://doi.org/10.1145/3373087.3375391 conf/fpga/2020 db/conf/fpga/fpga2020.html#JosipovicGI20 Stefan Nikolic 0001 Grace Zgheib Paolo Ienne Straight to the Point: Intra- and Intercluster LUT Connections to Mitigate the Delay of Programmable Routing. 150-160 2020 FPGA https://doi.org/10.1145/3373087.3375315 conf/fpga/2020 db/conf/fpga/fpga2020.html#NikolicZI20 Lana Josipovic Shabnam Sheikhha Andrea Guerrieri Paolo Ienne Jordi Cortadella Buffer Placement and Sizing for High-Performance Dataflow Circuits. 186-196 2020 FPGA https://doi.org/10.1145/3373087.3375314 conf/fpga/2020 db/conf/fpga/fpga2020.html#JosipovicSGIC20 Jianyi Cheng Lana Josipovic George A. Constantinides Paolo Ienne John Wickerson Combining Dynamic & Static Scheduling in High-level Synthesis. 288-298 2020 FPGA https://doi.org/10.1145/3373087.3375297 conf/fpga/2020 db/conf/fpga/fpga2020.html#ChengJCIW20 Stefan Nikolic 0001 Grace Zgheib Paolo Ienne Timing-Driven Placement for FPGA Architectures with Dedicated Routing Paths. 153-161 2020 FPL https://doi.org/10.1109/FPL50879.2020.00035 conf/fpl/2020 db/conf/fpl/fpl2020.html#NikolicZI20 Jovan Blanusa Radu Stoica Paolo Ienne Kubilay Atasu Parallelizing Maximal Clique Enumeration on Modern Manycore Processors. 211-214 2020 IPDPS Workshops https://doi.org/10.1109/IPDPSW50202.2020.00047 conf/ipps/2020w db/conf/ipps/ipdps2020w.html#BlanusaSIA20

Andrea Guerrieri Sahand Kashani-Akhavan Mikhail Asiatici Paolo Ienne Snap-On User-Space Manager for Dynamically Reconfigurable System-on-Chips. 103938-103947 2019 7 IEEE Access https://doi.org/10.1109/ACCESS.2019.2931475 db/journals/access/access7.html#GuerrieriKAI19

Lana Josipovic Andrea Guerrieri Paolo Ienne Speculative Dataflow Circuits. 162-171 2019 FPGA https://doi.org/10.1145/3289602.3293914 conf/fpga/2019 db/conf/fpga/fpga2019.html#JosipovicGI19 Anastasiia Kucherenko Stefan Nikolic 0001 Paolo Ienne On Feasibility of FPGAs Without Dedicated Programmable Interconnect Structure. 188 2019 FPGA https://doi.org/10.1145/3289602.3293974 https://www.wikidata.org/entity/Q130867374 conf/fpga/2019 db/conf/fpga/fpga2019.html#KucherenkoNI19 Mikhail Asiatici Paolo Ienne Stop Crying Over Your Cache Miss Rate: Handling Efficiently Thousands of Outstanding Misses in FPGAs. 310-319 2019 FPGA https://doi.org/10.1145/3289602.3293901 https://www.wikidata.org/entity/Q130897749 conf/fpga/2019 db/conf/fpga/fpga2019.html#AsiaticiI19 Stefan Nikolic 0001 Grace Zgheib Paolo Ienne Finding a Needle in the Haystack of Hardened Interconnect Patterns. 31-37 2019 FPL https://doi.org/10.1109/FPL.2019.00015 conf/fpl/2019 db/conf/fpl/fpl2019.html#NikolicZI19 Mikhail Asiatici Paolo Ienne DynaBurst: Dynamically Assemblying DRAM Bursts over a Multitude of Random Accesses. 254-262 2019 FPL https://doi.org/10.1109/FPL.2019.00049 conf/fpl/2019 db/conf/fpl/fpl2019.html#AsiaticiI19 Gabor Csordas Mikhail Asiatici Paolo Ienne In Search of Lost Bandwidth: Extensive Reordering of DRAM Accesses on FPGA. 188-196 2019 FPT https://doi.org/10.1109/ICFPT47387.2019.00030 conf/icfpt/2019 db/conf/icfpt/icfpt2019.html#CsordasAI19 Lana Josipovic Atri Bhattacharyya Andrea Guerrieri Paolo Ienne Shrink It or Shed It! Minimize the Use of LSQs in Dataflow Designs. 197-205 2019 FPT https://doi.org/10.1109/ICFPT47387.2019.00031 conf/icfpt/2019 db/conf/icfpt/icfpt2019.html#JosipovicBGI19 Andrea Guerrieri Sahand Kashani-Akhavan Pasquale Lombardi Bilel Belhadj Paolo Ienne A Dynamically Reconfigurable Platform for High-Performance and Low-Power On-Board Processing. 74-81 2018 AHS https://doi.org/10.1109/AHS.2018.8541452 conf/ahs/2018 db/conf/ahs/ahs2018.html#GuerrieriKLBI18 Lana Josipovic Radhika Ghosal Paolo Ienne Dynamically Scheduled High-level Synthesis. 127-136 2018 FPGA https://doi.org/10.1145/3174243.3174264 conf/fpga/2018 db/conf/fpga/fpga2018.html#JosipovicGI18 Mikhail Asiatici Damian Maiorano Paolo Ienne FPGAs in the Datacenters: the Case of Parallel Hybrid Super Scalar String Sample Sort (pHS<sup>5</sup>)(Abstract Only). 294 2018 FPGA https://doi.org/10.1145/3174243.3174993 https://www.wikidata.org/entity/Q130857147 conf/fpga/2018 db/conf/fpga/fpga2018.html#AsiaticiMI18 Andrea Guerrieri Sahand Kashani-Akhavan Mikhail Asiatici Pasquale Lombardi Bilel Belhadj Paolo Ienne LEOSoC: An Open-Source Cross-Platform Embedded Linux Library for Managing Hardware Accelerators in Heterogeneous System-on-Chips(Abstract Only). 295 2018 FPGA https://doi.org/10.1145/3174243.3175002 conf/fpga/2018 db/conf/fpga/fpga2018.html#GuerrieriKALBI18 João Vieira Nuno Roma Pedro Tomás Paolo Ienne Gabriel Falcão Paiva Fernandes Exploiting Compute Caches for Memory Bound Vector Operations. 197-200 2018 SBAC-PAD https://doi.org/10.1109/CAHPC.2018.8645905 conf/sbac-pad/2018 db/conf/sbac-pad/sbac-pad2018.html#VieiraRTIF18 Ana Petkovska Alan Mishchenko David Novo Muhsen Owaida Paolo Ienne Progressive Generation of Canonical Irredundant Sums of Products Using a SAT Solver. 169-188 2018 Advanced Logic Synthesis https://doi.org/10.1007/978-3-319-67295-3_8 books/sp/18/RD2018 db/books/collections/RD2018.html#PetkovskaMNOI18

Mikhail Asiatici Nithin George Kizheppatt Vipin Suhaib A. Fahmy Paolo Ienne Virtualized Execution Runtime for FPGA Accelerators in the Cloud. 1900-1910 2017 5 IEEE Access https://doi.org/10.1109/ACCESS.2017.2661582 db/journals/access/access5.html#AsiaticiGVFI17

João Andrade Nithin George Kimon Karras David Novo Frederico Pratas Leonel Sousa Paolo Ienne Gabriel Falcão 0001 Vítor Silva 0001 Design Space Exploration of LDPC Decoders Using High-Level Synthesis. 14600-14615 2017 5 IEEE Access https://doi.org/10.1109/ACCESS.2017.2727221 db/journals/access/access5.html#AndradeGKNPSIF017

Zidong Du Shaoli Liu Robert Fasthuber Tianshi Chen 0002 Paolo Ienne Ling Li 0001 Tao Luo Qi Guo 0001 Xiaobing Feng 0002 Yunji Chen Olivier Temam An Accelerator for High Efficient Vision Processing. 227-240 2017 36 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2 https://doi.org/10.1109/TCAD.2016.2584062 db/journals/tcad/tcad36.html#DuLFCILLGFCT17

Lana Josipovic Philip Brisk Paolo Ienne An Out-of-Order Load-Store Queue for Spatial Computing. 125:1-125:19 2017 16 ACM Trans. Embed. Comput. Syst. 5s https://doi.org/10.1145/3126525 db/journals/tecs/tecs16.html#JosipovicBI17

Lana Josipovic Philip Brisk Paolo Ienne From C to elastic circuits. 121-125 2017 ACSSC https://doi.org/10.1109/ACSSC.2017.8335150 conf/acssc/2017 db/conf/acssc/acssc2017.html#JosipovicBI17 Andrew Becker Wei Hu 0008 Yu Tai Philip Brisk Ryan Kastner Paolo Ienne Arbitrary Precision and Complexity Tradeoffs for Gate-Level Information Flow Tracking. 5:1-5:6 2017 DAC https://doi.org/10.1145/3061639.3062203 conf/dac/2017 db/conf/dac/dac2017.html#BeckerHTBKI17 Lana Josipovic Philip Brisk Paolo Ienne An Out-of-Order Load-Store Queue for Spatial Computing. 134 2017 FCCM https://doi.org/10.1109/FCCM.2017.26 https://doi.ieeecomputersociety.org/10.1109/FCCM.2017.26 conf/fccm/2017 db/conf/fccm/fccm2017.html#JosipovicBI17 Zhihong Huang Xing Wei Grace Zgheib Wei Li 0008 Yu Lin Zhenghong Jiang Kaihui Tu Paolo Ienne Haigang Yang NAND-NOR: A Compact, Fast, and Delay Balanced FPGA Logic Element. 135-140 2017 FPGA http://dl.acm.org/citation.cfm?id=3021750 conf/fpga/2017 db/conf/fpga/fpga2017.html#HuangWZLLJTIY17 Grace Zgheib Paolo Ienne Evaluating FPGA clusters under wide ranges of design parameters. 1-8 2017 FPL https://doi.org/10.23919/FPL.2017.8056826 conf/fpl/2017 db/conf/fpl/fpl2017.html#ZgheibI17 Zhufei Chu Xifan Tang Mathias Soeken Ana Petkovska Grace Zgheib Luca Gaetano Amarù Yinshui Xia Paolo Ienne Giovanni De Micheli Pierre-Emmanuel Gaillardon Improving Circuit Mapping Performance Through MIG-based Synthesis for Carry Chains. 131-136 2017 ACM Great Lakes Symposium on VLSI https://doi.org/10.1145/3060403.3060432 conf/glvlsi/2017 db/conf/glvlsi/glvlsi2017.html#ChuTSPZAXIMG17

Hossein Asadi 0001 Paolo Ienne Hamid Sarbazi-Azad Introduction: Special Section on Architecture of Future Many Core Systems. 219-220 2016 46 Microprocess. Microsystems https://doi.org/10.1016/j.micpro.2016.11.002 db/journals/mam/mam46.html#AsadiIS16

Hossein Asadi 0001 Paolo Ienne Hamid Sarbazi-Azad Guest Editors' Introduction: Special Section on Emerging Memory Technologies in Very Large Scale Computing and Storage Systems. 1006-1009 2016 65 IEEE Trans. Computers 4 https://doi.org/10.1109/TC.2016.2527138 http://doi.ieeecomputersociety.org/10.1109/TC.2016.2527138 db/journals/tc/tc65.html#AsadiIS16

Paolo Ienne Jean-Pierre Talpin Guest Editorial: Special Issue on Models and Methodologies for System Design. 29:1-29:2 2016 15 ACM Trans. Embed. Comput. Syst. 2 https://doi.org/10.1145/2885503 db/journals/tecs/tecs15.html#IenneT16

Sadegh Yazdanshenas Behnam Khaleghi Paolo Ienne Hossein Asadi 0001 Designing Low Power and Durable Digital Blocks Using Shadow Nanoelectromechanical Relays. 3489-3498 2016 24 IEEE Trans. Very Large Scale Integr. Syst. 12 https://doi.org/10.1109/TVLSI.2016.2553106 db/journals/tvlsi/tvlsi24.html#YazdanshenasKIA16

Francesco Regazzoni 0001 Paolo Ienne Instruction Set Extensions for secure applications. 1529-1534 2016 DATE https://ieeexplore.ieee.org/document/7459556/ conf/date/2016 db/conf/date/date2016.html#RegazzoniI16 Grace Zgheib Manana Lortkipanidze Muhsen Owaida David Novo Paolo Ienne FPRESSO: Enabling Express Transistor-Level Exploration of FPGA Architectures. 80-89 2016 FPGA https://doi.org/10.1145/2847263.2847280 https://www.wikidata.org/entity/Q130871170 conf/fpga/2016 db/conf/fpga/fpga2016.html#ZgheibLONI16 Mikhail Asiatici Nithin George Kizheppatt Vipin Suhaib A. Fahmy Paolo Ienne Designing a virtual runtime for FPGA accelerators in the cloud. 1-2 2016 FPL https://doi.org/10.1109/FPL.2016.7577389 conf/fpl/2016 db/conf/fpl/fpl2016.html#AsiaticiGVFI16 Paolo Ienne Walid A. Najjar Jason Helge Anderson Philip Brisk Walter Stechele Preface. 1 2016 FPL https://doi.org/10.1109/FPL.2016.7577297 conf/fpl/2016 db/conf/fpl/fpl2016.html#IenneNABS16 Ana Petkovska Mathias Soeken Giovanni De Micheli Paolo Ienne Alan Mishchenko Fast hierarchical NPN classification. 1-4 2016 FPL https://doi.org/10.1109/FPL.2016.7577306 conf/fpl/2016 db/conf/fpl/fpl2016.html#PetkovskaSMIM16 Lana Josipovic Nithin George Paolo Ienne Enriching C-based High-Level Synthesis with parallel pattern templates. 177-180 2016 FPT https://doi.org/10.1109/FPT.2016.7929527 conf/fpt/2016 db/conf/fpt/fpt2016.html#JosipovicGI16 Grace Zgheib Paolo Ienne Automatic wire modeling to explore novel FPGA architectures. 181-184 2016 FPT https://doi.org/10.1109/FPT.2016.7929528 conf/fpt/2016 db/conf/fpt/fpt2016.html#ZgheibI16 Ana Petkovska Alan Mishchenko Mathias Soeken Giovanni De Micheli Robert K. Brayton Paolo Ienne Fast generation of lexicographic satisfiable assignments: enabling canonicity in SAT-based applications. 4 2016 ICCAD https://doi.org/10.1145/2966986.2967040 conf/iccad/2016 db/conf/iccad/iccad2016.html#PetkovskaMSMBI16 Wei Hu 0008 Andrew Becker Armita Ardeshiricham Yu Tai Paolo Ienne Dejun Mu Ryan Kastner Imprecise security: quality and complexity tradeoffs for hardware information flow tracking. 95 2016 ICCAD https://doi.org/10.1145/2966986.2967046 conf/iccad/2016 db/conf/iccad/iccad2016.html#HuBATIMK16 Mathias Soeken Alan Mishchenko Ana Petkovska Baruch Sterin Paolo Ienne Robert K. Brayton Giovanni De Micheli Heuristic NPN Classification for Large Functions Using AIGs and LEXSAT. 212-227 2016 SAT https://doi.org/10.1007/978-3-319-40970-2_14 conf/sat/2016 db/conf/sat/sat2016.html#SoekenMPSIBM16 Paolo Ienne Walid A. Najjar Jason Helge Anderson Philip Brisk Walter Stechele 26th International Conference on Field Programmable Logic and Applications, FPL 2016, Lausanne, Switzerland, August 29 - September 2, 2016 FPL IEEE 2016 978-2-8399-1844-2 https://ieeexplore.ieee.org/xpl/conhome/7573873/proceeding db/conf/fpl/fpl2016.html

Ali Galip Bayrak Francesco Regazzoni 0001 David Novo Philip Brisk François-Xavier Standaert Paolo Ienne Automatic Application of Power Analysis Countermeasures. 329-341 2015 64 IEEE Trans. Computers 2 https://doi.org/10.1109/TC.2013.219 http://doi.ieeecomputersociety.org/10.1109/TC.2013.219 db/journals/tc/tc64.html#BayrakRNBSI15

Xavier Jimenez David Novo Paolo Ienne Libra: Software-Controlled Cell Bit-Density to Balance Wear in NAND Flash. 28:1-28:22 2015 14 ACM Trans. Embed. Comput. Syst. 2 https://doi.org/10.1145/2638552 db/journals/tecs/tecs14.html#JimenezNI15

Muhsen Owaida Gabriel Falcão 0001 João Andrade Christos D. Antonopoulos Nikolaos Bellas Madhura Purnaprajna David Novo Georgios Karakonstantis Andreas Burg 0001 Paolo Ienne Enhancing Design Space Exploration by Extending CPU/GPU Specifications onto FPGAs. 33:1-33:23 2015 14 ACM Trans. Embed. Comput. Syst. 2 https://doi.org/10.1145/2656207 db/journals/tecs/tecs14.html#OwaidaFAABPNKBI15

Jiachao Deng Yuntan Fang Zidong Du Ying Wang 0001 Huawei Li 0001 Olivier Temam Paolo Ienne David Novo Xiaowei Li 0001 Yunji Chen Chengyong Wu Retraining-based timing error mitigation for hardware neural networks. 593-596 2015 DATE http://dl.acm.org/citation.cfm?id=2755887 https://ieeexplore.ieee.org/document/7092456/ conf/date/2015 db/conf/date/date2015.html#DengFDWLTINLCW15 João Andrade Nithin George Kimon Karras David Novo Vítor Manuel Mendes da Silva Paolo Ienne Gabriel Falcão Paiva Fernandes Fast Design Space Exploration Using Vivado HLS: Non-binary LDPC Decoders. 97 2015 FCCM https://doi.org/10.1109/FCCM.2015.63 https://doi.ieeecomputersociety.org/10.1109/FCCM.2015.63 conf/fccm/2015 db/conf/fccm/fccm2015.html#AndradeGKNSIF15 João Andrade Nithin George Kimon Karras David Novo Vítor Manuel Mendes da Silva Paolo Ienne Gabriel Falcão Paiva Fernandes From low-architectural expertise up to high-throughput non-binary LDPC decoders: Optimization guidelines using high-level synthesis. 1-8 2015 FPL https://doi.org/10.1109/FPL.2015.7293940 conf/fpl/2015 db/conf/fpl/fpl2015.html#AndradeGKNSIF15 Nithin George HyoukJoong Lee David Novo Muhsen Owaida David Andrews 0001 Kunle Olukotun Paolo Ienne Automatic support for multi-module parallelism from computational patterns. 1-8 2015 FPL https://doi.org/10.1109/FPL.2015.7294011 conf/fpl/2015 db/conf/fpl/fpl2015.html#GeorgeLNOAOI15 Zhenghong Jiang Grace Zgheib Colin Yu Lin David Novo Zhihong Huang Liqun Yang Haigang Yang Paolo Ienne A technology mapper for depth-constrained FPGA logic cells. 1-8 2015 FPL https://doi.org/10.1109/FPL.2015.7294014 conf/fpl/2015 db/conf/fpl/fpl2015.html#JiangZLNHYYI15 Ana Petkovska Grace Zgheib David Novo Muhsen Owaida Alan Mishchenko Paolo Ienne Improved carry chain mapping for the VTR flow. 80-87 2015 FPT https://doi.org/10.1109/FPT.2015.7393133 conf/fpt/2015 db/conf/fpt/fpt2015.html#PetkovskaZNOMI15 Andrew Becker Djordje Maksimovic David Novo Mohsen Ewaida Andreas G. Veneris Barbara Jobstmann Paolo Ienne FudgeFactor: Syntax-Guided Synthesis for Accurate RTL Error Localization and Correction. 259-275 2015 Haifa Verification Conference https://doi.org/10.1007/978-3-319-26287-1_16 conf/hvc/2015 db/conf/hvc/hvc2015.html#BeckerMNEVJI15 Zidong Du Robert Fasthuber Tianshi Chen 0002 Paolo Ienne Ling Li 0001 Tao Luo Xiaobing Feng 0002 Yunji Chen Olivier Temam ShiDianNao: shifting vision processing closer to the sensor. 92-104 2015 ISCA https://doi.org/10.1145/2749469.2750389 conf/isca/2015 db/conf/isca/isca2015.html#DuFCILLFCT15 Panagiotis Skrimponis Georgios Zindros Ioannis Parnassos Muhsen Owaida Nikolaos Bellas Paolo Ienne Exploring Automatically Generated Platforms in High Performance FPGAs. 563-570 2015 PARCO https://doi.org/10.3233/978-1-61499-621-7-563 conf/parco/2015 db/conf/parco/parco2015.html#SkrimponisZPOBI15 Yunji Chen Paolo Ienne Qing Ji Advanced Parallel Processing Technologies - 11th International Symposium, APPT 2015, Jinan, China, August 20-21, 2015, Proceedings APPT Springer 2015 Lecture Notes in Computer Science 9231 978-3-319-23215-7 https://doi.org/10.1007/978-3-319-23216-4 db/conf/appt/appt2015.html

Walid A. Najjar Paolo Ienne Reconfigurable Computing. 4-6 2014 34 IEEE Micro 1 https://doi.org/10.1109/MM.2014.25 http://doi.ieeecomputersociety.org/10.1109/MM.2014.25 db/journals/micro/micro34.html#NajjarI14

Theo Kluter Samuel Burri Philip Brisk Edoardo Charbon Paolo Ienne Virtual Ways: Low-Cost Coherence for Instruction Set Extensions with Architecturally Visible Storage. 15:1-15:26 2014 11 ACM Trans. Archit. Code Optim. 2 https://doi.org/10.1145/2576877 db/journals/taco/taco11.html#KluterBBCI14

Theo Kluter Philip Brisk Edoardo Charbon Paolo Ienne Way Stealing: A Unified Data Cache and Architecturally Visible Storage for Instruction Set Extensions. 62-75 2014 22 IEEE Trans. Very Large Scale Integr. Syst. 1 https://doi.org/10.1109/TVLSI.2012.2236689 db/journals/tvlsi/tvlsi22.html#KluterBCI14

Jing Huang Yuanjie Huang Olivier Temam Paolo Ienne Yunji Chen Chengyong Wu A low-cost memory interface for high-throughput accelerators. 11:1-11:10 2014 CASES https://doi.org/10.1145/2656106.2656109 conf/cases/2014 db/conf/cases/cases2014.html#HuangHTICW14 Andrew Becker David Novo Paolo Ienne SKETCHILOG: Sketching combinational circuits. 1-4 2014 DATE https://doi.org/10.7873/DATE.2014.165 http://dl.acm.org/citation.cfm?id=2616793 conf/date/2014 db/conf/date/date2014.html#BeckerNI14 David Novo Nazanin Farahpour Paolo Ienne Ubaid Ahmad Francky Catthoor Energy efficient MIMO processing: A case study of opportunistic run-time approximations. 1-6 2014 DATE https://doi.org/10.7873/DATE.2014.220 http://dl.acm.org/citation.cfm?id=2616861 conf/date/2014 db/conf/date/date2014.html#NovoFIAC14 Xavier Jimenez David Novo Paolo Ienne Wear unleveling: improving NAND flash lifetime by balancing page endurance. 47-59 2014 FAST https://www.usenix.org/conference/fast14/technical-sessions/presentation/jimenez conf/fast/2014 db/conf/fast/fast2014.html#JimenezNI14 Grace Zgheib Liqun Yang Zhihong Huang David Novo Hadi Parandeh-Afshar Haigang Yang Paolo Ienne Revisiting and-inverter cones. 45-54 2014 FPGA https://doi.org/10.1145/2554688.2554791 conf/fpga/2014 db/conf/fpga/fpga2014.html#ZgheibYHNPYI14 Nithin George HyoukJoong Lee David Novo Tiark Rompf Kevin J. Brown Arvind K. Sujeeth Martin Odersky Kunle Olukotun Paolo Ienne Hardware system synthesis from Domain-Specific Languages. 1-8 2014 FPL https://doi.org/10.1109/FPL.2014.6927454 conf/fpl/2014 db/conf/fpl/fpl2014.html#GeorgeLNRBSOOI14 Ana Petkovska David Novo Alan Mishchenko Paolo Ienne Constrained interpolation for guided logic synthesis. 462-469 2014 ICCAD https://doi.org/10.1109/ICCAD.2014.7001392 http://dl.acm.org/citation.cfm?id=2691459 conf/iccad/2014 db/conf/iccad/iccad2014.html#PetkovskaNMI14

Mirjana Stojilovic David Novo Lazar Saranovac Philip Brisk Paolo Ienne Selective Flexibility: Creating Domain-Specific Reconfigurable Arrays. 681-694 2013 32 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 5 https://doi.org/10.1109/TCAD.2012.2235127 https://www.wikidata.org/entity/Q59387499 db/journals/tcad/tcad32.html#StojilovicNSBI13

Andrew Becker David Novo Paolo Ienne Automated circuit elaboration from incomplete architectural descriptions. 391-395 2013 ACSSC https://doi.org/10.1109/ACSSC.2013.6810303 conf/acssc/2013 db/conf/acssc/acssc2013.html#BeckerNI13 Ali Galip Bayrak Francesco Regazzoni 0001 David Novo Paolo Ienne Sleuth: Automated Verification of Software Power Analysis Countermeasures. 293-310 2013 conf/ches/2013 CHES https://doi.org/10.1007/978-3-642-40349-1_17 db/conf/ches/ches2013.html#BayrakRNI13 David Novo Sara El Alaoui Paolo Ienne Accuracy vs speed tradeoffs in the estimation of fixed-point errors on linear time-invariant systems. 15-20 2013 DATE https://doi.org/10.7873/DATE.2013.018 http://dl.acm.org/citation.cfm?id=2485295 conf/date/2013 db/conf/date/date2013.html#NovoAI13 Xavier Jimenez David Novo Paolo Ienne Phœnix: reviving MLC blocks as SLC to extend NAND flash devices lifetime. 226-229 2013 DATE https://doi.org/10.7873/DATE.2013.059 http://dl.acm.org/citation.cfm?id=2485345 conf/date/2013 db/conf/date/date2013.html#JimenezNI13 Ali Galip Bayrak Nikola Velickovic Francesco Regazzoni 0001 David Novo Philip Brisk Paolo Ienne An EDA-friendly protection scheme against side-channel attacks. 410-415 2013 DATE https://doi.org/10.7873/DATE.2013.093 http://dl.acm.org/citation.cfm?id=2485387 conf/date/2013 db/conf/date/date2013.html#BayrakVRNBI13 Alessandro Cevrero Nestor E. Evmorfopoulos Charalampos Antoniadis Paolo Ienne Yusuf Leblebici Andreas Burg 0001 Georgios I. Stamoulis Fast and accurate BER estimation methodology for I/O links based on extreme value theory. 503-508 2013 DATE https://doi.org/10.7873/DATE.2013.114 http://dl.acm.org/citation.cfm?id=2485413 conf/date/2013 db/conf/date/date2013.html#CevreroEAILBS13 Madhura Purnaprajna Paolo Ienne A Case for Heterogeneous Technology-Mapping: Soft Versus Hard Multiplexers. 53-56 2013 FCCM https://doi.org/10.1109/FCCM.2013.19 https://doi.ieeecomputersociety.org/10.1109/FCCM.2013.19 conf/fccm/2013 db/conf/fccm/fccm2013.html#PurnaprajnaI13 Yuanjie Huang Paolo Ienne Olivier Temam Yunji Chen Chengyong Wu Elastic CGRAs. 171-180 2013 FPGA https://doi.org/10.1145/2435264.2435296 conf/fpga/2013 db/conf/fpga/fpga2013.html#HuangITCW13 Hadi Parandeh-Afshar Grace Zgheib David Novo Madhura Purnaprajna Paolo Ienne Shadow AICs: reaping the benefits of and-inverter cones with minimal architectural impact (abstract only). 279 2013 FPGA https://doi.org/10.1145/2435264.2435348 conf/fpga/2013 db/conf/fpga/fpga2013.html#Parandeh-AfsharZNPI13 Hadi Parandeh-Afshar Grace Zgheib David Novo Madhura Purnaprajna Paolo Ienne Shadow And-Inverter Cones. 1-4 2013 FPL https://doi.org/10.1109/FPL.2013.6645566 conf/fpl/2013 db/conf/fpl/fpl2013.html#Parandeh-AfsharZNPI13 Nithin George David Novo Tiark Rompf Martin Odersky Paolo Ienne Making domain-specific hardware synthesis tools cost-efficient. 120-127 2013 FPT https://doi.org/10.1109/FPT.2013.6718341 conf/fpt/2013 db/conf/fpt/fpt2013.html#GeorgeNROI13 Lunkai Zhang Mingzhe Zhang Lingjun Fan Da Wang Paolo Ienne Spontaneous Reload Cache: Mimicking a Larger Cache with Minimal Hardware Requirement. 31-40 2013 NAS https://doi.org/10.1109/NAS.2013.11 https://doi.ieeecomputersociety.org/10.1109/NAS.2013.11 conf/nas/2013 db/conf/nas/nas2013.html#ZhangZFWI13 David Novo I. Tzimi Ubaid Ahmad Paolo Ienne Francky Catthoor Cracking the complexity of fixed-point refinement in complex wireless systems. 18-23 2013 SiPS https://doi.org/10.1109/SiPS.2013.6674474 conf/sips/2013 db/conf/sips/sips2013.html#NovoTAIC13

Ali Galip Bayrak Nikola Velickovic Paolo Ienne Wayne P. Burleson An architecture-independent instruction shuffler to protect against side-channel attacks. 20:1-20:19 2012 8 ACM Trans. Archit. Code Optim. 4 https://doi.org/10.1145/2086696.2086699 db/journals/taco/taco8.html#BayrakVIB12

Madhura Purnaprajna Paolo Ienne Making wide-issue VLIW processors viable on FPGAs. 33:1-33:16 2012 8 ACM Trans. Archit. Code Optim. 4 https://doi.org/10.1145/2086696.2086712 db/journals/taco/taco8.html#PurnaprajnaI12

Elisardo Antelo David Hough 0001 Paolo Ienne Guest Editors' Introduction: Special Section on Computer Arithmetic. 1057-1058 2012 61 IEEE Trans. Computers 8 https://doi.org/10.1109/TC.2012.153 http://doi.ieeecomputersociety.org/10.1109/TC.2012.153 db/journals/tc/tc61.html#AnteloHI12

Xavier Jimenez David Novo Paolo Ienne Software controlled cell bit-density to improve NAND flash lifetime. 229-234 2012 DAC https://doi.org/10.1145/2228360.2228404 conf/dac/2012 db/conf/dac/dac2012.html#JimenezNI12 Mirjana Stojilovic David Novo Lazar Saranovac Philip Brisk Paolo Ienne Selective flexibility: Breaking the rigidity of datapath merging. 1543-1548 2012 DATE https://doi.org/10.1109/DATE.2012.6176718 https://doi.ieeecomputersociety.org/10.1109/DATE.2012.6176718 http://dl.acm.org/citation.cfm?id=2493086 conf/date/2012 db/conf/date/date2012.html#StojilovicNSBI12 Shuai Jiao Paolo Ienne Xiaochun Ye Da Wang Dongrui Fan Ninghui Sun CRAW/P: A Workload Partition Method for the Efficient Parallel Simulation of Manycores. 102-114 2012 Euro-Par https://doi.org/10.1007/978-3-642-32820-6_12 conf/europar/2012 db/conf/europar/europar2012.html#JiaoIYWFS12 Gabriel Falcão 0001 Muhsen Owaida David Novo Madhura Purnaprajna Nikolaos Bellas Christos D. Antonopoulos Georgios Karakonstantis Andreas Burg 0001 Paolo Ienne Shortening Design Time through Multiplatform Simulations with a Portable OpenCL Golden-model: The LDPC Decoder Case. 224-231 2012 FCCM https://doi.org/10.1109/FCCM.2012.46 https://doi.ieeecomputersociety.org/10.1109/FCCM.2012.46 conf/fccm/2012 db/conf/fccm/fccm2012.html#FalcaoONPBAKBI12 Hadi Parandeh-Afshar Hind Benbihi David Novo Paolo Ienne Rethinking FPGAs: elude the flexibility excess of LUTs with and-inverter cones. 119-128 2012 FPGA https://doi.org/10.1145/2145694.2145715 conf/fpga/2012 db/conf/fpga/fpga2012.html#Parandeh-AfsharBNI12 Yehdhih Ould Mohammed Moctar Nithin George Hadi Parandeh-Afshar Paolo Ienne Guy G. F. Lemieux Philip Brisk Reducing the cost of floating-point mantissa alignment and normalization in FPGAs. 255-264 2012 FPGA https://doi.org/10.1145/2145694.2145738 conf/fpga/2012 db/conf/fpga/fpga2012.html#MoctarGPILB12 Aanjhan Ranganathan Ali Galip Bayrak Theo Kluter Philip Brisk Edoardo Charbon Paolo Ienne Counting stream registers: An efficient and effective snoop filter architecture. 120-127 2012 ICSAMOS https://doi.org/10.1109/SAMOS.2012.6404165 conf/samos/2012ic db/conf/samos/samos2012ic.html#RanganathanBKBCI12 Francesco Regazzoni 0001 Luca Breveglieri Paolo Ienne Israel Koren Interaction Between Fault Attack Countermeasures and the Resistance Against Power Analysis Attacks. 257-272 2012 Fault Analysis in Cryptography https://doi.org/10.1007/978-3-642-29656-7_15 series/isc/364229655 db/series/isc/isc364229655.html#RegazzoniBIK12

Hadi Parandeh-Afshar Arkosnato Neogy Philip Brisk Paolo Ienne Compressor tree synthesis on commercial high-performance FPGAs. 39:1-39:19 2011 4 ACM Trans. Reconfigurable Technol. Syst. 4 https://doi.org/10.1145/2068716.2068725 db/journals/trets/trets4.html#Parandeh-AfsharNBI11

Ali Galip Bayrak Francesco Regazzoni 0001 Philip Brisk François-Xavier Standaert Paolo Ienne A first step towards automatic application of power analysis countermeasures. 230-235 2011 DAC https://doi.org/10.1145/2024724.2024778 https://www.wikidata.org/entity/Q58765104 conf/dac/2011 db/conf/dac/dac2011.html#BayrakRBSI11 Alessandro Cevrero Francesco Regazzoni 0001 Micheal Schwander Stéphane Badel Paolo Ienne Yusuf Leblebici Power-gated MOS current mode logic (PG-MCML): a power aware DPA-resistant standard cell library. 1014-1019 2011 DAC https://doi.org/10.1145/2024724.2024947 conf/dac/2011 db/conf/dac/dac2011.html#CevreroRSBIL11 Hadi Parandeh-Afshar Grace Zgheib Philip Brisk Paolo Ienne Reducing the pressure on routing resources of FPGAs with generic logic chains. 237-246 2011 FPGA https://doi.org/10.1145/1950413.1950458 https://www.wikidata.org/entity/Q130884311 conf/fpga/2011 db/conf/fpga/fpga2011.html#Parandeh-AfsharZBI11 Hadi Parandeh-Afshar Paolo Ienne Measuring and Reducing the Performance Gap between Embedded and Soft Multipliers on FPGAs. 225-231 2011 FPL https://doi.org/10.1109/FPL.2011.48 https://doi.ieeecomputersociety.org/10.1109/FPL.2011.48 conf/fpl/2011 db/conf/fpl/fpl2011.html#Parandeh-AfsharI11 Elisardo Antelo David Hough 0001 Paolo Ienne 20th IEEE Symposium on Computer Arithmetic, ARITH 2011, Tübingen, Germany, 25-27 July 2011 978-0-7695-4318-5 IEEE Symposium on Computer Arithmetic IEEE Computer Society 2011 https://ieeexplore.ieee.org/xpl/conhome/5991607/proceeding http://www.computer.org/csdl/proceedings/arith/2011/4318/00/index.html db/conf/arith/arith2010.html Joseph R. Cavallaro Milos D. Ercegovac Frank Hannig Paolo Ienne Earl E. Swartzlander Jr. Alexandre F. Tenca 22nd IEEE International Conference on Application-specific Systems, Architectures and Processors, ASAP 2011, Santa Monica, CA, USA, Sept. 11-14, 2011 IEEE Computer Society 2011 978-1-4577-1291-3 https://ieeexplore.ieee.org/xpl/conhome/6033675/proceeding http://www.computer.org/csdl/proceedings/asap/2011/1291/00/index.html ASAP db/conf/asap/asap2011.html

Ajay Kumar Verma Philip Brisk Paolo Ienne Fast, Nearly Optimal ISE Identification With I/O Serialization Through Maximal Clique Enumeration. 341-354 2010 29 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 3 https://doi.org/10.1109/TCAD.2010.2041849 db/journals/tcad/tcad29.html#VermaBI10

Philip Brisk Ajay Kumar Verma Paolo Ienne An Optimal Linear-Time Algorithm for Interprocedural Register Allocation in High Level Synthesis Using SSA Form. 1096-1109 2010 29 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7 https://doi.org/10.1109/TCAD.2010.2049060 db/journals/tcad/tcad29.html#BriskVI10

Hadi Parandeh-Afshar Ajay Kumar Verma Philip Brisk Paolo Ienne Improving FPGA Performance for Carry-Save Arithmetic. 578-590 2010 18 IEEE Trans. Very Large Scale Integr. Syst. 4 https://doi.org/10.1109/TVLSI.2009.2014380 db/journals/tvlsi/tvlsi18.html#Parandeh-AfsharVBI10

Nagaraju Pothineni Philip Brisk Paolo Ienne Anshul Kumar Kolin Paul A high-level synthesis flow for custom instruction set extensions for application-specific processors. 707-712 2010 ASP-DAC https://doi.org/10.1109/ASPDAC.2010.5419795 http://dl.acm.org/citation.cfm?id=1899885 conf/aspdac/2010 db/conf/aspdac/aspdac2010.html#PothineniBIKP10 Hadi Parandeh-Afshar Paolo Ienne Highly Versatile DSP Blocks for Improved FPGA Arithmetic Performance. 229-236 2010 FCCM https://doi.org/10.1109/FCCM.2010.42 https://doi.ieeecomputersociety.org/10.1109/FCCM.2010.42 conf/fccm/2010 db/conf/fccm/fccm2010.html#Parandeh-AfsharI10 Amit Verma 0002 Ajay Kumar Verma Hadi Parandeh-Afshar Philip Brisk Paolo Ienne Synthesis of Floating-Point Addition Clusters on FPGAs Using Carry-Save Arithmetic. 19-24 2010 FPL https://doi.org/10.1109/FPL.2010.15 https://doi.ieeecomputersociety.org/10.1109/FPL.2010.15 conf/fpl/2010 db/conf/fpl/fpl2010.html#VermaVPBI10 Theo Kluter Samuel Burri Philip Brisk Edoardo Charbon Paolo Ienne Virtual Ways: Efficient Coherence for Architecturally Visible Storage in Automatic Instruction Set Extensions. 126-140 2010 HiPEAC https://doi.org/10.1007/978-3-642-11515-8_11 conf/hipeac/2010 db/conf/hipeac/hipeac2010.html#KluterBBCI10 Xiaochun Ye Dongrui Fan Wei Lin 0004 Nan Yuan Paolo Ienne High performance comparison-based sorting algorithm on many-core GPUs. 1-10 2010 IPDPS https://doi.org/10.1109/IPDPS.2010.5470445 https://doi.ieeecomputersociety.org/10.1109/IPDPS.2010.5470445 conf/ipps/2010 db/conf/ipps/ipdps2010.html#YeFLYI10

Philip Brisk Ajay Kumar Verma Paolo Ienne Optimistic chordal coloring: a coalescing heuristic for SSA form programs. 115-137 2009 13 Des. Autom. Embed. Syst. 1-2 https://doi.org/10.1007/s10617-008-9034-y db/journals/dafes/dafes13.html#BriskVI09

Francesco Regazzoni 0001 Thomas Eisenbarth 0001 Axel Poschmann Johann Großschädl Frank K. Gürkaynak Marco Macchetti Zeynep Toprak Deniz Laura Pozzi 0001 Christof Paar Yusuf Leblebici Paolo Ienne Evaluating Resistance of MCML Technology to Power Analysis Attacks Using a Simulation-Based Methodology. 230-243 2009 4 Trans. Comput. Sci. https://doi.org/10.1007/978-3-642-01004-0_13 journals/tcos/2009-4 db/journals/tcos/tcos4.html#RegazzoniEPGGMDPPLI09

Alessandro Cevrero Panagiotis Athanasopoulos Hadi Parandeh-Afshar Ajay Kumar Verma Seyed-Hosein Attarzadeh-Niaki Chrysostomos Nicopoulos Frank K. Gürkaynak Philip Brisk Yusuf Leblebici Paolo Ienne Field Programmable Compressor Trees: Acceleration of Multi-Input Addition on FPGAs. 2009 2 ACM Trans. Reconfigurable Technol. Syst. 2 https://doi.org/10.1145/1534916.1534923 db/journals/trets/trets2.html#CevreroAPVNNGBLI09 13:1-13:36

Hadi Parandeh-Afshar Philip Brisk Paolo Ienne An FPGA Logic Cell and Carry Chain Configurable as a 6: 2 or 7: 2 Compressor. 2009 2 ACM Trans. Reconfigurable Technol. Syst. 3 https://doi.org/10.1145/1575774.1575778 https://www.wikidata.org/entity/Q130895706 db/journals/trets/trets2.html#Parandeh-AfsharBI09 19:1-19:42

Ajay Kumar Verma Philip Brisk Paolo Ienne Challenges in Automatic Optimization of Arithmetic Circuits. 213-218 2009 IEEE Symposium on Computer Arithmetic https://doi.org/10.1109/ARITH.2009.39 https://doi.ieeecomputersociety.org/10.1109/ARITH.2009.39 conf/arith/2009 db/conf/arith/arith2009.html#VermaBI09 Amit Verma 0002 Ajay Kumar Verma Philip Brisk Paolo Ienne Hybrid LZA: a near optimal implementation of the leading zero anticipator. 203-209 2009 ASP-DAC https://doi.org/10.1109/ASPDAC.2009.4796481 http://dl.acm.org/citation.cfm?id=1509693 conf/aspdac/2009 db/conf/aspdac/aspdac2009.html#VermaVBI09 Francesco Regazzoni 0001 Alessandro Cevrero François-Xavier Standaert Stéphane Badel Theo Kluter Philip Brisk Yusuf Leblebici Paolo Ienne A Design Flow and Evaluation Framework for DPA-Resistant Instruction Set Extensions. 205-219 2009 CHES https://doi.org/10.1007/978-3-642-04138-9_15 https://www.wikidata.org/entity/Q58765214 conf/ches/2009 db/conf/ches/ches2009.html#RegazzoniCSBKBLI09 Theo Kluter Philip Brisk Paolo Ienne Edoardo Charbon Way Stealing: cache-assisted automatic instruction set extensions. 31-36 2009 DAC https://doi.org/10.1145/1629911.1629923 conf/dac/2009 db/conf/dac/dac2009.html#KluterBIC09 Claudio Favi René Beuchat Xavier Jimenez Paolo Ienne From gates to multi-processors learning systems hands-on with FPGA4U in a computer science programme. 56-63 2009 WESE@ESWEEK https://doi.org/10.1145/1719010.1719020 conf/esweek/2009wese db/conf/esweek/wese2009.html#FaviBJI09 Arun Paidimarri Alessandro Cevrero Philip Brisk Paolo Ienne FPGA Implementation of a Single-Precision Floating-Point Multiply-Accumulator with Single-Cycle Accumulation. 267-270 2009 FCCM https://doi.org/10.1109/FCCM.2009.50 https://doi.ieeecomputersociety.org/10.1109/FCCM.2009.50 conf/fccm/2009 db/conf/fccm/fccm2009.html#PaidimarriCBI09 Alessandro Cevrero Panagiotis Athanasopoulos Hadi Parandeh-Afshar Philip Brisk Yusuf Leblebici Paolo Ienne Maurizio Skerlj 3D configuration caching for 2D FPGAs. 286 2009 FPGA https://doi.org/10.1145/1508128.1508205 conf/fpga/2009 db/conf/fpga/fpga2009.html#CevreroAPBLIS09 Hadi Parandeh-Afshar Philip Brisk Paolo Ienne Exploiting fast carry-chains of FPGAs for designing compressor trees. 242-249 2009 FPL https://doi.org/10.1109/FPL.2009.5272301 conf/fpl/2009 db/conf/fpl/fpl2009.html#Parandeh-AfsharBI09 Alessandro Cevrero Panagiotis Athanasopoulos Hadi Parandeh-Afshar Maurizio Skerlj Philip Brisk Yusuf Leblebici Paolo Ienne Using 3D integration technology to realize multi-context FPGAs. 507-510 2009 FPL https://doi.org/10.1109/FPL.2009.5272454 conf/fpl/2009 db/conf/fpl/fpl2009.html#CevreroAPSBLI09 Hadi Parandeh-Afshar Alessandro Cevrero Panagiotis Athanasopoulos Philip Brisk Yusuf Leblebici Paolo Ienne A flexible DSP block to enhance FPGA arithmetic performance. 70-77 2009 FPT https://doi.org/10.1109/FPT.2009.5377638 conf/fpt/2009 db/conf/fpt/fpt2009.html#Parandeh-AfsharCABLI09 Theo Kluter Philip Brisk Edoardo Charbon Paolo Ienne MPSoC Design Using Application-Specific Architecturally Visible Communication. 183-197 2009 HiPEAC https://doi.org/10.1007/978-3-540-92990-1_15 conf/hipeac/2009 db/conf/hipeac/hipeac2009.html#KluterBCI09 Panagiotis Athanasopoulos Philip Brisk Yusuf Leblebici Paolo Ienne Memory organization and data layout for instruction set extensions with architecturally visible storage. 689-696 2009 ICCAD https://doi.org/10.1145/1687399.1687527 https://ieeexplore.ieee.org/document/5361222/ conf/iccad/2009 db/conf/iccad/iccad2009.html#AthanasopoulosBLI09 Ajay Kumar Verma Philip Brisk Paolo Ienne Iterative layering: Optimizing arithmetic circuits by structuring the information flow. 797-804 2009 ICCAD https://doi.org/10.1145/1687399.1687547 https://ieeexplore.ieee.org/document/5361206/ conf/iccad/2009 db/conf/iccad/iccad2009.html#VermaBI09 Ajay Kumar Verma Yi Zhu Philip Brisk Paolo Ienne Arithmetic optimization for custom instruction set synthesis. 54-57 2009 SASP https://doi.org/10.1109/SASP.2009.5226336 https://doi.ieeecomputersociety.org/10.1109/SASP.2009.5226336 conf/sasp/2009 db/conf/sasp/sasp2009.html#VermaZBI09 Marcela Zuluaga Theo Kluter Philip Brisk Nigel P. Topham Paolo Ienne Introducing control-flow inclusion to support pipelining in custom instruction set extensions. 114-121 2009 SASP https://doi.org/10.1109/SASP.2009.5226328 https://doi.ieeecomputersociety.org/10.1109/SASP.2009.5226328 conf/sasp/2009 db/conf/sasp/sasp2009.html#ZuluagaKBTI09 Jani Boutellier Alessandro Cevrero Philip Brisk Paolo Ienne Architectural support for the orchestration of fine-grained multiprocessing for portable streaming applications. 115-120 2009 SiPS https://doi.org/10.1109/SIPS.2009.5336235 conf/sips/2009 db/conf/sips/sips2009.html#BoutellierCBI09

Ajay Kumar Verma Philip Brisk Paolo Ienne Data-Flow Transformations to Maximize the Use of Carry-Save Representation in Arithmetic Circuits. 1761-1774 2008 27 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10 https://doi.org/10.1109/TCAD.2008.2003280 db/journals/tcad/tcad27.html#VermaBI08

Paolo Ienne Peter Petrov Guest Editorial Special Section on Application Specific Processors. 1257-1258 2008 16 IEEE Trans. Very Large Scale Integr. Syst. 10 https://doi.org/10.1109/TVLSI.2008.2005245 db/journals/tvlsi/tvlsi16.html#IenneP08

Hadi Parandeh-Afshar Philip Brisk Paolo Ienne Efficient synthesis of compressor trees on FPGAs. 138-143 2008 ASP-DAC https://doi.org/10.1109/ASPDAC.2008.4483927 http://dl.acm.org/citation.cfm?id=1356841 conf/aspdac/2008 db/conf/aspdac/aspdac2008.html#Parandeh-AfsharBI08 Ajay Kumar Verma Philip Brisk Paolo Ienne Fast, quasi-optimal, and pipelined instruction-set extensions. 334-339 2008 ASP-DAC https://doi.org/10.1109/ASPDAC.2008.4483970 http://dl.acm.org/citation.cfm?id=1356887 conf/aspdac/2008 db/conf/aspdac/aspdac2008.html#VermaBI08 Seyed-Hosein Attarzadeh-Niaki Alessandro Cevrero Philip Brisk Chrysostomos Nicopoulos Frank K. Gürkaynak Yusuf Leblebici Paolo Ienne Design space exploration for field programmable compressor trees. 207-216 2008 CASES https://doi.org/10.1145/1450095.1450126 conf/cases/2008 db/conf/cases/cases2008.html#NiakiCBNGLI08 Theo Kluter Philip Brisk Paolo Ienne Edoardo Charbon Speculative DMA for architecturally visible storage in instruction set extensions. 243-248 2008 CODES+ISSS https://doi.org/10.1145/1450135.1450191 conf/codes/2008 db/conf/codes/codes2008.html#KluterBIC08 Ajay Kumar Verma Philip Brisk Paolo Ienne Variable Latency Speculative Addition: A New Paradigm for Arithmetic Circuit Design. 1250-1255 2008 DATE https://doi.org/10.1109/DATE.2008.4484850 https://doi.ieeecomputersociety.org/10.1109/DATE.2008.4484850 https://doi.org/10.1145/1403375.1403679 conf/date/2008 db/conf/date/date2008.html#VermaBI08 Hadi Parandeh-Afshar Philip Brisk Paolo Ienne Improving Synthesis of Compressor Trees on FPGAs via Integer Linear Programming. 1256-1261 2008 DATE https://doi.org/10.1109/DATE.2008.4484851 https://doi.ieeecomputersociety.org/10.1109/DATE.2008.4484851 https://doi.org/10.1145/1403375.1403680 conf/date/2008 db/conf/date/date2008.html#Parandeh-AfsharBI08 Francesco Regazzoni 0001 Thomas Eisenbarth 0001 Luca Breveglieri Paolo Ienne Israel Koren Can Knowledge Regarding the Presence of Countermeasures Against Fault Attacks Simplify Power Attacks on Cryptographic Devices?. 202-210 2008 DFT https://doi.org/10.1109/DFT.2008.53 https://doi.ieeecomputersociety.org/10.1109/DFT.2008.53 conf/dft/2008 db/conf/dft/dft2008.html#RegazzoniEBIK08 Hadi Parandeh-Afshar Philip Brisk Paolo Ienne A novel FPGA logic block for improved arithmetic performance. 171-180 2008 FPGA https://doi.org/10.1145/1344671.1344698 https://www.wikidata.org/entity/Q130877662 conf/fpga/2008 db/conf/fpga/fpga2008.html#Parandeh-AfsharBI08 Alessandro Cevrero Panagiotis Athanasopoulos Hadi Parandeh-Afshar Ajay Kumar Verma Philip Brisk Frank K. Gürkaynak Yusuf Leblebici Paolo Ienne Architectural improvements for field programmable counter arrays: enabling efficient synthesis of fast compressor trees on FPGAs. 181-190 2008 FPGA https://doi.org/10.1145/1344671.1344699 conf/fpga/2008 db/conf/fpga/fpga2008.html#CevreroAPVBGLI08 Maurizio Skerlj Paolo Ienne Error Protected Data Bus Inversion Using Standard DRAM Components. 35-42 2008 ISQED https://doi.org/10.1109/ISQED.2008.4479694 https://doi.ieeecomputersociety.org/10.1109/ISQED.2008.74 conf/isqed/2008 db/conf/isqed/isqed2008.html#SkerljI08

Partha Biswas Nikil D. Dutt Laura Pozzi 0001 Paolo Ienne Introduction of Architecturally Visible Storage in Instruction Set Extensions. 435-446 2007 26 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 3 https://doi.org/10.1109/TCAD.2006.890582 db/journals/tcad/tcad26.html#BiswasDPI07

Ajay Kumar Verma Paolo Ienne Improving XOR-Dominated Circuits by Exploiting Dependencies between Operands. 601-608 2007 conf/aspdac/2007 ASP-DAC https://doi.org/10.1109/ASPDAC.2007.358052 https://doi.ieeecomputersociety.org/10.1109/ASPDAC.2007.358052 http://dl.acm.org/citation.cfm?id=1323458 db/conf/aspdac/aspdac2007.html#VermaI07 Ajay Kumar Verma Philip Brisk Paolo Ienne Rethinking custom ISE identification: a new processor-agnostic method. 125-134 2007 conf/cases/2007 CASES https://doi.org/10.1145/1289881.1289905 db/conf/cases/cases2007.html#VermaBI07 Philip Brisk Ajay Kumar Verma Paolo Ienne An optimistic and conservative register assignment heuristic for chordal graphs. 209-217 2007 conf/cases/2007 CASES https://doi.org/10.1145/1289881.1289919 db/conf/cases/cases2007.html#BriskVI07 Philip Brisk Ajay Kumar Verma Paolo Ienne Hadi Parandeh-Afshar Enhancing FPGA Performance for Arithmetic Circuits. 334-337 2007 conf/dac/2007 DAC https://doi.org/10.1145/1278480.1278565 db/conf/dac/dac2007.html#BriskVIP07 Ajay Kumar Verma Philip Brisk Paolo Ienne Progressive Decomposition: A Heuristic to Structure Arithmetic Circuits. 404-409 2007 conf/dac/2007 DAC https://doi.org/10.1145/1278480.1278585 db/conf/dac/dac2007.html#VermaBI07 Ajay Kumar Verma Paolo Ienne Automatic synthesis of compressor trees: reevaluating large counters. 443-448 2007 conf/date/2007 DATE https://doi.org/10.1109/DATE.2007.364632 https://doi.ieeecomputersociety.org/10.1109/DATE.2007.364632 http://dl.acm.org/citation.cfm?id=1266461 db/conf/date/date2007.html#VermaI07 Francesco Regazzoni 0001 Thomas Eisenbarth 0001 Johann Großschädl Luca Breveglieri Paolo Ienne Israel Koren Christof Paar Power Attacks Resistance of Cryptographic S-Boxes with Added Error Detection Circuits. 508-516 2007 DFT https://doi.org/10.1109/DFT.2007.61 https://doi.ieeecomputersociety.org/10.1109/DFT.2007.61 conf/dft/2007 db/conf/dft/dft2007.html#RegazzoniEGBIKP07 Philip Brisk Ajay Kumar Verma Paolo Ienne Optimal polynomial-time interprocedural register allocation for high-level synthesis and ASIP design. 172-179 2007 conf/iccad/2007 ICCAD https://doi.org/10.1109/ICCAD.2007.4397262 https://doi.ieeecomputersociety.org/10.1109/ICCAD.2007.4397262 https://dl.acm.org/citation.cfm?id=1326109 db/conf/iccad/iccad2007.html#BriskVI07 Frederic Worm Patrick Thiran Paolo Ienne Optimizing Checking-Logic for Reliability-Agnostic Control of Self-Calibrating Designs. 861-866 2007 conf/isqed/2007 ISQED https://doi.org/10.1109/ISQED.2007.113 https://doi.ieeecomputersociety.org/10.1109/ISQED.2007.113 db/conf/isqed/isqed2007.html#WormTI07 Francesco Regazzoni 0001 Stéphane Badel Thomas Eisenbarth 0001 Johann Großschädl Axel Poschmann Zeynep Toprak Deniz Marco Macchetti Laura Pozzi 0001 Christof Paar Yusuf Leblebici Paolo Ienne A Simulation-Based Methodology for Evaluating the DPA-Resistance of Cryptographic Functional Units with Application to CMOS and MCML Technologies. 209-214 2007 conf/samos/2007ic ICSAMOS https://doi.org/10.1109/ICSAMOS.2007.4285753 db/conf/samos/samos2007ic.html#RegazzoniBEGPDMPPLI07

Partha Biswas Sudarshan Banerjee Nikil D. Dutt Laura Pozzi 0001 Paolo Ienne ISEGEN: Generation of High-Quality Instruction Set Extensions by Iterative Improvement http://arxiv.org/abs/0710.4820 2007 CoRR abs/0710.4820 db/journals/corr/corr0710.html#abs-0710-4820

Laura Pozzi 0001 Kubilay Atasu Paolo Ienne Exact and approximate algorithms for the extension of embedded processor instruction sets. 1209-1229 2006 25 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7 https://doi.org/10.1109/TCAD.2005.855950 db/journals/tcad/tcad25.html#PozziAI06

Partha Biswas Sudarshan Banerjee Nikil D. Dutt Laura Pozzi 0001 Paolo Ienne ISEGEN: an iterative improvement-based ISE generation technique for fast customization of processors. 754-762 2006 14 IEEE Trans. Very Large Scale Integr. Syst. 7 https://doi.org/10.1109/TVLSI.2006.878345 db/journals/tvlsi/tvlsi14.html#BiswasBDPI06

Miljan Vuletic Laura Pozzi 0001 Paolo Ienne Virtual memory window for application-specific reconfigurable coprocessors. 910-915 2006 14 IEEE Trans. Very Large Scale Integr. Syst. 8 https://doi.org/10.1109/TVLSI.2006.878481 db/journals/tvlsi/tvlsi14.html#VuleticPI06

Ajay Kumar Verma Paolo Ienne Towards the automatic exploration of arithmetic-circuit architectures. 445-450 2006 conf/dac/2006 DAC https://doi.org/10.1145/1146909.1147027 db/conf/dac/dac2006.html#VermaI06 Partha Biswas Nikil D. Dutt Paolo Ienne Laura Pozzi 0001 Automatic identification of application-specific functional units with architecturally visible storage. 212-217 2006 conf/date/2006p DATE https://doi.org/10.1109/DATE.2006.244088 https://doi.ieeecomputersociety.org/10.1109/DATE.2006.244088 http://dl.acm.org/citation.cfm?id=1131542 db/conf/date/date2006p.html#BiswasDIP06 Johann Großschädl Paolo Ienne Laura Pozzi 0001 Stefan Tillich Ajay Kumar Verma Combining algorithm exploration with instruction set design: a case study in elliptic curve cryptography. 218-223 2006 conf/date/2006p DATE https://doi.org/10.1109/DATE.2006.244089 https://doi.ieeecomputersociety.org/10.1109/DATE.2006.244089 http://dl.acm.org/citation.cfm?id=1131543 db/conf/date/date2006p.html#GrossschadlIPTV06 Miljan Vuletic Paolo Ienne Christopher Claus Walter Stechele Multithreaded virtual-memory-enabled reconfigurable hardware accelerators. 197-204 2006 FPT https://doi.org/10.1109/FPT.2006.270312 conf/fpt/2006 db/conf/fpt/fpt2006.html#VuleticICS06 Frederic Worm Patrick Thiran Paolo Ienne Designing Robust Checkers in the Presence of Massive Timing Errors. 281-286 2006 conf/iolts/2006 IOLTS https://doi.org/10.1109/IOLTS.2006.22 https://doi.ieeecomputersociety.org/10.1109/IOLTS.2006.22 db/conf/iolts/iolts2006.html#WormTI06 Mehmet Derin Harmanci Nuria Pazos Paolo Ienne Yusuf Leblebici A Predictable Communication Scheme for Embedded Multiprocessor Systems. 152-157 2006 conf/vlsi/2006soc VLSI-SoC https://doi.org/10.1109/VLSISOC.2006.313225 db/conf/vlsi/vlsisoc2006.html#HarmanciPIL06 Partha Biswas Sudarshan Banerjee Nikil D. Dutt Paolo Ienne Laura Pozzi 0001 Performance and Energy Benefits of Instruction Set Extensions in an FPGA Soft Core. 651-656 2006 conf/vlsid/2006 VLSI Design https://doi.org/10.1109/VLSID.2006.131 https://doi.ieeecomputersociety.org/10.1109/VLSID.2006.131 db/conf/vlsid/vlsid2006.html#BiswasBDIP06

Miljan Vuletic Laura Pozzi 0001 Paolo Ienne Seamless Hardware-Software Integration in Reconfigurable Computing Systems. 102-113 2005 22 IEEE Des. Test Comput. 2 https://doi.org/10.1109/MDT.2005.44 http://doi.ieeecomputersociety.org/10.1109/MDT.2005.44 db/journals/dt/dt22.html#VuleticPI05

Frederic Worm Paolo Ienne Patrick Thiran Giovanni De Micheli A robust self-calibrating transmission scheme for on-chip networks. 126-139 2005 13 IEEE Trans. Very Large Scale Integr. Syst. 1 https://doi.org/10.1109/TVLSI.2004.834241 https://www.wikidata.org/entity/Q59452752 db/journals/tvlsi/tvlsi13.html#WormITM05

Frederic Worm Patrick Thiran Paolo Ienne A Unified Coding Framework for Delay-Insensitivity. 201-211 2005 conf/async/2005 ASYNC https://doi.org/10.1109/ASYNC.2005.8 https://doi.ieeecomputersociety.org/10.1109/ASYNC.2005.8 db/conf/async/async2005.html#WormTI05 Laura Pozzi 0001 Paolo Ienne Exploiting pipelining to relax register-file port constraints of instruction-set extensions. 2-10 2005 conf/cases/2005 CASES https://doi.org/10.1145/1086297.1086300 db/conf/cases/cases2005.html#PozziI05 Miljan Vuletic Christophe Dubach Laura Pozzi 0001 Paolo Ienne Enabling unrestricted automated synthesis of portable hardware accelerators for virtual machines. 243-248 2005 conf/codes/2005 CODES+ISSS https://doi.org/10.1145/1084834.1084896 https://www.wikidata.org/entity/Q131119508 db/conf/codes/codes2005.html#VuleticDPI05 Partha Biswas Sudarshan Banerjee Nikil D. Dutt Laura Pozzi 0001 Paolo Ienne ISEGEN: Generation of High-Quality Instruction Set Extensions by Iterative Improvement. 1246-1251 2005 conf/date/2005 DATE https://doi.org/10.1109/DATE.2005.191 https://doi.ieeecomputersociety.org/10.1109/DATE.2005.191 http://dl.acm.org/citation.cfm?id=1049306 db/conf/date/date2005.html#BiswasBDPI05 Soner Yaldiz Alper Demir 0001 Serdar Tasiran Paolo Ienne Yusuf Leblebici Characterizing and Exploiting Task-Load Variability and Correlation for Energy Management in multi-core systems. 135-140 2005 conf/estimedia/2005 ESTIMedia https://doi.org/10.1109/ESTMED.2005.1518092 https://doi.ieeecomputersociety.org/10.1109/ESTMED.2005.1518092 https://www.wikidata.org/entity/Q57896915 db/conf/estimedia/estimedia2005.html#YaldizDTIL05 Mehmet Derin Harmanci Nuria Pazos Escudero Yusuf Leblebici Paolo Ienne Quantitative modelling and comparison of communication schemes to guarantee quality-of-service in networks-on-chip. 1782-1785 2005 conf/iscas/2005 ISCAS (2) https://doi.org/10.1109/ISCAS.2005.1464954 db/conf/iscas/iscas2005-2.html#HarmanciELI05 Frederic Worm Paolo Ienne Patrick Thiran Giovanni De Micheli Self-calibrating networks-on-chip. 2361-2364 2005 conf/iscas/2005 ISCAS (3) https://doi.org/10.1109/ISCAS.2005.1465099 db/conf/iscas/iscas2005-3.html#WormITM05

Frederic Worm Paolo Ienne Patrick Thiran Giovanni De Micheli On-Chip Self-Calibrating Communication Techniques Robust to Electrical Parameter Variations. 524-535 2004 21 IEEE Des. Test Comput. 6 https://doi.org/10.1109/MDT.2004.96 http://doi.ieeecomputersociety.org/10.1109/MDT.2004.96 db/journals/dt/dt21.html#WormITM04

Marc Epalza Paolo Ienne Daniel Mlynek Adding Limited Reconfigurability to Superscalar Processors. 53-62 2004 conf/IEEEpact/2004 IEEE PACT https://doi.ieeecomputersociety.org/10.1109/PACT.2004.10023 db/conf/IEEEpact/IEEEpact2004.html#EpalzaIM04 Marc Epalza Paolo Ienne Daniel Mlynek Dynamic Reallocation of Functional Units in Superscalar Processors. 185-198 https://doi.org/10.1007/978-3-540-30102-8_16 2004 conf/aPcsac/2004 Asia-Pacific Computer Systems Architecture Conference db/conf/aPcsac/aPcsac2004.html#EpalzaIM04 Miljan Vuletic Laura Pozzi 0001 Paolo Ienne Programming Transparency and Portable Hardware Interfacing: Towards General-Purpose Reconfigurable Computing. 339-351 2004 conf/asap/2004 ASAP https://doi.ieeecomputersociety.org/10.1109/ASAP.2004.10028 db/conf/asap/asap2004.html#VuleticPI04 Partha Biswas Vinay Choudhary Kubilay Atasu Laura Pozzi 0001 Paolo Ienne Nikil D. Dutt Introduction of local memory elements in instruction set extensions. 729-734 2004 conf/dac/2004 DAC https://doi.org/10.1145/996566.996765 db/conf/dac/dac2004.html#BiswasCAPID04 Miljan Vuletic Laura Pozzi 0001 Paolo Ienne Virtual memory window for application-specific reconfigurable coprocessors. 948-953 2004 conf/dac/2004 DAC https://doi.org/10.1145/996566.996818 db/conf/dac/dac2004.html#VuleticPI04 Miljan Vuletic Ludovic Righetti Laura Pozzi 0001 Paolo Ienne Operating System Support for Interface Virtualisation of Reconfigurable Coprocessors. 748 2004 conf/date/2004 DATE https://doi.org/10.1109/DATE.2004.1268960 https://doi.ieeecomputersociety.org/10.1109/DATE.2004.1268960 http://dl.acm.org/citation.cfm?id=969016 db/conf/date/date2004-1.html#VuleticRPI04 Paolo Ienne Ajay Kumar Verma Arithmetic Transformations to Maximise the Use of Compressor Trees. 219-224 2004 conf/delta/2004 DELTA https://doi.org/10.1109/DELTA.2004.10054 https://doi.ieeecomputersociety.org/10.1109/DELTA.2004.10054 db/conf/delta/delta2004.html#IenneV04 Miljan Vuletic Laura Pozzi 0001 Paolo Ienne Virtual Memory Window for a Portable Reconfigurable Cryptography Coprocessor. 24-33 2004 conf/fccm/2004 FCCM https://doi.org/10.1109/FCCM.2004.62 https://doi.ieeecomputersociety.org/10.1109/FCCM.2004.62 db/conf/fccm/fccm2004.html#VuleticPI04 Miljan Vuletic Laura Pozzi 0001 Paolo Ienne Dynamic Prefetching in the Virtual Memory Window of Portable Reconfigurable Coprocessors. 596-605 https://doi.org/10.1007/978-3-540-30117-2_61 2004 conf/fpl/2004 FPL db/conf/fpl/fpl2004.html#VuleticPI04 Frederic Worm Paolo Ienne Patrick Thiran Soft self-synchronising codes for self-calibrating communication. 440-447 2004 conf/iccad/2004 ICCAD https://doi.org/10.1109/ICCAD.2004.1382617 https://doi.ieeecomputersociety.org/10.1109/ICCAD.2004.1382617 https://dl.acm.org/citation.cfm?id=1112311 db/conf/iccad/iccad2004.html#WormIT04 Ajay Kumar Verma Paolo Ienne Improved use of the carry-save representation for the synthesis of complex arithmetic circuits. 791-798 2004 conf/iccad/2004 ICCAD https://doi.org/10.1109/ICCAD.2004.1382683 https://doi.ieeecomputersociety.org/10.1109/ICCAD.2004.1382683 https://dl.acm.org/citation.cfm?id=1112362 db/conf/iccad/iccad2004.html#VermaI04 Mehmet Derin Harmanci Nuria Pazos Escudero Yusuf Leblebici Paolo Ienne Providing QoS to connection-less packet-switched NoC by implementing DiffServ functionalities. 37-40 2004 SoC https://doi.org/10.1109/ISSOC.2004.1411140 conf/issoc/2004 db/conf/issoc/issoc2004.html#HarmanciELI04 Diviya Jain Anshul Kumar Laura Pozzi 0001 Paolo Ienne Automatically Customising VLIW Architectures with Coarse Grained Application-Specific Functional Units. 17-32 https://doi.org/10.1007/978-3-540-30113-4_3 2004 conf/scopes/2004 SCOPES db/conf/scopes/scopes2004.html#JainKPI04

Kubilay Atasu Laura Pozzi 0001 Paolo Ienne Automatic Application-Specific Instruction-Set Extensions Under Microarchitectural Constraints. 411-428 2003 31 Int. J. Parallel Program. 6 https://doi.org/10.1023/B:IJPP.0000004508.14594.b9 db/journals/ijpp/ijpp31.html#AtasuPI03

Armita Peymandoust Laura Pozzi 0001 Paolo Ienne Giovanni De Micheli Automatic Instruction Set Extension and Utilization for Embedded Processors. 108- 2003 conf/asap/2003 ASAP https://doi.org/10.1109/ASAP.2003.1212834 https://doi.ieeecomputersociety.org/10.1109/ASAP.2003.1212834 https://www.wikidata.org/entity/Q59452758 db/conf/asap/asap2003.html#PeymandoustPIM03 Kubilay Atasu Laura Pozzi 0001 Paolo Ienne Automatic application-specific instruction-set extensions under microarchitectural constraints. 256-261 2003 conf/dac/2003 DAC https://doi.org/10.1145/775832.775897 db/conf/dac/dac2003.html#AtasuPI03 Laura Pozzi 0001 Miljan Vuletic Paolo Ienne Automatic Topology-Based Identification of Instruction-Set Extensions for Embedded Processors. 1138 2002 conf/date/2002 DATE https://doi.org/10.1109/DATE.2002.998496 https://doi.ieeecomputersociety.org/10.1109/DATE.2002.998496 http://dl.acm.org/citation.cfm?id=874468 db/conf/date/date2002.html#PozziVI02 M. Balakrishnan Anshul Kumar Paolo Ienne Anup Gangwar Bhuvan Middha A Trimaran Based Framework for Exploring the Design Space of VLIW ASIPs with Coarse Grain Functional Units. 2-7 2002 conf/isss/2002 ISSS https://doi.ieeecomputersociety.org/10.1109/ISSS.2002.1227143 https://doi.org/10.1145/581199.581203 db/conf/isss/isss2002.html#BalakrishnanKIGM02 Paolo Ienne Patrick Thiran Giovanni De Micheli Frederic Worm An Adaptive Low-Power Transmission Scheme for On-Chip Networks. 92-100 2002 conf/isss/2002 ISSS https://doi.ieeecomputersociety.org/10.1109/ISSS.2002.1227158 https://doi.org/10.1145/581199.581221 db/conf/isss/isss2002.html#IenneTMW02 Paolo Ienne Alexander Grießing Practical Experiences with Standard-Cell Based Datapath Design Tools: Do We Really Need Regular Layouts? 396-401 1998 conf/dac/1998 DAC https://doi.org/10.1145/277044.277152 db/conf/dac/dac98.html#IenneG98

Paolo Ienne Patrick Thiran Nikolaos Vassilas Modified self-organizing feature map algorithms for efficient digital hardware implementation. 315-330 1997 8 IEEE Trans. Neural Networks 2 https://doi.org/10.1109/72.557669 https://www.wikidata.org/entity/Q39833118 db/journals/tnn/tnn8.html#IenneTV97

Paolo Ienne Digital Connectionist Hardware: Current Problems and Future Challenges. 688-713 1997 conf/iwann/1997 IWANN db/conf/iwann/iwann1997.html#Ienne97 https://doi.org/10.1007/BFb0032529

Thierry Cornu Paolo Ienne Dagmar Niebur Patrick Thiran Marc A. Viredaz Design, Implementation, and Test of a Multi-Model Systolic Neural-Network Accelerator. 47-61 1996 5 Sci. Program. 1 https://doi.org/10.1155/1996/189626 http://content.iospress.com/articles/scientific-programming/spr5-1-06 db/journals/sp/sp5.html#CornuINTV96

Paolo Ienne Thierry Cornu Gary Kuhn Special-purpose digital hardware for neural networks: An architectural survey. 5-25 1996 13 J. VLSI Signal Process. 1 https://doi.org/10.1007/BF00930664 db/journals/vlsisp/vlsisp13.html#IenneCK96

Nikolaos Vassilas Patrick Thiran Paolo Ienne On modifications of Kohonen's feature map algorithm for an efficient parallel implementation. 932-937 1996 ICNN https://doi.org/10.1109/ICNN.1996.549022 conf/icnn/1996 db/conf/icnn/icnn1996.html#VassilasTI96

Paolo Ienne Marc A. Viredaz GENES IV: A bit-serial processing element for a multi-model neural-network accelerator. 257-273 1995 9 J. VLSI Signal Process. 3 https://doi.org/10.1007/BF02407088 db/journals/vlsisp/vlsisp9.html#IenneV95

Paolo Ienne Horizontal Microcode Compaction for Programmable Systolic Accelerators. 85- 1995 conf/asap/1995 ASAP https://doi.org/10.1109/ASAP.1995.522908 https://doi.ieeecomputersociety.org/10.1109/ASAP.1995.522908 db/conf/asap/asap1995.html#Ienne95

Paolo Ienne Marc A. Viredaz Bit-Serial Multipliers and Squarers. 1445-1450 1994 43 IEEE Trans. Computers 12 db/journals/tc/tc43.html#IenneV94 https://doi.org/10.1109/12.338107 http://doi.ieeecomputersociety.org/10.1109/12.338107

Paolo Ienne Marc A. Viredaz GENES IV: A bit-serial processing element for a built-model neural-network accelerator. 345-356 1993 ASAP https://doi.org/10.1109/ASAP.1993.397157 conf/asap/1993 db/conf/asap/asap1993.html#IenneV93 Francesco Mondada Edoardo Franzi Paolo Ienne Mobile Robot Miniaturisation: A Tool for Investigation in Control Algorithms. 501-513 1993 conf/iser/1993 ISER db/conf/iser/iser1993.html#MondadaFI93 https://doi.org/10.1007/BFb0027617 https://www.wikidata.org/entity/Q56401208 Karl Aberer Michael Adler Ubaid Ahmad Alexandre Alahi Sara El Alaoui Yannick Calvino Alonso Luca G. AmarùLuca Gaetano Amarù Jason Helge AndersonJason Anderson 0001 João Andrade David Andrews 0001 Elisardo Antelo Charalampos Antoniadis Christos D. Antonopoulos Toni Abi Aoun Armita Ardeshiricham Hossein Asadi 0001 Mikhail Asiatici Kubilay Atasu Panagiotis Athanasopoulos Seyed-Hosein Attarzadeh-Niaki Stéphane Badel M. Balakrishnan Mohammadreza Banaei Sudarshan Banerjee Deniz Bayazit Ali Galip Bayrak Andrew Becker Freya Behrens Cemalettin BelentepeCemalettin Cem Belentepe Bilel Belhadj Nikolaos Bellas Hind Benbihi Rene BeuchatRené Beuchat Atri Bhattacharyya Partha Biswas Anne-Florence Bitbol Thomas Blanchard Jovan Blanusa Marin Bonnassies Beatriz Borges Antoine Bosselut Menzo Bouaissi Thomas Bourgeat Jani Boutellier Matthieu Bovel Robert K. Brayton Luca Breveglieri Philip Brisk Kevin J. Brown Étienne Bruno Andreas Peter BurgAndreas Burg 0001 Wayne P. Burleson Samuel Burri Timothée Callens Martina Camaioni George Candea Giuseppe Carleo Julien de Castelnau Francky Catthoor Joseph R. Cavallaro Michele Ceriotti Volkan Cevher Alessandro Cevrero Jean-Cédric Chappelier Edoardo Charbon Tianshi Chen 0002 Yunji Chen Zeming Chen 0001 Jianyi Cheng Alberto Silvio Chiappa Yuri Cho Vinay Choudhary Zhufei Chu Christopher Claus George A. Constantinides Thierry Cornu Jordi Cortadella Louis Coulon Gabor Csordas Leello Tadesse DadiLeello Dadi Alper Demir 0001 Jiachao Deng Zeynep Toprak Deniz Zidong Du Christophe Dubach Nikil D. Dutt Negar Foroutan EghlidiNegar Foroutan Thomas Eisenbarth 0001 Ayatallah Elakhras Marc Epalza Milos D. Ercegovac Martin Erhart Nestoras E. EvmorfopoulosNestor E. Evmorfopoulos Mohsen Ewaida Suhaib A. Fahmy Boi Faltings Dongrui Fan Lingjun Fan Simin Fan Yuntan Fang Nazanin Farahpour Robert Fasthuber Claudio Favi Xiaobing Feng 0002 Gabriel Falcão Paiva FernandesGabriel Falcão 0001 Nicolas Flammarion Edoardo Franzi Jibril Frej Sacha Friedli Jean-Marie Fürbringer Pierre-Emmanuel Gaillardon Sankalp Gambhir Anup Gangwar Silin Gao Michael Gastpar Nithin George Puck van Gerwen Radhika Ghosal Alexander Grießing Johann Großschädl Rachid Guerraoui Andrea Guerrieri Srijeet Guha Qi Guo 0001 Frank K. Gürkaynak Frank Hannig Mehmet Derin Harmanci Cécile Hébert Pierre Hellich Yann Herklotz Florian Hofhammer David Hough 0001 Wei Hu 0008 Jing Huang Yuanjie Huang Zhihong Huang Eddie Hung Mete Ismayilzada Martin Jaggi Diviya Jain Andrej Janchevski Patrick Jermann Qing Ji Zhenghong Jiang Shuai Jiao Xavier Jimenez Barbara Jobstmann Lana Josipovic Georgios Karakonstantis Kimon Karras Tanja Käser Sahand Kashani-Akhavan Sanidhya Kashyap Ryan Kastner Behnam Khaleghi Theo Kluter Israel Koren Anastasiia Kucherenko Gary Kuhn Anshul Kumar Viktor Kuncak Chris Lavin Yusuf Leblebici HyoukJoong Lee Guy LemieuxGuy G. F. Lemieux Olivier Lévêque Huawei Li 0001 Ling Li 0001 Wei Li 0008 Xiaowei Li 0001 Colin Yu Lin Wei Lin 0004 Yu Lin Clarence Linden Shaoli Liu Pasquale Lombardi Manana Lortkipanidze Tao Luo Marco Macchetti Damian Maiorano Djordje Maksimovic Sepideh Mamooler François Maréchal Axel Marmet Alexander Mathis Giovanni De Micheli Bhuvan Middha Alan Mishchenko Daniel Mlynek Yehdhih Ould Mohammed Moctar Francesco Mondada Syrielle Montariol Dejun Mu Walid A. Najjar Tanya Nazaretzky Arkosnato Neogy Seyed Parsa Neshaei Chrysostomos Nicopoulos Dagmar Niebur Stefan Nikolic 0001 David Novo Martin Odersky Kunle Olukotun Giacomo Orsi Muhsen Owaida Christof Paar Arun Paidimarri Yueyang Pan Hadi Parandeh-Afshar Ioannis Parnassos Debjit Paul Kolin Paul Mathias Payer Nuria PazosNuria Pazos Escudero Jean-Philippe Pellet Gabriel Pescia Ana Petkovska Peter Petrov Armita Peymandoust Valerio Piazza Giovanni Piccioli Manuela Pineros-Rodriguez Rouzbeh Pirayadi Solal Pirelli Axel Poschmann Nagaraju Pothineni Laura Pozzi 0001 Frederico Pratas Madhura Purnaprajna Aleksandra Radenovic Adham Ragab Martin Rajman Lucas Ramirez Aanjhan Ranganathan Francesco Regazzoni 0001 Manoel Horta Ribeiro Ludovic Righetti Geovani Rizk Carmine Rizzi Nuno Roma Angelika Romanou Tiark Rompf Alireza Sakhaeirad Marcel Salathé Francesco Salvi Lazar Saranovac Hamid Sarbazi-Azad Riya Sawhney Alexandre Schöpfer Philippe Schwaller Micheal Schwander Antonio Sclocchi Philippe Servant Hadrien Sevel Mohamed Shahawy Shabnam Sheikhha Vítor Silva 0001Vítor Manuel Mendes da Silva Viesturs Simanis Maurizio Skerlj Panagiotis Skrimponis Mathias Soeken Canberk Sönmez Anna Sotnikova Leonel Sousa Georgios I. Stamoulis François-Xavier Standaert Walter Stechele Baruch Sterin Lucas Stoffl Radu Stoica Mirjana Stojilovic Arvind K. Sujeeth Ninghui Sun Ola Svensson Earl E. Swartzlander Jr. Yu Tai Jean-Pierre Talpin Xifan Tang Serdar Tasiran Olivier Temam Alexandre F. Tenca Patrick Thiran Anja Tiede Stefan Tillich Zsolt Tokei Pedro Tomás Nigel P. Topham Emanuele Troiani Kaihui Tu Devis Tuia I. Tzimi Nikolaos Vassilas Nikola Velickovic Andreas G. Veneris Ajay Kumar Verma Amit Verma 0002 João Vieira Kizheppatt Vipin Marc A. Viredaz Miljan Vuletic Da Wang Ying Wang 0001 Xing Wei Gail Weiss Robert West 0001 Isaac John Wetenkamp John Wickerson Frederic Worm Chengyong Wu Matthieu Wyart Yinshui Xia Jiahui Xu Soner Yaldiz Haigang Yang Liqun Yang Sadegh Yazdanshenas Xiaochun Ye Nan Yuan Lenka Zdeborová Grace Zgheib Lunkai Zhang Mingzhe Zhang Zhiru Zhang Yi Zhu Georgios Zindros Marcela Zuluaga